LLVM 20.0.0git
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Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this: More...
#include "SIFixSGPRCopies.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/ADT/SetOperations.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/InitializePasses.h"
#include "llvm/Target/TargetMachine.h"
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "si-fix-sgpr-copies" |
Variables | |
static cl::opt< bool > | EnableM0Merge ("amdgpu-enable-merge-m0", cl::desc("Merge and hoist M0 initializations"), cl::init(true)) |
DEBUG_TYPE | |
SI Fix SGPR | copies |
SI Fix SGPR | false |
Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this:
Register Class <vsrc> is the union of <vgpr> and <sgpr>
BB0: %0 <sgpr> = SCALAR_INST %1 <vsrc> = COPY %0 <sgpr> ... BRANCH cond BB1, BB2 BB1: %2 <vgpr> = VECTOR_INST %3 <vsrc> = COPY %2 <vgpr> BB2: %4 <vsrc> = PHI %1 <vsrc>, <bb.0>, %3 <vrsc>, <bb.1> %5 <vgpr> = VECTOR_INST %4 <vsrc>
The coalescer will begin at BB0 and eliminate its copy, then the resulting code will look like this:
BB0: %0 <sgpr> = SCALAR_INST ... BRANCH cond BB1, BB2 BB1: %2 <vgpr> = VECTOR_INST %3 <vsrc> = COPY %2 <vgpr> BB2: %4 <sgpr> = PHI %0 <sgpr>, <bb.0>, %3 <vsrc>, <bb.1> %5 <vgpr> = VECTOR_INST %4 <sgpr>
Now that the result of the PHI instruction is an SGPR, the register allocator is now forced to constrain the register class of %3 to <sgpr> so we end up with final code like this:
BB0: %0 <sgpr> = SCALAR_INST ... BRANCH cond BB1, BB2 BB1: %2 <vgpr> = VECTOR_INST %3 <sgpr> = COPY %2 <vgpr> BB2: %4 <sgpr> = PHI %0 <sgpr>, <bb.0>, %3 <sgpr>, <bb.1> %5 <vgpr> = VECTOR_INST %4 <sgpr>
Now this code contains an illegal copy from a VGPR to an SGPR.
In order to avoid this problem, this pass searches for PHI instructions which define a <vsrc> register and constrains its definition class to <vgpr> if the user of the PHI's definition register is a vector instruction. If the PHI's definition class is constrained to <vgpr> then the coalescer will be unable to perform the COPY removal from the above example which ultimately led to the creation of an illegal COPY.
Definition in file SIFixSGPRCopies.cpp.
#define DEBUG_TYPE "si-fix-sgpr-copies" |
Definition at line 78 of file SIFixSGPRCopies.cpp.
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Definition at line 277 of file SIFixSGPRCopies.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineInstr::eraseFromParent(), getCopyRegClasses(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), I, llvm::MachineInstr::isCopy(), llvm::Register::isPhysical(), isSGPRToVGPRCopy(), llvm::RegState::Kill, MI, MRI, N, SubReg, TII, TRI, and tryChangeVGPRtoSGPRinCopy().
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Definition at line 202 of file SIFixSGPRCopies.cpp.
References llvm::Register::isVirtual(), MRI, and TRI.
Referenced by foldVGPRCopyIntoRegSequence().
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Definition at line 438 of file SIFixSGPRCopies.cpp.
References llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstNonPHI(), I, MBB, and TII.
Referenced by hoistAndMergeSGPRInits().
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Definition at line 450 of file SIFixSGPRCopies.cpp.
References llvm::any_of(), assert(), B, llvm::CallingConv::C, llvm::SmallSet< T, N, C >::count(), llvm::dbgs(), llvm::MachineDominatorTree::dominates(), llvm::MachineDominatorTree::findNearestCommonDominator(), From, getFirstNonPrologue(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), I, llvm::SmallSet< T, N, C >::insert(), isReachable(), llvm::HexagonInstrInfo::isSchedulingBoundary(), LLVM_DEBUG, MBB, MI, MRI, llvm::printMBBReference(), llvm::MachineDominatorTree::properlyDominates(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineBasicBlock::splice(), TII, and TRI.
INITIALIZE_PASS_BEGIN | ( | SIFixSGPRCopiesLegacy | , |
DEBUG_TYPE | , | ||
"SI Fix SGPR copies" | , | ||
false | , | ||
false | |||
) |
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Definition at line 419 of file SIFixSGPRCopies.cpp.
References llvm::MachineDominatorTree::dominates(), From, llvm::MachineInstr::getParent(), MBB, and searchPredecessors().
Referenced by hoistAndMergeSGPRInits().
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Definition at line 356 of file SIFixSGPRCopies.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), and TII.
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Definition at line 229 of file SIFixSGPRCopies.cpp.
References TRI.
Referenced by foldVGPRCopyIntoRegSequence().
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Definition at line 222 of file SIFixSGPRCopies.cpp.
References TRI.
bool searchPredecessors | ( | const MachineBasicBlock * | MBB, |
const MachineBasicBlock * | CutOff, | ||
UnaryPredicate | Predicate | ||
) |
Definition at line 391 of file SIFixSGPRCopies.cpp.
References llvm::SmallVectorImpl< T >::append(), llvm::SmallVectorBase< Size_T >::empty(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), MBB, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::MachineBasicBlock::pred_begin(), llvm::MachineBasicBlock::pred_end(), and llvm::MachineBasicBlock::predecessors().
Referenced by isReachable().
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Definition at line 236 of file SIFixSGPRCopies.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::Register::isVirtual(), MI, MRI, TII, TRI, and UseMI.
Referenced by foldVGPRCopyIntoRegSequence().
Definition at line 190 of file SIFixSGPRCopies.cpp.
DEBUG_TYPE |
Definition at line 190 of file SIFixSGPRCopies.cpp.
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Definition at line 191 of file SIFixSGPRCopies.cpp.