38 switch (
MI.getOpcode()) {
39 case R600::INTERP_PAIR_XY:
40 case R600::INTERP_PAIR_ZW:
41 case R600::INTERP_VEC_LOAD:
52 if (
TII->isLDSRetInstr(
MI.getOpcode()))
55 if (
TII->isVector(
MI) ||
TII->isCubeOp(
MI.getOpcode()) ||
56 TII->isReductionOp(
MI.getOpcode()))
59 unsigned NumLiteral = 0;
61 E =
MI.operands_end();
64 if (MO.
isReg() && MO.
getReg() == R600::ALU_LITERAL_X)
67 return 1 + NumLiteral;
71 if (
TII->isALUInstr(
MI.getOpcode()))
73 if (
TII->isVector(
MI) ||
TII->isCubeOp(
MI.getOpcode()))
75 switch (
MI.getOpcode()) {
77 case R600::INTERP_PAIR_XY:
78 case R600::INTERP_PAIR_ZW:
79 case R600::INTERP_VEC_LOAD:
89 switch (
MI.getOpcode()) {
92 case R600::IMPLICIT_DEF:
99 std::pair<unsigned, unsigned> getAccessedBankLine(
unsigned Sel)
const {
103 return std::pair<unsigned, unsigned>(
104 ((Sel >> 2) - 512) >> 12,
110 ((((Sel >> 2) - 512) & 4095) >> 5) << 1);
115 std::vector<std::pair<unsigned, unsigned>> &CachedConsts,
116 bool UpdateInstr =
true)
const {
117 std::vector<std::pair<unsigned, unsigned>> UsedKCache;
119 if (!
TII->isALUInstr(
MI.getOpcode()) &&
MI.getOpcode() != R600::DOT_4)
125 (
TII->isALUInstr(
MI.getOpcode()) ||
MI.getOpcode() == R600::DOT_4) &&
126 "Can't assign Const");
127 for (
auto &[
Op, Sel] : Consts) {
128 if (
Op->getReg() != R600::ALU_CONST)
130 unsigned Chan = Sel & 3,
Index = ((Sel >> 2) - 512) & 31;
131 unsigned KCacheIndex =
Index * 4 + Chan;
132 const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
133 if (CachedConsts.empty()) {
134 CachedConsts.push_back(BankLine);
135 UsedKCache.emplace_back(0, KCacheIndex);
138 if (CachedConsts[0] == BankLine) {
139 UsedKCache.emplace_back(0, KCacheIndex);
142 if (CachedConsts.size() == 1) {
143 CachedConsts.push_back(BankLine);
144 UsedKCache.emplace_back(1, KCacheIndex);
147 if (CachedConsts[1] == BankLine) {
148 UsedKCache.emplace_back(1, KCacheIndex);
158 for (
auto &[
Op, Sel] : Consts) {
159 if (
Op->getReg() != R600::ALU_CONST)
161 switch (UsedKCache[j].first) {
163 Op->setReg(R600::R600_KC0RegClass.getRegister(UsedKCache[j].second));
166 Op->setReg(R600::R600_KC1RegClass.getRegister(UsedKCache[j].second));
176 bool canClauseLocalKillFitInClause(
177 unsigned AluInstCount,
178 std::vector<std::pair<unsigned, unsigned>> KCacheBanks,
184 MOI =
Def->operands_begin(),
185 MOE =
Def->operands_end(); MOI != MOE; ++MOI) {
186 if (!MOI->isReg() || !MOI->isDef() ||
187 TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
192 unsigned LastUseCount = 0;
194 AluInstCount += OccupiedDwords(*UseI);
196 if (!SubstituteKCacheBank(*UseI, KCacheBanks,
false))
202 if (AluInstCount >=
TII->getMaxAlusPerClause())
211 if (UseI->readsRegister(MOI->getReg(), &
TRI))
212 LastUseCount = AluInstCount;
215 if (UseI != Def && UseI->killsRegister(MOI->getReg(), &
TRI))
219 return LastUseCount <=
TII->getMaxAlusPerClause();
228 std::vector<std::pair<unsigned, unsigned>> KCacheBanks;
229 bool PushBeforeModifier =
false;
230 unsigned AluInstCount = 0;
232 if (IsTrivialInst(*
I))
236 if (AluInstCount >
TII->getMaxAlusPerClause())
238 if (
I->getOpcode() == R600::PRED_X) {
245 if (AluInstCount > 0)
248 PushBeforeModifier =
true;
259 if (
TII->mustBeLastInClause(
I->getOpcode())) {
266 if (!canClauseLocalKillFitInClause(AluInstCount, KCacheBanks,
I, E))
269 if (!SubstituteKCacheBank(*
I, KCacheBanks))
271 AluInstCount += OccupiedDwords(*
I);
273 unsigned Opcode = PushBeforeModifier ?
274 R600::CF_ALU_PUSH_BEFORE : R600::CF_ALU;
281 .
addImm(KCacheBanks.empty()?0:KCacheBanks[0].first)
282 .
addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first)
283 .
addImm(KCacheBanks.empty()?0:2)
284 .
addImm((KCacheBanks.size() < 2)?0:2)
285 .
addImm(KCacheBanks.empty()?0:KCacheBanks[0].second)
286 .
addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second)
301 TII =
ST.getInstrInfo();
305 if (
I !=
MBB.
end() &&
I->getOpcode() == R600::CF_ALU)
309 auto next = MakeALUClause(
MBB,
I);
320 return "R600 Emit Clause Markers Pass";
324char R600EmitClauseMarkers::ID = 0;
329 "R600 Emit Clause Markers",
false,
false)
334 return new R600EmitClauseMarkers();
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Provides R600 specific target descriptions.
AMDGPU R600 specific subclass of TargetSubtarget.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
NodeAddr< DefNode * > Def
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void initializeR600EmitClauseMarkersPass(PassRegistry &)
FunctionPass * createR600EmitClauseMarkers()