llvm::TargetInstrInfo Member List
This is the complete list of members for llvm::TargetInstrInfo, including all inherited members.
| accumulateInstrSeqToRootLatency(MachineInstr &Root) const | llvm::TargetInstrInfo | inlinevirtual |
| analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const | llvm::TargetInstrInfo | inlinevirtual |
| analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const | llvm::TargetInstrInfo | inlinevirtual |
| analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const | llvm::TargetInstrInfo | inlinevirtual |
| analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const | llvm::TargetInstrInfo | inlinevirtual |
| analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const | llvm::TargetInstrInfo | inlinevirtual |
| analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const | llvm::TargetInstrInfo | inlinevirtual |
| areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const | llvm::TargetInstrInfo | inlinevirtual |
| areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const | llvm::TargetInstrInfo | inlinevirtual |
| areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const | llvm::TargetInstrInfo | |
| breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | inlinevirtual |
| buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const | llvm::TargetInstrInfo | inlinevirtual |
| buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const | llvm::TargetInstrInfo | inlinevirtual |
| canCopyGluedNodeDuringSchedule(SDNode *N) const | llvm::TargetInstrInfo | inlinevirtual |
| canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const | llvm::TargetInstrInfo | inlinevirtual |
| canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const | llvm::TargetInstrInfo | inlinevirtual |
| canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const | llvm::TargetInstrInfo | inlinevirtual |
| canPredicatePredicatedInstr(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const | llvm::TargetInstrInfo | inlinevirtual |
| CommuteAnyOperandIndex | llvm::TargetInstrInfo | static |
| commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const | llvm::TargetInstrInfo | |
| commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const | llvm::TargetInstrInfo | protectedvirtual |
| ComplexDeprecationPredicate typedef | llvm::MCInstrInfo | |
| convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const | llvm::TargetInstrInfo | inlinevirtual |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const | llvm::TargetInstrInfo | inlinevirtual |
| createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | virtual |
| createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const | llvm::TargetInstrInfo | inlinevirtual |
| createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const | llvm::TargetInstrInfo | inlinevirtual |
| CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const | llvm::TargetInstrInfo | virtual |
| CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const | llvm::TargetInstrInfo | virtual |
| CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const | llvm::TargetInstrInfo | virtual |
| CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const | llvm::TargetInstrInfo | inlinevirtual |
| CreateTargetScheduleState(const TargetSubtargetInfo &) const | llvm::TargetInstrInfo | inlinevirtual |
| decomposeMachineOperandsTargetFlags(unsigned) const | llvm::TargetInstrInfo | inlinevirtual |
| defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const | llvm::TargetInstrInfo | |
| describeLoadedValue(const MachineInstr &MI, Register Reg) const | llvm::TargetInstrInfo | virtual |
| duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const | llvm::TargetInstrInfo | virtual |
| emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const | llvm::TargetInstrInfo | inlinevirtual |
| expandPostRAPseudo(MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const | llvm::TargetInstrInfo | inlinevirtual |
| finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const | llvm::TargetInstrInfo | inlinevirtual |
| findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const | llvm::TargetInstrInfo | virtual |
| fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2) | llvm::TargetInstrInfo | protectedstatic |
| foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const | llvm::TargetInstrInfo | inlinevirtual |
| foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const | llvm::TargetInstrInfo | |
| foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const | llvm::TargetInstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const | llvm::TargetInstrInfo | inlineprotectedvirtual |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const | llvm::TargetInstrInfo | inlineprotectedvirtual |
| genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstIdxForVirtReg) const | llvm::TargetInstrInfo | virtual |
| get(unsigned Opcode) const | llvm::MCInstrInfo | inline |
| getAccumulationStartOpcode(unsigned Opcode) const | llvm::TargetInstrInfo | inlinevirtual |
| getAccumulatorChain(MachineInstr *CurrentInstr, SmallVectorImpl< Register > &Chain) const | llvm::TargetInstrInfo | |
| getAccumulatorReassociationPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns) const | llvm::TargetInstrInfo | |
| getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | inlinevirtual |
| getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const | llvm::TargetInstrInfo | inlinevirtual |
| getBranchDestBlock(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| getCalleeOperand(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| getCallFrameDestroyOpcode() const | llvm::TargetInstrInfo | inline |
| getCallFrameSetupOpcode() const | llvm::TargetInstrInfo | inline |
| getCallFrameSizeAt(MachineInstr &MI) const | llvm::TargetInstrInfo | |
| getCatchReturnOpcode() const | llvm::TargetInstrInfo | inline |
| getCombinerObjective(unsigned Pattern) const | llvm::TargetInstrInfo | virtual |
| getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const | llvm::TargetInstrInfo | inlinevirtual |
| getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info) const | llvm::MCInstrInfo | |
| getExecutionDomain(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| getExtendResourceLenLimit() const | llvm::TargetInstrInfo | inlinevirtual |
| getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const | llvm::TargetInstrInfo | |
| getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const | llvm::TargetInstrInfo | inlineprotectedvirtual |
| getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const | llvm::TargetInstrInfo | inlinevirtual |
| getFrameSize(const MachineInstr &I) const | llvm::TargetInstrInfo | inline |
| getFrameTotalSize(const MachineInstr &I) const | llvm::TargetInstrInfo | inline |
| getIncrementValue(const MachineInstr &MI, int &Value) const | llvm::TargetInstrInfo | inlinevirtual |
| getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const | llvm::TargetInstrInfo | virtual |
| getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const | llvm::TargetInstrInfo | |
| getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const | llvm::TargetInstrInfo | inlineprotectedvirtual |
| getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const | llvm::TargetInstrInfo | virtual |
| getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const | llvm::TargetInstrInfo | virtual |
| getInstructionUniformity(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| getInstSizeInBytes(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| getInverseOpcode(unsigned Opcode) const | llvm::TargetInstrInfo | inlinevirtual |
| getJumpTableIndex(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| getLiveRangeSplitOpcode(Register Reg, const MachineFunction &MF) const | llvm::TargetInstrInfo | inlinevirtual |
| getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const | llvm::TargetInstrInfo | virtual |
| getMachineCombinerTraceStrategy() const | llvm::TargetInstrInfo | virtual |
| getMachineCSELookAheadLimit() const | llvm::TargetInstrInfo | inlinevirtual |
| getMemOperandAACheckLimit() const | llvm::TargetInstrInfo | inlinevirtual |
| getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | inlinevirtual |
| getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | |
| getMIRFormatter() const | llvm::TargetInstrInfo | inlinevirtual |
| getName(unsigned Opcode) const | llvm::MCInstrInfo | inline |
| getNop() const | llvm::TargetInstrInfo | virtual |
| getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const | llvm::TargetInstrInfo | virtual |
| getNumOpcodes() const | llvm::MCInstrInfo | inline |
| getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const | llvm::TargetInstrInfo | inlinevirtual |
| getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const | llvm::TargetInstrInfo | virtual |
| getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const | llvm::TargetInstrInfo | virtual |
| getOpRegClassID(const MCOperandInfo &OpInfo) const | llvm::TargetInstrInfo | inline |
| llvm::MCInstrInfo::getOpRegClassID(const MCOperandInfo &OpInfo, unsigned HwModeId) const | llvm::MCInstrInfo | inline |
| getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const | llvm::TargetInstrInfo | inlinevirtual |
| getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const | llvm::TargetInstrInfo | inlinevirtual |
| getOutliningType(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const | llvm::TargetInstrInfo | |
| getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const | llvm::TargetInstrInfo | inlineprotectedvirtual |
| getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | inlinevirtual |
| getPatchpointUnfoldableRange(const MachineInstr &MI) const | llvm::TargetInstrInfo | virtual |
| getPredicationCost(const MachineInstr &MI) const | llvm::TargetInstrInfo | virtual |
| getReassociateOperandIndices(const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const | llvm::TargetInstrInfo | virtual |
| getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root, const MachineInstr &Prev) const | llvm::TargetInstrInfo | |
| getReduceOpcodeForAccumulator(unsigned int AccumulatorOpCode) const | llvm::TargetInstrInfo | inlinevirtual |
| getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | virtual |
| getRegClassByHwModeTable(unsigned ModeId) const | llvm::MCInstrInfo | inline |
| getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const | llvm::TargetInstrInfo | |
| getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const | llvm::TargetInstrInfo | inlineprotectedvirtual |
| getReturnOpcode() const | llvm::TargetInstrInfo | inline |
| getSerializableBitmaskMachineOperandTargetFlags() const | llvm::TargetInstrInfo | inlinevirtual |
| getSerializableDirectMachineOperandTargetFlags() const | llvm::TargetInstrInfo | inlinevirtual |
| getSerializableMachineMemOperandTargetFlags() const | llvm::TargetInstrInfo | inlinevirtual |
| getSerializableTargetIndices() const | llvm::TargetInstrInfo | inlinevirtual |
| getSPAdjust(const MachineInstr &MI) const | llvm::TargetInstrInfo | virtual |
| getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const | llvm::TargetInstrInfo | virtual |
| getTailDuplicateSize(CodeGenOptLevel OptLevel) const | llvm::TargetInstrInfo | inlinevirtual |
| getTailMergeSize(const MachineFunction &MF) const | llvm::TargetInstrInfo | inlinevirtual |
| getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | inlinevirtual |
| hasCommutePreference(MachineInstr &MI, bool &Commute) const | llvm::TargetInstrInfo | inlinevirtual |
| hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const | llvm::TargetInstrInfo | inlinevirtual |
| hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const | llvm::TargetInstrInfo | virtual |
| hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const | llvm::TargetInstrInfo | virtual |
| hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const | llvm::TargetInstrInfo | virtual |
| hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const | llvm::TargetInstrInfo | virtual |
| hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const | llvm::TargetInstrInfo | virtual |
| InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, const uint8_t *DF, const ComplexDeprecationPredicate *CDI, unsigned NO, const int16_t *RCHWTables=nullptr, int16_t NumRegClassByHwMode=0) | llvm::MCInstrInfo | inline |
| insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const | llvm::TargetInstrInfo | inlinevirtual |
| insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const | llvm::TargetInstrInfo | inlinevirtual |
| insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const | llvm::TargetInstrInfo | virtual |
| insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const | llvm::TargetInstrInfo | virtual |
| insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const | llvm::TargetInstrInfo | inlinevirtual |
| insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const | llvm::TargetInstrInfo | inlinevirtual |
| insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const | llvm::TargetInstrInfo | inline |
| isAccumulationOpcode(unsigned Opcode) const | llvm::TargetInstrInfo | inlinevirtual |
| isAddImmediate(const MachineInstr &MI, Register Reg) const | llvm::TargetInstrInfo | inlinevirtual |
| isAsCheapAsAMove(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert=false) const | llvm::TargetInstrInfo | inlinevirtual |
| isBasicBlockPrologue(const MachineInstr &MI, Register Reg=Register()) const | llvm::TargetInstrInfo | inlinevirtual |
| isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const | llvm::TargetInstrInfo | inlinevirtual |
| isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const | llvm::TargetInstrInfo | inlinevirtual |
| isCopyInstr(const MachineInstr &MI) const | llvm::TargetInstrInfo | inline |
| isCopyInstrImpl(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlineprotectedvirtual |
| isCopyLikeInstr(const MachineInstr &MI) const | llvm::TargetInstrInfo | inline |
| isCopyLikeInstrImpl(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlineprotectedvirtual |
| isExplicitTargetIndexDef(const MachineInstr &MI, int &Index, int64_t &Offset) const | llvm::TargetInstrInfo | inlinevirtual |
| isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const | llvm::TargetInstrInfo | inlinevirtual |
| isFrameInstr(const MachineInstr &I) const | llvm::TargetInstrInfo | inline |
| isFrameSetup(const MachineInstr &I) const | llvm::TargetInstrInfo | inline |
| isFullCopyInstr(const MachineInstr &MI) const | llvm::TargetInstrInfo | inline |
| isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const | llvm::TargetInstrInfo | inlinevirtual |
| isFunctionSafeToSplit(const MachineFunction &MF) const | llvm::TargetInstrInfo | virtual |
| isGenericAtomicRMWOpcode(unsigned Opc) | llvm::TargetInstrInfo | inlinestatic |
| isGenericOpcode(unsigned Opc) | llvm::TargetInstrInfo | inlinestatic |
| isGlobalMemoryObject(const MachineInstr *MI) const | llvm::TargetInstrInfo | virtual |
| isHighLatencyDef(int opc) const | llvm::TargetInstrInfo | inlinevirtual |
| isIgnorableUse(const MachineOperand &MO) const | llvm::TargetInstrInfo | inlinevirtual |
| isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const | llvm::TargetInstrInfo | inlinevirtual |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const | llvm::TargetInstrInfo | inlinevirtual |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const | llvm::TargetInstrInfo | inlinevirtual |
| isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const | llvm::TargetInstrInfo | inlinevirtual |
| isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const | llvm::TargetInstrInfo | virtual |
| isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const | llvm::TargetInstrInfo | inlinevirtual |
| isPCRelRegisterOperandLegal(const MachineOperand &MO) const | llvm::TargetInstrInfo | inlinevirtual |
| isPostIncrement(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| isPredicable(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| isPredicated(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const | llvm::TargetInstrInfo | inlinevirtual |
| isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const | llvm::TargetInstrInfo | inlinevirtual |
| isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const | llvm::TargetInstrInfo | inlinevirtual |
| isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const | llvm::TargetInstrInfo | inlinevirtual |
| isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const | llvm::TargetInstrInfo | |
| isReMaterializable(const MachineInstr &MI) const | llvm::TargetInstrInfo | inline |
| isReMaterializableImpl(const MachineInstr &MI) const | llvm::TargetInstrInfo | protectedvirtual |
| isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const | llvm::TargetInstrInfo | inlinevirtual |
| isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, MachineCycleInfo *CI) const | llvm::TargetInstrInfo | inlinevirtual |
| isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const | llvm::TargetInstrInfo | virtual |
| isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const | llvm::TargetInstrInfo | inlinevirtual |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const | llvm::TargetInstrInfo | inlinevirtual |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const | llvm::TargetInstrInfo | inlinevirtual |
| isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const | llvm::TargetInstrInfo | inlinevirtual |
| isSubregFoldable() const | llvm::TargetInstrInfo | inlinevirtual |
| isTailCall(const MachineInstr &Inst) const | llvm::TargetInstrInfo | inlinevirtual |
| isThroughputPattern(unsigned Pattern) const | llvm::TargetInstrInfo | virtual |
| isTriviallyReMaterializable(const MachineInstr &MI) const | llvm::TargetInstrInfo | inline |
| isUnconditionalTailCall(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| isUnpredicatedTerminator(const MachineInstr &MI) const | llvm::TargetInstrInfo | |
| isUnspillableTerminator(const MachineInstr *MI) const | llvm::TargetInstrInfo | inline |
| isUnspillableTerminatorImpl(const MachineInstr *MI) const | llvm::TargetInstrInfo | inlineprotectedvirtual |
| isZeroCost(unsigned Opcode) const | llvm::TargetInstrInfo | inline |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const | llvm::TargetInstrInfo | inlinevirtual |
| lowerCopy(MachineInstr *MI, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | |
| mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const | llvm::TargetInstrInfo | virtual |
| NumRegClassByHwModes | llvm::MCInstrInfo | protected |
| operator=(const TargetInstrInfo &)=delete | llvm::TargetInstrInfo | |
| optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const | llvm::TargetInstrInfo | inlinevirtual |
| optimizeCondBranch(MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const | llvm::TargetInstrInfo | virtual |
| optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const | llvm::TargetInstrInfo | inlinevirtual |
| PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const | llvm::TargetInstrInfo | virtual |
| predictBranchSizeForIfCvt(MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const | llvm::TargetInstrInfo | inlinevirtual |
| produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const | llvm::TargetInstrInfo | virtual |
| reassociateOps(MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, ArrayRef< unsigned > OperandIndices, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const | llvm::TargetInstrInfo | |
| reduceAccumulatorTree(SmallVectorImpl< Register > &RegistersToReduce, SmallVectorImpl< MachineInstr * > &InsInstrs, MachineFunction &MF, MachineInstr &Root, MachineRegisterInfo &MRI, DenseMap< Register, unsigned > &InstrIdxForVirtReg, Register ResultReg) const | llvm::TargetInstrInfo | |
| reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const | llvm::TargetInstrInfo | inlinevirtual |
| RegClassByHwMode | llvm::TargetInstrInfo | protected |
| RegClassByHwModeTables | llvm::MCInstrInfo | protected |
| reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const | llvm::TargetInstrInfo | virtual |
| removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const | llvm::TargetInstrInfo | inlinevirtual |
| replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const | llvm::TargetInstrInfo | inlinevirtual |
| ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const | llvm::TargetInstrInfo | virtual |
| reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const | llvm::TargetInstrInfo | inlinevirtual |
| setExecutionDomain(MachineInstr &MI, unsigned Domain) const | llvm::TargetInstrInfo | inlinevirtual |
| setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const | llvm::TargetInstrInfo | inlinevirtual |
| shouldBreakCriticalEdgeToSink(MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const | llvm::TargetInstrInfo | inlinevirtual |
| shouldHoist(const MachineInstr &MI, const MachineLoop *FromLoop) const | llvm::TargetInstrInfo | inlinevirtual |
| shouldOutlineFromFunctionByDefault(MachineFunction &MF) const | llvm::TargetInstrInfo | inlinevirtual |
| shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const | llvm::TargetInstrInfo | inlinevirtual |
| shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const | llvm::TargetInstrInfo | inlinevirtual |
| shouldSink(const MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| simplifyInstruction(MachineInstr &MI) const | llvm::TargetInstrInfo | inlinevirtual |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const | llvm::TargetInstrInfo | inlinevirtual |
| SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const | llvm::TargetInstrInfo | inlinevirtual |
| TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u, const int16_t *const RegClassByHwModeTable=nullptr) | llvm::TargetInstrInfo | inlineprotected |
| TargetInstrInfo(const TargetInstrInfo &)=delete | llvm::TargetInstrInfo | |
| unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, Register Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const | llvm::TargetInstrInfo | inlinevirtual |
| unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const | llvm::TargetInstrInfo | inlinevirtual |
| useMachineCombiner() const | llvm::TargetInstrInfo | inlinevirtual |
| usePreRAHazardRecognizer() const | llvm::TargetInstrInfo | |
| verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const | llvm::TargetInstrInfo | inlinevirtual |
| ~TargetInstrInfo() | llvm::TargetInstrInfo | virtual |
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