25#define GET_INSTRINFO_CTOR_DTOR
26#include "LoongArchGenInstrInfo.inc"
30 LoongArch::ADJCALLSTACKUP),
45 bool RenamableSrc)
const {
46 if (LoongArch::GPRRegClass.
contains(DstReg, SrcReg)) {
54 if (LoongArch::LSX128RegClass.
contains(DstReg, SrcReg)) {
62 if (LoongArch::LASX256RegClass.
contains(DstReg, SrcReg)) {
70 if (LoongArch::CFRRegClass.
contains(DstReg) &&
71 LoongArch::GPRRegClass.
contains(SrcReg)) {
77 if (LoongArch::GPRRegClass.
contains(DstReg) &&
78 LoongArch::CFRRegClass.
contains(SrcReg)) {
84 if (LoongArch::CFRRegClass.
contains(DstReg, SrcReg)) {
92 if (LoongArch::FPR32RegClass.
contains(DstReg, SrcReg)) {
93 Opc = LoongArch::FMOV_S;
94 }
else if (LoongArch::FPR64RegClass.
contains(DstReg, SrcReg)) {
95 Opc = LoongArch::FMOV_D;
96 }
else if (LoongArch::GPRRegClass.
contains(DstReg) &&
97 LoongArch::FPR32RegClass.
contains(SrcReg)) {
99 Opc = LoongArch::MOVFR2GR_S;
100 }
else if (LoongArch::GPRRegClass.
contains(DstReg) &&
101 LoongArch::FPR64RegClass.
contains(SrcReg)) {
103 Opc = LoongArch::MOVFR2GR_D;
121 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
122 Opcode =
TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
125 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
126 Opcode = LoongArch::FST_S;
127 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
128 Opcode = LoongArch::FST_D;
129 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
130 Opcode = LoongArch::VST;
131 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
132 Opcode = LoongArch::XVST;
133 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
134 Opcode = LoongArch::PseudoST_CFR;
159 DL =
I->getDebugLoc();
162 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
163 Opcode =
TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
166 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
167 Opcode = LoongArch::FLD_S;
168 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
169 Opcode = LoongArch::FLD_D;
170 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
171 Opcode = LoongArch::VLD;
172 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
173 Opcode = LoongArch::XVLD;
174 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
175 Opcode = LoongArch::PseudoLD_CFR;
201 for (
auto &Inst : Seq) {
203 case LoongArch::LU12I_W:
208 case LoongArch::ADDI_W:
210 case LoongArch::LU32I_D:
211 case LoongArch::LU52I_D:
217 case LoongArch::BSTRINS_D:
226 assert(
false &&
"Unknown insn emitted by LoongArchMatInt");
235 unsigned Opcode =
MI.getOpcode();
237 if (Opcode == TargetOpcode::INLINEASM ||
238 Opcode == TargetOpcode::INLINEASM_BR) {
241 return getInlineAsmLength(
MI.getOperand(0).getSymbolName(), *MAI);
244 unsigned NumBytes = 0;
250 switch (
Desc.getOpcode()) {
252 return Desc.getSize();
253 case TargetOpcode::STATEPOINT:
255 assert(NumBytes % 4 == 0 &&
"Invalid number of NOP bytes requested!");
265 const unsigned Opcode =
MI.getOpcode();
269 case LoongArch::ADDI_D:
271 case LoongArch::XORI:
272 return (
MI.getOperand(1).isReg() &&
273 MI.getOperand(1).getReg() == LoongArch::R0) ||
274 (
MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0);
276 return MI.isAsCheapAsAMove();
281 assert(
MI.getDesc().isBranch() &&
"Unexpected opcode!");
283 return MI.getOperand(
MI.getNumExplicitOperands() - 1).getMBB();
290 "Unknown conditional branch");
295 for (
int i = 0; i < NumOp - 1; i++)
303 bool AllowModify)
const {
309 if (
I ==
MBB.
end() || !isUnpredicatedTerminator(*
I))
315 int NumTerminators = 0;
316 for (
auto J =
I.getReverse(); J !=
MBB.
rend() && isUnpredicatedTerminator(*J);
319 if (J->getDesc().isUnconditionalBranch() ||
320 J->getDesc().isIndirectBranch()) {
327 if (AllowModify && FirstUncondOrIndirectBr !=
MBB.
end()) {
328 while (std::next(FirstUncondOrIndirectBr) !=
MBB.
end()) {
329 std::next(FirstUncondOrIndirectBr)->eraseFromParent();
332 I = FirstUncondOrIndirectBr;
336 if (NumTerminators == 1 &&
I->getDesc().isUnconditionalBranch()) {
342 if (NumTerminators == 1 &&
I->getDesc().isConditionalBranch()) {
348 if (NumTerminators == 2 && std::prev(
I)->getDesc().isConditionalBranch() &&
349 I->getDesc().isUnconditionalBranch()) {
360 int64_t BrOffset)
const {
368 case LoongArch::BLTU:
369 case LoongArch::BGEU:
370 return isInt<18>(BrOffset);
371 case LoongArch::BEQZ:
372 case LoongArch::BNEZ:
373 case LoongArch::BCEQZ:
374 case LoongArch::BCNEZ:
375 return isInt<23>(BrOffset);
377 case LoongArch::PseudoBR:
378 return isInt<28>(BrOffset);
388 auto MII =
MI.getIterator();
420 switch (
MI.getOpcode()) {
421 case LoongArch::PCALAU12I: {
422 auto AddI = std::next(MII);
423 if (AddI == MIE || AddI->getOpcode() != LoongArch::ADDI_D)
425 auto Lu32I = std::next(AddI);
426 if (Lu32I == MIE || Lu32I->getOpcode() != LoongArch::LU32I_D)
428 auto MO0 =
MI.getOperand(1).getTargetFlags();
429 auto MO1 = AddI->getOperand(2).getTargetFlags();
430 auto MO2 = Lu32I->getOperand(2).getTargetFlags();
447 case LoongArch::LU52I_D: {
448 auto MO =
MI.getOperand(2).getTargetFlags();
462 int *BytesRemoved)
const {
469 if (!
I->getDesc().isBranch())
475 I->eraseFromParent();
482 if (!
I->getDesc().isConditionalBranch())
488 I->eraseFromParent();
501 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
503 "LoongArch branch conditions have at most two components!");
515 for (
unsigned i = 1; i <
Cond.size(); ++i)
538 assert(RS &&
"RegScavenger required for long branching");
540 "new block should be inserted for expanding unconditional branch");
549 if (!isInt<32>(BrOffset))
551 "Branch offsets outside of the signed 32-bit range not supported");
553 Register ScratchReg =
MRI.createVirtualRegister(&LoongArch::GPRRegClass);
571 LoongArch::GPRRegClass, PCALAU12I.
getIterator(),
false,
573 if (Scav != LoongArch::NoRegister)
578 Scav = LoongArch::R20;
580 if (FrameIndex == -1)
590 TRI->eliminateFrameIndex(RestoreBB.
back(),
593 MRI.replaceRegWith(ScratchReg, Scav);
602 return LoongArch::BNE;
604 return LoongArch::BEQ;
605 case LoongArch::BEQZ:
606 return LoongArch::BNEZ;
607 case LoongArch::BNEZ:
608 return LoongArch::BEQZ;
609 case LoongArch::BCEQZ:
610 return LoongArch::BCNEZ;
611 case LoongArch::BCNEZ:
612 return LoongArch::BCEQZ;
614 return LoongArch::BGE;
616 return LoongArch::BLT;
617 case LoongArch::BLTU:
618 return LoongArch::BGEU;
619 case LoongArch::BGEU:
620 return LoongArch::BLTU;
626 assert((
Cond.size() &&
Cond.size() <= 3) &&
"Invalid branch condition!");
631std::pair<unsigned, unsigned>
633 return std::make_pair(TF, 0u);
638 using namespace LoongArchII;
640 static const std::pair<unsigned, const char *> TargetFlags[] = {
641 {MO_CALL,
"loongarch-call"},
642 {MO_CALL_PLT,
"loongarch-call-plt"},
643 {MO_PCREL_HI,
"loongarch-pcrel-hi"},
644 {MO_PCREL_LO,
"loongarch-pcrel-lo"},
645 {MO_PCREL64_LO,
"loongarch-pcrel64-lo"},
646 {MO_PCREL64_HI,
"loongarch-pcrel64-hi"},
647 {MO_GOT_PC_HI,
"loongarch-got-pc-hi"},
648 {MO_GOT_PC_LO,
"loongarch-got-pc-lo"},
649 {MO_GOT_PC64_LO,
"loongarch-got-pc64-lo"},
650 {MO_GOT_PC64_HI,
"loongarch-got-pc64-hi"},
651 {MO_LE_HI,
"loongarch-le-hi"},
652 {MO_LE_LO,
"loongarch-le-lo"},
653 {MO_LE64_LO,
"loongarch-le64-lo"},
654 {MO_LE64_HI,
"loongarch-le64-hi"},
655 {MO_IE_PC_HI,
"loongarch-ie-pc-hi"},
656 {MO_IE_PC_LO,
"loongarch-ie-pc-lo"},
657 {MO_IE_PC64_LO,
"loongarch-ie-pc64-lo"},
658 {MO_IE_PC64_HI,
"loongarch-ie-pc64-hi"},
659 {MO_DESC_PC_HI,
"loongarch-desc-pc-hi"},
660 {MO_DESC_PC_LO,
"loongarch-desc-pc-lo"},
661 {MO_DESC64_PC_LO,
"loongarch-desc64-pc-lo"},
662 {MO_DESC64_PC_HI,
"loongarch-desc64-pc-hi"},
663 {MO_DESC_LD,
"loongarch-desc-ld"},
664 {MO_DESC_CALL,
"loongarch-desc-call"},
665 {MO_LD_PC_HI,
"loongarch-ld-pc-hi"},
666 {MO_GD_PC_HI,
"loongarch-gd-pc-hi"},
667 {MO_LE_HI_R,
"loongarch-le-hi-r"},
668 {MO_LE_ADD_R,
"loongarch-le-add-r"},
669 {MO_LE_LO_R,
"loongarch-le-lo-r"}};
675 return MI.getOpcode() == LoongArch::ADDI_W &&
MI.getOperand(1).isReg() &&
676 MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0;
unsigned const MachineRegisterInfo * MRI
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static unsigned getOppositeBranchOpc(unsigned Opcode)
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
const LoongArchSubtarget & STI
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
LoongArchInstrInfo(LoongArchSubtarget &STI)
MCInst getNop() const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...
int getBranchRelaxationSpillFrameIndex()
This class is intended to be used as a base class for asm properties and features specific to the tar...
MCInstBuilder & addReg(MCRegister Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Wrapper class representing physical registers. Should be passed by value.
unsigned pred_size() const
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineBasicBlock * getMBB() const
void setMBB(MachineBasicBlock *MBB)
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
MI-level Statepoint operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given statepoint should emit.
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Target - Wrapper for Target specific information.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstSeq generateInstSeq(int64_t Val)
bool isSEXT_W(const MachineInstr &MI)
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned getKillRegState(bool B)
Description of the encoding of one expression Op.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.