LLVM 20.0.0git
LoongArchInstrInfo.cpp
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1//=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchInstrInfo.h"
14#include "LoongArch.h"
22
23using namespace llvm;
24
25#define GET_INSTRINFO_CTOR_DTOR
26#include "LoongArchGenInstrInfo.inc"
27
29 : LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN,
30 LoongArch::ADJCALLSTACKUP),
31 STI(STI) {}
32
34 return MCInstBuilder(LoongArch::ANDI)
35 .addReg(LoongArch::R0)
36 .addReg(LoongArch::R0)
37 .addImm(0);
38}
39
42 const DebugLoc &DL, MCRegister DstReg,
43 MCRegister SrcReg, bool KillSrc,
44 bool RenamableDest,
45 bool RenamableSrc) const {
46 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
47 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
48 .addReg(SrcReg, getKillRegState(KillSrc))
49 .addReg(LoongArch::R0);
50 return;
51 }
52
53 // VR->VR copies.
54 if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) {
55 BuildMI(MBB, MBBI, DL, get(LoongArch::VORI_B), DstReg)
56 .addReg(SrcReg, getKillRegState(KillSrc))
57 .addImm(0);
58 return;
59 }
60
61 // XR->XR copies.
62 if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) {
63 BuildMI(MBB, MBBI, DL, get(LoongArch::XVORI_B), DstReg)
64 .addReg(SrcReg, getKillRegState(KillSrc))
65 .addImm(0);
66 return;
67 }
68
69 // GPR->CFR copy.
70 if (LoongArch::CFRRegClass.contains(DstReg) &&
71 LoongArch::GPRRegClass.contains(SrcReg)) {
72 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVGR2CF), DstReg)
73 .addReg(SrcReg, getKillRegState(KillSrc));
74 return;
75 }
76 // CFR->GPR copy.
77 if (LoongArch::GPRRegClass.contains(DstReg) &&
78 LoongArch::CFRRegClass.contains(SrcReg)) {
79 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVCF2GR), DstReg)
80 .addReg(SrcReg, getKillRegState(KillSrc));
81 return;
82 }
83 // CFR->CFR copy.
84 if (LoongArch::CFRRegClass.contains(DstReg, SrcReg)) {
85 BuildMI(MBB, MBBI, DL, get(LoongArch::PseudoCopyCFR), DstReg)
86 .addReg(SrcReg, getKillRegState(KillSrc));
87 return;
88 }
89
90 // FPR->FPR copies.
91 unsigned Opc;
92 if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) {
93 Opc = LoongArch::FMOV_S;
94 } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) {
95 Opc = LoongArch::FMOV_D;
96 } else if (LoongArch::GPRRegClass.contains(DstReg) &&
97 LoongArch::FPR32RegClass.contains(SrcReg)) {
98 // FPR32 -> GPR copies
99 Opc = LoongArch::MOVFR2GR_S;
100 } else if (LoongArch::GPRRegClass.contains(DstReg) &&
101 LoongArch::FPR64RegClass.contains(SrcReg)) {
102 // FPR64 -> GPR copies
103 Opc = LoongArch::MOVFR2GR_D;
104 } else {
105 // TODO: support other copies.
106 llvm_unreachable("Impossible reg-to-reg copy");
107 }
108
109 BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
110 .addReg(SrcReg, getKillRegState(KillSrc));
111}
112
115 bool IsKill, int FI, const TargetRegisterClass *RC,
116 const TargetRegisterInfo *TRI, Register VReg) const {
118 MachineFrameInfo &MFI = MF->getFrameInfo();
119
120 unsigned Opcode;
121 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
122 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
123 ? LoongArch::ST_W
124 : LoongArch::ST_D;
125 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
126 Opcode = LoongArch::FST_S;
127 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
128 Opcode = LoongArch::FST_D;
129 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
130 Opcode = LoongArch::VST;
131 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
132 Opcode = LoongArch::XVST;
133 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
134 Opcode = LoongArch::PseudoST_CFR;
135 else
136 llvm_unreachable("Can't store this register to stack slot");
137
140 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
141
142 BuildMI(MBB, I, DebugLoc(), get(Opcode))
143 .addReg(SrcReg, getKillRegState(IsKill))
144 .addFrameIndex(FI)
145 .addImm(0)
146 .addMemOperand(MMO);
147}
148
151 Register DstReg, int FI,
152 const TargetRegisterClass *RC,
153 const TargetRegisterInfo *TRI,
154 Register VReg) const {
156 MachineFrameInfo &MFI = MF->getFrameInfo();
157 DebugLoc DL;
158 if (I != MBB.end())
159 DL = I->getDebugLoc();
160
161 unsigned Opcode;
162 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
163 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
164 ? LoongArch::LD_W
165 : LoongArch::LD_D;
166 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
167 Opcode = LoongArch::FLD_S;
168 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
169 Opcode = LoongArch::FLD_D;
170 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
171 Opcode = LoongArch::VLD;
172 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
173 Opcode = LoongArch::XVLD;
174 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
175 Opcode = LoongArch::PseudoLD_CFR;
176 else
177 llvm_unreachable("Can't load this register from stack slot");
178
181 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
182
183 BuildMI(MBB, I, DL, get(Opcode), DstReg)
184 .addFrameIndex(FI)
185 .addImm(0)
186 .addMemOperand(MMO);
187}
188
191 const DebugLoc &DL, Register DstReg,
192 uint64_t Val, MachineInstr::MIFlag Flag) const {
193 Register SrcReg = LoongArch::R0;
194
195 if (!STI.is64Bit() && !isInt<32>(Val))
196 report_fatal_error("Should only materialize 32-bit constants for LA32");
197
198 auto Seq = LoongArchMatInt::generateInstSeq(Val);
199 assert(!Seq.empty());
200
201 for (auto &Inst : Seq) {
202 switch (Inst.Opc) {
203 case LoongArch::LU12I_W:
204 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
205 .addImm(Inst.Imm)
206 .setMIFlag(Flag);
207 break;
208 case LoongArch::ADDI_W:
209 case LoongArch::ORI:
210 case LoongArch::LU32I_D: // "rj" is needed due to InstrInfo pattern
211 case LoongArch::LU52I_D:
212 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
213 .addReg(SrcReg, RegState::Kill)
214 .addImm(Inst.Imm)
215 .setMIFlag(Flag);
216 break;
217 case LoongArch::BSTRINS_D:
218 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
219 .addReg(SrcReg, RegState::Kill)
220 .addReg(SrcReg, RegState::Kill)
221 .addImm(Inst.Imm >> 32)
222 .addImm(Inst.Imm & 0xFF)
223 .setMIFlag(Flag);
224 break;
225 default:
226 assert(false && "Unknown insn emitted by LoongArchMatInt");
227 }
228
229 // Only the first instruction has $zero as its source.
230 SrcReg = DstReg;
231 }
232}
233
235 unsigned Opcode = MI.getOpcode();
236
237 if (Opcode == TargetOpcode::INLINEASM ||
238 Opcode == TargetOpcode::INLINEASM_BR) {
239 const MachineFunction *MF = MI.getParent()->getParent();
240 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
241 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
242 }
243
244 unsigned NumBytes = 0;
245 const MCInstrDesc &Desc = MI.getDesc();
246
247 // Size should be preferably set in
248 // llvm/lib/Target/LoongArch/LoongArch*InstrInfo.td (default case).
249 // Specific cases handle instructions of variable sizes.
250 switch (Desc.getOpcode()) {
251 default:
252 return Desc.getSize();
253 case TargetOpcode::STATEPOINT:
254 NumBytes = StatepointOpers(&MI).getNumPatchBytes();
255 assert(NumBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
256 // No patch bytes means a normal call inst (i.e. `bl`) is emitted.
257 if (NumBytes == 0)
258 NumBytes = 4;
259 break;
260 }
261 return NumBytes;
262}
263
265 const unsigned Opcode = MI.getOpcode();
266 switch (Opcode) {
267 default:
268 break;
269 case LoongArch::ADDI_D:
270 case LoongArch::ORI:
271 case LoongArch::XORI:
272 return (MI.getOperand(1).isReg() &&
273 MI.getOperand(1).getReg() == LoongArch::R0) ||
274 (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
275 }
276 return MI.isAsCheapAsAMove();
277}
278
281 assert(MI.getDesc().isBranch() && "Unexpected opcode!");
282 // The branch target is always the last operand.
283 return MI.getOperand(MI.getNumExplicitOperands() - 1).getMBB();
284}
285
288 // Block ends with fall-through condbranch.
289 assert(LastInst.getDesc().isConditionalBranch() &&
290 "Unknown conditional branch");
291 int NumOp = LastInst.getNumExplicitOperands();
292 Target = LastInst.getOperand(NumOp - 1).getMBB();
293
294 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
295 for (int i = 0; i < NumOp - 1; i++)
296 Cond.push_back(LastInst.getOperand(i));
297}
298
301 MachineBasicBlock *&FBB,
303 bool AllowModify) const {
304 TBB = FBB = nullptr;
305 Cond.clear();
306
307 // If the block has no terminators, it just falls into the block after it.
309 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
310 return false;
311
312 // Count the number of terminators and find the first unconditional or
313 // indirect branch.
314 MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
315 int NumTerminators = 0;
316 for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
317 J++) {
318 NumTerminators++;
319 if (J->getDesc().isUnconditionalBranch() ||
320 J->getDesc().isIndirectBranch()) {
321 FirstUncondOrIndirectBr = J.getReverse();
322 }
323 }
324
325 // If AllowModify is true, we can erase any terminators after
326 // FirstUncondOrIndirectBR.
327 if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
328 while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
329 std::next(FirstUncondOrIndirectBr)->eraseFromParent();
330 NumTerminators--;
331 }
332 I = FirstUncondOrIndirectBr;
333 }
334
335 // Handle a single unconditional branch.
336 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
338 return false;
339 }
340
341 // Handle a single conditional branch.
342 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
344 return false;
345 }
346
347 // Handle a conditional branch followed by an unconditional branch.
348 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
349 I->getDesc().isUnconditionalBranch()) {
350 parseCondBranch(*std::prev(I), TBB, Cond);
351 FBB = getBranchDestBlock(*I);
352 return false;
353 }
354
355 // Otherwise, we can't handle this.
356 return true;
357}
358
360 int64_t BrOffset) const {
361 switch (BranchOp) {
362 default:
363 llvm_unreachable("Unknown branch instruction!");
364 case LoongArch::BEQ:
365 case LoongArch::BNE:
366 case LoongArch::BLT:
367 case LoongArch::BGE:
368 case LoongArch::BLTU:
369 case LoongArch::BGEU:
370 return isInt<18>(BrOffset);
371 case LoongArch::BEQZ:
372 case LoongArch::BNEZ:
373 case LoongArch::BCEQZ:
374 case LoongArch::BCNEZ:
375 return isInt<23>(BrOffset);
376 case LoongArch::B:
377 case LoongArch::PseudoBR:
378 return isInt<28>(BrOffset);
379 }
380}
381
383 const MachineBasicBlock *MBB,
384 const MachineFunction &MF) const {
386 return true;
387
388 auto MII = MI.getIterator();
389 auto MIE = MBB->end();
390
391 // According to psABI v2.30:
392 //
393 // https://github.com/loongson/la-abi-specs/releases/tag/v2.30
394 //
395 // The following instruction patterns are prohibited from being reordered:
396 //
397 // * pcalau12i $a0, %pc_hi20(s)
398 // addi.d $a1, $zero, %pc_lo12(s)
399 // lu32i.d $a1, %pc64_lo20(s)
400 // lu52i.d $a1, $a1, %pc64_hi12(s)
401 //
402 // * pcalau12i $a0, %got_pc_hi20(s) | %ld_pc_hi20(s) | %gd_pc_hi20(s)
403 // addi.d $a1, $zero, %got_pc_lo12(s)
404 // lu32i.d $a1, %got64_pc_lo20(s)
405 // lu52i.d $a1, $a1, %got64_pc_hi12(s)
406 //
407 // * pcalau12i $a0, %ie_pc_hi20(s)
408 // addi.d $a1, $zero, %ie_pc_lo12(s)
409 // lu32i.d $a1, %ie64_pc_lo20(s)
410 // lu52i.d $a1, $a1, %ie64_pc_hi12(s)
411 //
412 // * pcalau12i $a0, %desc_pc_hi20(s)
413 // addi.d $a1, $zero, %desc_pc_lo12(s)
414 // lu32i.d $a1, %desc64_pc_lo20(s)
415 // lu52i.d $a1, $a1, %desc64_pc_hi12(s)
416 //
417 // For simplicity, only pcalau12i and lu52i.d are marked as scheduling
418 // boundaries, and the instructions between them are guaranteed to be
419 // ordered according to data dependencies.
420 switch (MI.getOpcode()) {
421 case LoongArch::PCALAU12I: {
422 auto AddI = std::next(MII);
423 if (AddI == MIE || AddI->getOpcode() != LoongArch::ADDI_D)
424 break;
425 auto Lu32I = std::next(AddI);
426 if (Lu32I == MIE || Lu32I->getOpcode() != LoongArch::LU32I_D)
427 break;
428 auto MO0 = MI.getOperand(1).getTargetFlags();
429 auto MO1 = AddI->getOperand(2).getTargetFlags();
430 auto MO2 = Lu32I->getOperand(2).getTargetFlags();
433 return true;
435 MO0 == LoongArchII::MO_GD_PC_HI) &&
437 return true;
440 return true;
441 if (MO0 == LoongArchII::MO_DESC_PC_HI &&
444 return true;
445 break;
446 }
447 case LoongArch::LU52I_D: {
448 auto MO = MI.getOperand(2).getTargetFlags();
451 return true;
452 break;
453 }
454 default:
455 break;
456 }
457
458 return false;
459}
460
462 int *BytesRemoved) const {
463 if (BytesRemoved)
464 *BytesRemoved = 0;
466 if (I == MBB.end())
467 return 0;
468
469 if (!I->getDesc().isBranch())
470 return 0;
471
472 // Remove the branch.
473 if (BytesRemoved)
474 *BytesRemoved += getInstSizeInBytes(*I);
475 I->eraseFromParent();
476
477 I = MBB.end();
478
479 if (I == MBB.begin())
480 return 1;
481 --I;
482 if (!I->getDesc().isConditionalBranch())
483 return 1;
484
485 // Remove the branch.
486 if (BytesRemoved)
487 *BytesRemoved += getInstSizeInBytes(*I);
488 I->eraseFromParent();
489 return 2;
490}
491
492// Inserts a branch into the end of the specific MachineBasicBlock, returning
493// the number of instructions inserted.
496 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
497 if (BytesAdded)
498 *BytesAdded = 0;
499
500 // Shouldn't be a fall through.
501 assert(TBB && "insertBranch must not be told to insert a fallthrough");
502 assert(Cond.size() <= 3 && Cond.size() != 1 &&
503 "LoongArch branch conditions have at most two components!");
504
505 // Unconditional branch.
506 if (Cond.empty()) {
507 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(TBB);
508 if (BytesAdded)
509 *BytesAdded += getInstSizeInBytes(MI);
510 return 1;
511 }
512
513 // Either a one or two-way conditional branch.
514 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
515 for (unsigned i = 1; i < Cond.size(); ++i)
516 MIB.add(Cond[i]);
517 MIB.addMBB(TBB);
518 if (BytesAdded)
519 *BytesAdded += getInstSizeInBytes(*MIB);
520
521 // One-way conditional branch.
522 if (!FBB)
523 return 1;
524
525 // Two-way conditional branch.
526 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(FBB);
527 if (BytesAdded)
528 *BytesAdded += getInstSizeInBytes(MI);
529 return 2;
530}
531
533 MachineBasicBlock &DestBB,
534 MachineBasicBlock &RestoreBB,
535 const DebugLoc &DL,
536 int64_t BrOffset,
537 RegScavenger *RS) const {
538 assert(RS && "RegScavenger required for long branching");
539 assert(MBB.empty() &&
540 "new block should be inserted for expanding unconditional branch");
541 assert(MBB.pred_size() == 1);
542
548
549 if (!isInt<32>(BrOffset))
551 "Branch offsets outside of the signed 32-bit range not supported");
552
553 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
554 auto II = MBB.end();
555
556 MachineInstr &PCALAU12I =
557 *BuildMI(MBB, II, DL, get(LoongArch::PCALAU12I), ScratchReg)
559 MachineInstr &ADDI =
560 *BuildMI(MBB, II, DL,
561 get(STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W),
562 ScratchReg)
563 .addReg(ScratchReg)
565 BuildMI(MBB, II, DL, get(LoongArch::PseudoBRIND))
566 .addReg(ScratchReg, RegState::Kill)
567 .addImm(0);
568
571 LoongArch::GPRRegClass, PCALAU12I.getIterator(), /*RestoreAfter=*/false,
572 /*SPAdj=*/0, /*AllowSpill=*/false);
573 if (Scav != LoongArch::NoRegister)
574 RS->setRegUsed(Scav);
575 else {
576 // When there is no scavenged register, it needs to specify a register.
577 // Specify t8 register because it won't be used too often.
578 Scav = LoongArch::R20;
579 int FrameIndex = LAFI->getBranchRelaxationSpillFrameIndex();
580 if (FrameIndex == -1)
581 report_fatal_error("The function size is incorrectly estimated.");
582 storeRegToStackSlot(MBB, PCALAU12I, Scav, /*IsKill=*/true, FrameIndex,
583 &LoongArch::GPRRegClass, TRI, Register());
584 TRI->eliminateFrameIndex(std::prev(PCALAU12I.getIterator()),
585 /*SpAdj=*/0, /*FIOperandNum=*/1);
586 PCALAU12I.getOperand(1).setMBB(&RestoreBB);
587 ADDI.getOperand(2).setMBB(&RestoreBB);
588 loadRegFromStackSlot(RestoreBB, RestoreBB.end(), Scav, FrameIndex,
589 &LoongArch::GPRRegClass, TRI, Register());
590 TRI->eliminateFrameIndex(RestoreBB.back(),
591 /*SpAdj=*/0, /*FIOperandNum=*/1);
592 }
593 MRI.replaceRegWith(ScratchReg, Scav);
594 MRI.clearVirtRegs();
595}
596
597static unsigned getOppositeBranchOpc(unsigned Opc) {
598 switch (Opc) {
599 default:
600 llvm_unreachable("Unrecognized conditional branch");
601 case LoongArch::BEQ:
602 return LoongArch::BNE;
603 case LoongArch::BNE:
604 return LoongArch::BEQ;
605 case LoongArch::BEQZ:
606 return LoongArch::BNEZ;
607 case LoongArch::BNEZ:
608 return LoongArch::BEQZ;
609 case LoongArch::BCEQZ:
610 return LoongArch::BCNEZ;
611 case LoongArch::BCNEZ:
612 return LoongArch::BCEQZ;
613 case LoongArch::BLT:
614 return LoongArch::BGE;
615 case LoongArch::BGE:
616 return LoongArch::BLT;
617 case LoongArch::BLTU:
618 return LoongArch::BGEU;
619 case LoongArch::BGEU:
620 return LoongArch::BLTU;
621 }
622}
623
626 assert((Cond.size() && Cond.size() <= 3) && "Invalid branch condition!");
627 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
628 return false;
629}
630
631std::pair<unsigned, unsigned>
633 return std::make_pair(TF, 0u);
634}
635
638 using namespace LoongArchII;
639 // TODO: Add more target flags.
640 static const std::pair<unsigned, const char *> TargetFlags[] = {
641 {MO_CALL, "loongarch-call"},
642 {MO_CALL_PLT, "loongarch-call-plt"},
643 {MO_PCREL_HI, "loongarch-pcrel-hi"},
644 {MO_PCREL_LO, "loongarch-pcrel-lo"},
645 {MO_PCREL64_LO, "loongarch-pcrel64-lo"},
646 {MO_PCREL64_HI, "loongarch-pcrel64-hi"},
647 {MO_GOT_PC_HI, "loongarch-got-pc-hi"},
648 {MO_GOT_PC_LO, "loongarch-got-pc-lo"},
649 {MO_GOT_PC64_LO, "loongarch-got-pc64-lo"},
650 {MO_GOT_PC64_HI, "loongarch-got-pc64-hi"},
651 {MO_LE_HI, "loongarch-le-hi"},
652 {MO_LE_LO, "loongarch-le-lo"},
653 {MO_LE64_LO, "loongarch-le64-lo"},
654 {MO_LE64_HI, "loongarch-le64-hi"},
655 {MO_IE_PC_HI, "loongarch-ie-pc-hi"},
656 {MO_IE_PC_LO, "loongarch-ie-pc-lo"},
657 {MO_IE_PC64_LO, "loongarch-ie-pc64-lo"},
658 {MO_IE_PC64_HI, "loongarch-ie-pc64-hi"},
659 {MO_DESC_PC_HI, "loongarch-desc-pc-hi"},
660 {MO_DESC_PC_LO, "loongarch-desc-pc-lo"},
661 {MO_DESC64_PC_LO, "loongarch-desc64-pc-lo"},
662 {MO_DESC64_PC_HI, "loongarch-desc64-pc-hi"},
663 {MO_DESC_LD, "loongarch-desc-ld"},
664 {MO_DESC_CALL, "loongarch-desc-call"},
665 {MO_LD_PC_HI, "loongarch-ld-pc-hi"},
666 {MO_GD_PC_HI, "loongarch-gd-pc-hi"},
667 {MO_LE_HI_R, "loongarch-le-hi-r"},
668 {MO_LE_ADD_R, "loongarch-le-add-r"},
669 {MO_LE_LO_R, "loongarch-le-lo-r"}};
670 return ArrayRef(TargetFlags);
671}
672
673// Returns true if this is the sext.w pattern, addi.w rd, rs, 0.
675 return MI.getOpcode() == LoongArch::ADDI_W && MI.getOperand(1).isReg() &&
676 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0;
677}
unsigned const MachineRegisterInfo * MRI
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static unsigned getOppositeBranchOpc(unsigned Opcode)
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
const LoongArchSubtarget & STI
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
LoongArchInstrInfo(LoongArchSubtarget &STI)
MCInst getNop() const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
MCInstBuilder & addReg(MCRegister Reg)
Add a new register operand.
Definition: MCInstBuilder.h:37
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:43
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:317
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
unsigned pred_size() const
reverse_iterator rend()
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:575
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:572
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:585
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineBasicBlock * getMBB() const
void setMBB(MachineBasicBlock *MBB)
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
MI-level Statepoint operands.
Definition: StackMaps.h:158
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given statepoint should emit.
Definition: StackMaps.h:207
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Target - Wrapper for Target specific information.
self_iterator getIterator()
Definition: ilist_node.h:132
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstSeq generateInstSeq(int64_t Val)
bool isSEXT_W(const MachineInstr &MI)
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
unsigned getKillRegState(bool B)
Description of the encoding of one expression Op.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.