SPIRVUtils.h File Reference

#include "MCTargetDesc/SPIRVBaseInfo.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/TypedPointerType.h"
#include <queue>
#include <string>
#include <unordered_map>
#include <unordered_set>

Go to the source code of this file.

Classes
class	llvm::PartialOrderingVisitor

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	TYPED_PTR_TARGET_EXT_NAME   "spirv.$TypedPointerType"
#define	SPIRV_BACKEND_SERVICE_FUN_NAME   "__spirv_backend_service_fun"

Enumerations
enum	llvm::FPDecorationId {   llvm::NONE = 0 , llvm::RTE , llvm::RTZ , llvm::RTP ,   llvm::RTN , llvm::SAT }

Functions
void	llvm::addStringImm (const StringRef &Str, MCInst &Inst)
void	llvm::addStringImm (const StringRef &Str, MachineInstrBuilder &MIB)
void	llvm::addStringImm (const StringRef &Str, IRBuilder<> &B, std::vector< Value * > &Args)
std::string	llvm::getStringImm (const MachineInstr &MI, unsigned StartIndex)
std::string	llvm::getStringValueFromReg (Register Reg, MachineRegisterInfo &MRI)
void	llvm::addNumImm (const APInt &Imm, MachineInstrBuilder &MIB)
void	llvm::buildOpName (Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
void	llvm::buildOpName (Register Target, const StringRef &Name, MachineInstr &I, const SPIRVInstrInfo &TII)
void	llvm::buildOpDecorate (Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
void	llvm::buildOpDecorate (Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
void	llvm::buildOpMemberDecorate (Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, uint32_t Member, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
void	llvm::buildOpMemberDecorate (Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII, SPIRV::Decoration::Decoration Dec, uint32_t Member, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
void	llvm::buildOpSpirvDecorations (Register Reg, MachineIRBuilder &MIRBuilder, const MDNode *GVarMD)
MachineBasicBlock::iterator	llvm::getOpVariableMBBIt (MachineInstr &I)
MachineBasicBlock::iterator	llvm::getInsertPtValidEnd (MachineBasicBlock *MBB)
constexpr bool	llvm::isGenericCastablePtr (SPIRV::StorageClass::StorageClass SC)
constexpr unsigned	llvm::storageClassToAddressSpace (SPIRV::StorageClass::StorageClass SC)
SPIRV::StorageClass::StorageClass	llvm::addressSpaceToStorageClass (unsigned AddrSpace, const SPIRVSubtarget &STI)
SPIRV::MemorySemantics::MemorySemantics	llvm::getMemSemanticsForStorageClass (SPIRV::StorageClass::StorageClass SC)
SPIRV::MemorySemantics::MemorySemantics	llvm::getMemSemantics (AtomicOrdering Ord)
SPIRV::Scope::Scope	llvm::getMemScope (LLVMContext &Ctx, SyncScope::ID Id)
MachineInstr *	llvm::getDefInstrMaybeConstant (Register &ConstReg, const MachineRegisterInfo *MRI)
uint64_t	llvm::getIConstVal (Register ConstReg, const MachineRegisterInfo *MRI)
bool	llvm::isSpvIntrinsic (const MachineInstr &MI, Intrinsic::ID IntrinsicID)
bool	llvm::isSpvIntrinsic (const Value *Arg)
Type *	llvm::getMDOperandAsType (const MDNode *N, unsigned I)
std::string	llvm::getOclOrSpirvBuiltinDemangledName (StringRef Name)
bool	llvm::hasBuiltinTypePrefix (StringRef Name)
bool	llvm::isSpecialOpaqueType (const Type *Ty)
bool	llvm::isEntryPoint (const Function &F)
Type *	llvm::parseBasicTypeName (StringRef &TypeName, LLVMContext &Ctx)
bool	llvm::sortBlocks (Function &F)
bool	llvm::hasInitializer (const GlobalVariable *GV)
bool	llvm::isTypedPointerTy (const Type *T)
bool	llvm::isUntypedPointerTy (const Type *T)
bool	llvm::isPointerTy (const Type *T)
unsigned	llvm::getPointerAddressSpace (const Type *T)
bool	llvm::hasPointeeTypeAttr (Argument *Arg)
Type *	llvm::getPointeeTypeByAttr (Argument *Arg)
Type *	llvm::reconstructFunctionType (Function *F)
Type *	llvm::getTypedPointerWrapper (Type *ElemTy, unsigned AS)
bool	llvm::isTypedPointerWrapper (const TargetExtType *ExtTy)
bool	llvm::isPointerTyOrWrapper (const Type *Ty)
Type *	llvm::applyWrappers (Type *Ty)
Type *	llvm::getPointeeType (const Type *Ty)
bool	llvm::isUntypedEquivalentToTyExt (Type *Ty1, Type *Ty2)
bool	llvm::isEquivalentTypes (Type *Ty1, Type *Ty2)
Type *	llvm::toTypedPointer (Type *Ty)
Type *	llvm::toTypedFunPointer (FunctionType *FTy)
const Type *	llvm::unifyPtrType (const Type *Ty)
bool	llvm::isVector1 (Type *Ty)
Type *	llvm::normalizeType (Type *Ty)
PoisonValue *	llvm::getNormalizedPoisonValue (Type *Ty)
MetadataAsValue *	llvm::buildMD (Value *Arg)
CallInst *	llvm::buildIntrWithMD (Intrinsic::ID IntrID, ArrayRef< Type * > Types, Value *Arg, Value *Arg2, ArrayRef< Constant * > Imms, IRBuilder<> &B)
MachineInstr *	llvm::getVRegDef (MachineRegisterInfo &MRI, Register Reg)
bool	llvm::getVacantFunctionName (Module &M, std::string &Name)
void	llvm::setRegClassType (Register Reg, const Type *Ty, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR, bool Force)
void	llvm::setRegClassType (Register Reg, const MachineInstr *SpvType, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI, const MachineFunction &MF, bool Force=false)
Register	llvm::createVirtualRegister (const MachineInstr *SpvType, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI, const MachineFunction &MF)
Register	llvm::createVirtualRegister (const MachineInstr *SpvType, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIRBuilder)
Register	llvm::createVirtualRegister (const Type *Ty, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR)
bool	llvm::isNestedPointer (const Type *Ty)
FPDecorationId	llvm::demangledPostfixToDecorationId (const std::string &S)
SmallVector< MachineInstr *, 4 >	llvm::createContinuedInstructions (MachineIRBuilder &MIRBuilder, unsigned Opcode, unsigned MinWC, unsigned ContinuedOpcode, ArrayRef< Register > Args, Register ReturnRegister, Register TypeID)
const std::set< unsigned > &	llvm::getTypeFoldingSupportedOpcodes ()
bool	llvm::isTypeFoldingSupported (unsigned Opcode)
SmallVector< unsigned, 1 >	llvm::getSpirvLoopControlOperandsFromLoopMetadata (Loop *L)
MachineInstr *	llvm::passCopy (MachineInstr *Def, const MachineRegisterInfo *MRI)
MachineInstr *	llvm::getDef (const MachineOperand &MO, const MachineRegisterInfo *MRI)
MachineInstr *	llvm::getImm (const MachineOperand &MO, const MachineRegisterInfo *MRI)
int64_t	llvm::foldImm (const MachineOperand &MO, const MachineRegisterInfo *MRI)
unsigned	llvm::getArrayComponentCount (const MachineRegisterInfo *MRI, const MachineInstr *ResType)
MachineBasicBlock::iterator	llvm::getFirstValidInstructionInsertPoint (MachineBasicBlock &BB)

Macro Definition Documentation

SPIRV_BACKEND_SERVICE_FUN_NAME

#define SPIRV_BACKEND_SERVICE_FUN_NAME   "__spirv_backend_service_fun"

Definition at line 452 of file SPIRVUtils.h.

Referenced by llvm::SPIRVCallLowering::lowerCall(), llvm::SPIRVCallLowering::lowerFormalArguments(), and llvm::SPIRVCallLowering::lowerReturn().

TYPED_PTR_TARGET_EXT_NAME

#define TYPED_PTR_TARGET_EXT_NAME   "spirv.$TypedPointerType"

Definition at line 324 of file SPIRVUtils.h.

Referenced by llvm::getTypedPointerWrapper(), and llvm::isTypedPointerWrapper().