23#define GET_INSTRINFO_CTOR_DTOR
24#include "BPFGenInstrInfo.inc"
35 bool RenamableDest,
bool RenamableSrc)
const {
36 if (BPF::GPRRegClass.
contains(DestReg, SrcReg))
39 else if (BPF::GPR32RegClass.
contains(DestReg, SrcReg))
50 uint64_t Alignment =
MI->getOperand(3).getImm();
51 Register ScratchReg =
MI->getOperand(4).getReg();
54 unsigned LdOpc, StOpc;
77 unsigned IterationNum = CopyLen >>
Log2_64(Alignment);
78 for(
unsigned I = 0;
I < IterationNum; ++
I) {
87 unsigned BytesLeft = CopyLen & (Alignment - 1);
88 unsigned Offset = IterationNum * Alignment;
89 bool Hanging4Byte = BytesLeft & 0x4;
90 bool Hanging2Byte = BytesLeft & 0x2;
91 bool Hanging1Byte = BytesLeft & 0x1;
117 if (
MI.getOpcode() == BPF::MEMCPY) {
127 Register SrcReg,
bool IsKill,
int FI,
133 DL =
I->getDebugLoc();
135 if (RC == &BPF::GPRRegClass)
140 else if (RC == &BPF::GPR32RegClass)
157 DL =
I->getDebugLoc();
159 if (RC == &BPF::GPRRegClass)
161 else if (RC == &BPF::GPR32RegClass)
171 bool AllowModify)
const {
177 if (
I->isDebugInstr())
182 if (!isUnpredicatedTerminator(*
I))
191 if (
I->getOpcode() == BPF::JMP) {
193 TBB =
I->getOperand(0).getMBB();
205 I->eraseFromParent();
211 TBB =
I->getOperand(0).getMBB();
226 int *BytesAdded)
const {
227 assert(!BytesAdded &&
"code size not handled");
230 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
234 assert(!FBB &&
"Unconditional branch with multiple successors!");
243 int *BytesRemoved)
const {
244 assert(!BytesRemoved &&
"code size not handled");
251 if (
I->isDebugInstr())
253 if (
I->getOpcode() != BPF::JMP)
256 I->eraseFromParent();
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Wrapper class representing physical registers. Should be passed by value.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Define
Register definition.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getKillRegState(bool B)