24#define DEBUG_TYPE "riscv-merge-base-offset"
25#define RISCV_MERGE_BASE_OFFSET_NAME "RISC-V Merge Base Offset"
51 MachineFunctionProperties::Property::IsSSA);
65char RISCVMergeBaseOffsetOpt::ID = 0;
87 if (
Hi.getOpcode() != RISCV::LUI &&
Hi.getOpcode() != RISCV::AUIPC &&
88 Hi.getOpcode() != RISCV::PseudoMovAddr)
92 unsigned ExpectedFlags =
101 if (
Hi.getOpcode() == RISCV::PseudoMovAddr) {
106 Register HiDestReg =
Hi.getOperand(0).getReg();
107 if (!
MRI->hasOneUse(HiDestReg))
110 Lo = &*
MRI->use_instr_begin(HiDestReg);
111 if (
Lo->getOpcode() != RISCV::ADDI)
116 if (
Hi.getOpcode() == RISCV::LUI ||
Hi.getOpcode() == RISCV::PseudoMovAddr) {
122 assert(
Hi.getOpcode() == RISCV::AUIPC);
134 }
else if (HiOp1.
isCPI()) {
150 if (
Hi.getOpcode() != RISCV::AUIPC)
153 MRI->constrainRegClass(
Lo.getOperand(0).getReg(),
154 MRI->getRegClass(
Tail.getOperand(0).getReg()));
155 MRI->replaceRegWith(
Tail.getOperand(0).getReg(),
Lo.getOperand(0).getReg());
156 Tail.eraseFromParent();
158 <<
" " <<
Hi <<
" " <<
Lo;);
185 assert((TailAdd.
getOpcode() == RISCV::ADD) &&
"Expected ADD instruction!");
191 if (!
Reg.isVirtual() || !
MRI->hasOneUse(Reg))
195 if (OffsetTail.
getOpcode() == RISCV::ADDI ||
196 OffsetTail.
getOpcode() == RISCV::ADDIW) {
203 int64_t OffLo = AddiImmOp.
getImm();
206 if (AddiReg == RISCV::X0) {
208 foldOffset(
Hi,
Lo, TailAdd, OffLo);
215 if (OffsetLui.
getOpcode() != RISCV::LUI ||
219 int64_t
Offset = SignExtend64<32>(LuiImmOp.
getImm() << 12);
222 if (!
ST->is64Bit() || OffsetTail.
getOpcode() == RISCV::ADDIW)
228 <<
" " << OffsetLui);
233 }
else if (OffsetTail.
getOpcode() == RISCV::LUI) {
261 TailShXAdd.
getOpcode() == RISCV::SH2ADD ||
262 TailShXAdd.
getOpcode() == RISCV::SH3ADD) &&
263 "Expected SHXADD instruction!");
276 if (OffsetTail.
getOpcode() != RISCV::ADDI)
289 case RISCV::SH1ADD: ShAmt = 1;
break;
290 case RISCV::SH2ADD: ShAmt = 2;
break;
291 case RISCV::SH3ADD: ShAmt = 3;
break;
302bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(
MachineInstr &
Hi,
309 if (!
MRI->hasOneUse(DestReg))
314 switch (
Tail.getOpcode()) {
316 LLVM_DEBUG(
dbgs() <<
"Don't know how to get offset from this instr:"
325 if (
MRI->hasOneUse(TailDestReg)) {
327 if (TailTail.
getOpcode() == RISCV::ADDI) {
331 Tail.eraseFromParent();
349 return foldLargeOffset(
Hi,
Lo,
Tail, DestReg);
356 return foldShiftedOffset(
Hi,
Lo,
Tail, DestReg);
378 std::optional<int64_t> CommonOffset;
380 InlineAsmMemoryOpIndexesMap;
382 switch (
UseMI.getOpcode()) {
403 if (
UseMI.getOperand(1).isFI())
409 "Expected base address use");
412 if (CommonOffset &&
Offset != CommonOffset)
417 case RISCV::INLINEASM:
418 case RISCV::INLINEASM_BR: {
422 I <
UseMI.getNumOperands();
I += 1 + NumOps) {
425 if (!FlagsMO.
isImm())
429 NumOps =
Flags.getNumOperandRegisters();
432 if (NumOps != 2 || !
Flags.isMemKind()) {
435 for (
unsigned J = 0; J < NumOps; ++J) {
445 if (
Flags.getMemoryConstraintID() == InlineAsm::ConstraintCode::A)
453 if (!OffsetMO.
isImm())
458 if (CommonOffset &&
Offset != CommonOffset)
463 InlineAsmMemoryOpIndexesMap.
insert(
464 std::make_pair(&
UseMI, InlineAsmMemoryOpIndexes));
474 int64_t NewOffset =
Hi.getOperand(1).getOffset() + *CommonOffset;
477 NewOffset = SignExtend64<32>(NewOffset);
479 if (!isInt<32>(NewOffset))
482 Hi.getOperand(1).setOffset(NewOffset);
485 if (
Hi.getOpcode() == RISCV::PseudoMovAddr) {
486 auto *
TII =
ST->getInstrInfo();
487 Hi.setDesc(
TII->get(RISCV::LUI));
491 if (
Hi.getOpcode() != RISCV::AUIPC)
497 if (
UseMI.getOpcode() == RISCV::INLINEASM ||
498 UseMI.getOpcode() == RISCV::INLINEASM_BR) {
499 auto &InlineAsmMemoryOpIndexes = InlineAsmMemoryOpIndexesMap[&
UseMI];
500 for (
unsigned I : InlineAsmMemoryOpIndexes) {
521 UseMI.removeOperand(2);
522 UseMI.addOperand(ImmOp);
531 MRI->replaceRegWith(
Lo.getOperand(0).getReg(),
Hi.getOperand(0).getReg());
532 Lo.eraseFromParent();
536bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(
MachineFunction &Fn) {
542 bool MadeChange =
false;
548 if (!detectFoldable(
Hi,
Lo))
550 MadeChange |= detectAndFoldOffset(
Hi, *
Lo);
551 MadeChange |= foldIntoMemoryOps(
Hi, *
Lo);
560 return new RISCVMergeBaseOffsetOpt();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
const HexagonInstrInfo * TII
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
#define RISCV_MERGE_BASE_OFFSET_NAME
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
support::ulittle16_t & Lo
support::ulittle16_t & Hi
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
FunctionPass class - This class is used to implement most global optimizations.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
void ChangeToBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
ChangeToBA - Replace this operand with a new block address operand.
const BlockAddress * getBlockAddress() const
void setOffset(int64_t Offset)
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Register getReg() const
getReg - Returns the register number.
MCSymbol * getMCSymbol() const
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.