22#include "llvm/IR/IntrinsicsSPIRV.h"
24#define DEBUG_TYPE "spirv-lower"
60 unsigned Intrinsic)
const {
61 unsigned AlignIdx = 3;
63 case Intrinsic::spv_load:
66 case Intrinsic::spv_store: {
67 if (
I.getNumOperands() >= AlignIdx + 1) {
68 auto *AlignOp = cast<ConstantInt>(
I.getOperand(AlignIdx));
69 Info.align =
Align(AlignOp->getZExtValue());
72 cast<ConstantInt>(
I.getOperand(AlignIdx - 1))->getZExtValue());
73 Info.memVT = MVT::i64;
85std::pair<unsigned, const TargetRegisterClass *>
91 return std::make_pair(0u, RC);
94 RC = VT.
isVector() ? &SPIRV::vfIDRegClass
96 : &SPIRV::fIDRegClass);
98 RC = VT.
isVector() ? &SPIRV::vIDRegClass
100 : &SPIRV::iIDRegClass);
102 RC = &SPIRV::iIDRegClass;
104 return std::make_pair(0u, RC);
109 return TypeInst && TypeInst->
getOpcode() == SPIRV::OpFunctionParameter
128 MRI->setRegClass(NewReg, &SPIRV::iIDRegClass);
130 I.getOperand(OpIdx).setReg(NewReg);
137 SPIRV::StorageClass::StorageClass SC =
138 static_cast<SPIRV::StorageClass::StorageClass
>(
144 ResTy, MIB, SPIRV::AccessQualifier::ReadWrite, EmitIR);
156 Register OpReg =
I.getOperand(OpIdx).getReg();
159 if (!ResType || !OpType || OpType->
getOpcode() != SPIRV::OpTypePointer)
168 bool IsEqualTypes = IsSameMF ? ElemType == ResType
178 "insert validation bitcast: incompatible result and operand types");
188 constexpr unsigned OpIdx = 2;
190 Register OpReg =
I.getOperand(OpIdx).getReg();
193 if (!OpType || OpType->
getOpcode() != SPIRV::OpTypePointer)
196 if (!ElemType || ElemType->
getOpcode() == SPIRV::OpTypeEvent)
209 Register PtrReg =
I.getOperand(0).getReg();
214 if (!PonteeElemType || PonteeElemType->
getOpcode() == SPIRV::OpTypeVoid ||
215 (PonteeElemType->
getOpcode() == SPIRV::OpTypeInt &&
219 SPIRV::StorageClass::StorageClass SC =
220 static_cast<SPIRV::StorageClass::StorageClass
>(
235 Register OpReg =
I.getOperand(OpIdx).getReg();
238 if (!OpType || OpType->
getOpcode() != SPIRV::OpTypePointer)
241 if (!ElemType || ElemType->
getOpcode() != SPIRV::OpTypeStruct ||
249 unsigned MemberTypeOp = MemberType->
getOpcode();
250 if (MemberTypeOp != SPIRV::OpTypeVector && MemberTypeOp != SPIRV::OpTypeInt &&
251 MemberTypeOp != SPIRV::OpTypeFloat && MemberTypeOp != SPIRV::OpTypeBool)
255 SPIRV::StorageClass::StorageClass SC =
256 static_cast<SPIRV::StorageClass::StorageClass
>(
276 if (FunDef->
getOpcode() != SPIRV::OpFunction)
280 FunDef && FunDef->
getOpcode() == SPIRV::OpFunctionParameter &&
285 DefPtrType && DefPtrType->
getOpcode() == SPIRV::OpTypePointer
312 const Function *
F = dyn_cast<Function>(GV);
331 &FunCall->getParent()->getParent()->getRegInfo();
340 if (BaseTypeInst && BaseTypeInst->
getOpcode() == SPIRV::OpTypePointer) {
352 if (ProcessedMF.find(&MF) != ProcessedMF.end())
363 switch (
MI.getOpcode()) {
364 case SPIRV::OpAtomicLoad:
365 case SPIRV::OpAtomicExchange:
366 case SPIRV::OpAtomicCompareExchange:
367 case SPIRV::OpAtomicCompareExchangeWeak:
368 case SPIRV::OpAtomicIIncrement:
369 case SPIRV::OpAtomicIDecrement:
370 case SPIRV::OpAtomicIAdd:
371 case SPIRV::OpAtomicISub:
372 case SPIRV::OpAtomicSMin:
373 case SPIRV::OpAtomicUMin:
374 case SPIRV::OpAtomicSMax:
375 case SPIRV::OpAtomicUMax:
376 case SPIRV::OpAtomicAnd:
377 case SPIRV::OpAtomicOr:
378 case SPIRV::OpAtomicXor:
387 case SPIRV::OpAtomicStore:
398 case SPIRV::OpPtrCastToGeneric:
399 case SPIRV::OpGenericCastToPtr:
402 case SPIRV::OpInBoundsPtrAccessChain:
403 if (
MI.getNumOperands() == 4)
407 case SPIRV::OpFunctionCall:
410 if (
MI.getNumOperands() > 3)
414 case SPIRV::OpFunction:
422 case SPIRV::OpBitwiseOrS:
423 case SPIRV::OpBitwiseOrV:
428 case SPIRV::OpBitwiseAndS:
429 case SPIRV::OpBitwiseAndV:
434 case SPIRV::OpBitwiseXorS:
435 case SPIRV::OpBitwiseXorV:
440 case SPIRV::OpLifetimeStart:
441 case SPIRV::OpLifetimeStop:
442 if (
MI.getOperand(1).getImm() > 0)
445 case SPIRV::OpGroupAsyncCopy:
449 case SPIRV::OpGroupWaitEvents:
453 case SPIRV::OpConstantI: {
455 if (
Type->getOpcode() != SPIRV::OpTypeInt &&
MI.getOperand(2).isImm() &&
456 MI.getOperand(2).getImm() == 0) {
459 for (
unsigned i =
MI.getNumOperands() - 1; i > 1; --i)
466 ProcessedMF.insert(&MF);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Analysis containing CSE Info
unsigned const TargetRegisterInfo * TRI
static void doInsertBitcast(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I, Register OpReg, unsigned OpIdx, SPIRVType *NewPtrType)
static void validateLifetimeStart(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I)
static void validateGroupAsyncCopyPtr(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I, unsigned OpIdx)
static void validateGroupWaitEventsPtr(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I)
Register getTypeReg(MachineRegisterInfo *MRI, Register OpReg)
void validateAccessChain(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I)
void validateFunCallMachineDef(const SPIRVSubtarget &STI, MachineRegisterInfo *DefMRI, MachineRegisterInfo *CallMRI, SPIRVGlobalRegistry &GR, MachineInstr &FunCall, MachineInstr *FunDef)
void validateForwardCalls(const SPIRVSubtarget &STI, MachineRegisterInfo *DefMRI, SPIRVGlobalRegistry &GR, MachineInstr &FunDef)
const Function * validateFunCall(const SPIRVSubtarget &STI, MachineRegisterInfo *CallMRI, SPIRVGlobalRegistry &GR, MachineInstr &FunCall)
static void validatePtrTypes(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I, unsigned OpIdx, SPIRVType *ResType, const Type *ResTy=nullptr)
static SPIRVType * createNewPtrType(SPIRVGlobalRegistry &GR, MachineInstr &I, SPIRVType *OpType, bool ReuseType, bool EmitIR, SPIRVType *ResType, const Type *ResTy)
This class represents a function call, abstracting a target machine's calling convention.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
This is an important class for using LLVM in a threaded context.
uint64_t getScalarSizeInBits() const
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
unsigned getNumOperands() const
Retuns the total number of operands.
const MachineOperand & getOperand(unsigned i) const
Flags
Flags values. These may be or'd together.
const GlobalValue * getGlobal() const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Wrapper class representing virtual and physical registers.
SPIRVType * getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const
void addForwardCall(const Function *F, MachineInstr *MI)
const Type * getTypeForSPIRVType(const SPIRVType *Ty) const
bool isBitcastCompatible(const SPIRVType *Type1, const SPIRVType *Type2) const
const MachineInstr * getFunctionDefinition(const Function *F)
SPIRVType * getPointeeType(SPIRVType *PtrType)
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
SmallPtrSet< MachineInstr *, 8 > * getForwardCalls(const Function *F)
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
MachineFunction * setCurrentFunc(MachineFunction &MF)
SPIRVType * getOrCreateSPIRVPointerType(SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SClass=SPIRV::StorageClass::Function)
const Function * getFunctionByDefinition(const MachineInstr *MI)
const SPIRVInstrInfo * getInstrInfo() const override
SPIRVGlobalRegistry * getSPIRVGlobalRegistry() const
const SPIRVRegisterInfo * getRegisterInfo() const override
const RegisterBankInfo * getRegBankInfo() const override
unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const override
Return the number of registers that this ValueType will eventually require.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
StringRef - Represent a constant reference to a string, i.e.
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
static TargetExtType * get(LLVMContext &Context, StringRef Name, ArrayRef< Type * > Types=std::nullopt, ArrayRef< unsigned > Ints=std::nullopt)
Return a target extension type having the specified name and optional type and integer parameters.
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
static IntegerType * getInt8Ty(LLVMContext &C)
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
This is an optimization pass for GlobalISel generic memory operations.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This struct is a compact representation of a valid (non-zero power of two) alignment.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isVector() const
Return true if this is a vector value type.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.