LLVM 20.0.0git
SPIRVISelLowering.cpp
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1//===- SPIRVISelLowering.cpp - SPIR-V DAG Lowering Impl ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the SPIRVTargetLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SPIRVISelLowering.h"
14#include "SPIRV.h"
15#include "SPIRVInstrInfo.h"
17#include "SPIRVRegisterInfo.h"
18#include "SPIRVSubtarget.h"
19#include "SPIRVTargetMachine.h"
22#include "llvm/IR/IntrinsicsSPIRV.h"
23
24#define DEBUG_TYPE "spirv-lower"
25
26using namespace llvm;
27
29 LLVMContext &Context, CallingConv::ID CC, EVT VT) const {
30 // This code avoids CallLowering fail inside getVectorTypeBreakdown
31 // on v3i1 arguments. Maybe we need to return 1 for all types.
32 // TODO: remove it once this case is supported by the default implementation.
33 if (VT.isVector() && VT.getVectorNumElements() == 3 &&
34 (VT.getVectorElementType() == MVT::i1 ||
35 VT.getVectorElementType() == MVT::i8))
36 return 1;
37 if (!VT.isVector() && VT.isInteger() && VT.getSizeInBits() <= 64)
38 return 1;
39 return getNumRegisters(Context, VT);
40}
41
44 EVT VT) const {
45 // This code avoids CallLowering fail inside getVectorTypeBreakdown
46 // on v3i1 arguments. Maybe we need to return i32 for all types.
47 // TODO: remove it once this case is supported by the default implementation.
48 if (VT.isVector() && VT.getVectorNumElements() == 3) {
49 if (VT.getVectorElementType() == MVT::i1)
50 return MVT::v4i1;
51 else if (VT.getVectorElementType() == MVT::i8)
52 return MVT::v4i8;
53 }
54 return getRegisterType(Context, VT);
55}
56
58 const CallInst &I,
60 unsigned Intrinsic) const {
61 unsigned AlignIdx = 3;
62 switch (Intrinsic) {
63 case Intrinsic::spv_load:
64 AlignIdx = 2;
65 [[fallthrough]];
66 case Intrinsic::spv_store: {
67 if (I.getNumOperands() >= AlignIdx + 1) {
68 auto *AlignOp = cast<ConstantInt>(I.getOperand(AlignIdx));
69 Info.align = Align(AlignOp->getZExtValue());
70 }
71 Info.flags = static_cast<MachineMemOperand::Flags>(
72 cast<ConstantInt>(I.getOperand(AlignIdx - 1))->getZExtValue());
73 Info.memVT = MVT::i64;
74 // TODO: take into account opaque pointers (don't use getElementType).
75 // MVT::getVT(PtrTy->getElementType());
76 return true;
77 break;
78 }
79 default:
80 break;
81 }
82 return false;
83}
84
85std::pair<unsigned, const TargetRegisterClass *>
87 StringRef Constraint,
88 MVT VT) const {
89 const TargetRegisterClass *RC = nullptr;
90 if (Constraint.starts_with("{"))
91 return std::make_pair(0u, RC);
92
93 if (VT.isFloatingPoint())
94 RC = VT.isVector() ? &SPIRV::vfIDRegClass
95 : (VT.getScalarSizeInBits() > 32 ? &SPIRV::fID64RegClass
96 : &SPIRV::fIDRegClass);
97 else if (VT.isInteger())
98 RC = VT.isVector() ? &SPIRV::vIDRegClass
99 : (VT.getScalarSizeInBits() > 32 ? &SPIRV::iID64RegClass
100 : &SPIRV::iIDRegClass);
101 else
102 RC = &SPIRV::iIDRegClass;
103
104 return std::make_pair(0u, RC);
105}
106
108 SPIRVType *TypeInst = MRI->getVRegDef(OpReg);
109 return TypeInst && TypeInst->getOpcode() == SPIRV::OpFunctionParameter
110 ? TypeInst->getOperand(1).getReg()
111 : OpReg;
112}
113
116 Register OpReg, unsigned OpIdx,
117 SPIRVType *NewPtrType) {
118 Register NewReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
119 MachineIRBuilder MIB(I);
120 bool Res = MIB.buildInstr(SPIRV::OpBitcast)
121 .addDef(NewReg)
122 .addUse(GR.getSPIRVTypeID(NewPtrType))
123 .addUse(OpReg)
125 *STI.getRegBankInfo());
126 if (!Res)
127 report_fatal_error("insert validation bitcast: cannot constrain all uses");
128 MRI->setRegClass(NewReg, &SPIRV::iIDRegClass);
129 GR.assignSPIRVTypeToVReg(NewPtrType, NewReg, MIB.getMF());
130 I.getOperand(OpIdx).setReg(NewReg);
131}
132
134 SPIRVType *OpType, bool ReuseType,
135 bool EmitIR, SPIRVType *ResType,
136 const Type *ResTy) {
137 SPIRV::StorageClass::StorageClass SC =
138 static_cast<SPIRV::StorageClass::StorageClass>(
139 OpType->getOperand(1).getImm());
140 MachineIRBuilder MIB(I);
141 SPIRVType *NewBaseType =
142 ReuseType ? ResType
144 ResTy, MIB, SPIRV::AccessQualifier::ReadWrite, EmitIR);
145 return GR.getOrCreateSPIRVPointerType(NewBaseType, MIB, SC);
146}
147
148// Insert a bitcast before the instruction to keep SPIR-V code valid
149// when there is a type mismatch between results and operand types.
150static void validatePtrTypes(const SPIRVSubtarget &STI,
152 MachineInstr &I, unsigned OpIdx,
153 SPIRVType *ResType, const Type *ResTy = nullptr) {
154 // Get operand type
155 MachineFunction *MF = I.getParent()->getParent();
156 Register OpReg = I.getOperand(OpIdx).getReg();
157 Register OpTypeReg = getTypeReg(MRI, OpReg);
158 SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpTypeReg, MF);
159 if (!ResType || !OpType || OpType->getOpcode() != SPIRV::OpTypePointer)
160 return;
161 // Get operand's pointee type
162 Register ElemTypeReg = OpType->getOperand(2).getReg();
163 SPIRVType *ElemType = GR.getSPIRVTypeForVReg(ElemTypeReg, MF);
164 if (!ElemType)
165 return;
166 // Check if we need a bitcast to make a statement valid
167 bool IsSameMF = MF == ResType->getParent()->getParent();
168 bool IsEqualTypes = IsSameMF ? ElemType == ResType
169 : GR.getTypeForSPIRVType(ElemType) == ResTy;
170 if (IsEqualTypes)
171 return;
172 // There is a type mismatch between results and operand types
173 // and we insert a bitcast before the instruction to keep SPIR-V code valid
174 SPIRVType *NewPtrType =
175 createNewPtrType(GR, I, OpType, IsSameMF, false, ResType, ResTy);
176 if (!GR.isBitcastCompatible(NewPtrType, OpType))
178 "insert validation bitcast: incompatible result and operand types");
179 doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType);
180}
181
182// Insert a bitcast before OpGroupWaitEvents if the last argument is a pointer
183// that doesn't point to OpTypeEvent.
187 MachineInstr &I) {
188 constexpr unsigned OpIdx = 2;
189 MachineFunction *MF = I.getParent()->getParent();
190 Register OpReg = I.getOperand(OpIdx).getReg();
191 Register OpTypeReg = getTypeReg(MRI, OpReg);
192 SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpTypeReg, MF);
193 if (!OpType || OpType->getOpcode() != SPIRV::OpTypePointer)
194 return;
195 SPIRVType *ElemType = GR.getSPIRVTypeForVReg(OpType->getOperand(2).getReg());
196 if (!ElemType || ElemType->getOpcode() == SPIRV::OpTypeEvent)
197 return;
198 // Insert a bitcast before the instruction to keep SPIR-V code valid.
199 LLVMContext &Context = MF->getFunction().getContext();
200 SPIRVType *NewPtrType =
201 createNewPtrType(GR, I, OpType, false, true, nullptr,
202 TargetExtType::get(Context, "spirv.Event"));
203 doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType);
204}
205
209 Register PtrReg = I.getOperand(0).getReg();
210 MachineFunction *MF = I.getParent()->getParent();
211 Register PtrTypeReg = getTypeReg(MRI, PtrReg);
212 SPIRVType *PtrType = GR.getSPIRVTypeForVReg(PtrTypeReg, MF);
213 SPIRVType *PonteeElemType = PtrType ? GR.getPointeeType(PtrType) : nullptr;
214 if (!PonteeElemType || PonteeElemType->getOpcode() == SPIRV::OpTypeVoid ||
215 (PonteeElemType->getOpcode() == SPIRV::OpTypeInt &&
216 PonteeElemType->getOperand(1).getImm() == 8))
217 return;
218 // To keep the code valid a bitcast must be inserted
219 SPIRV::StorageClass::StorageClass SC =
220 static_cast<SPIRV::StorageClass::StorageClass>(
221 PtrType->getOperand(1).getImm());
222 MachineIRBuilder MIB(I);
223 LLVMContext &Context = MF->getFunction().getContext();
224 SPIRVType *ElemType =
226 SPIRVType *NewPtrType = GR.getOrCreateSPIRVPointerType(ElemType, MIB, SC);
227 doInsertBitcast(STI, MRI, GR, I, PtrReg, 0, NewPtrType);
228}
229
233 unsigned OpIdx) {
234 MachineFunction *MF = I.getParent()->getParent();
235 Register OpReg = I.getOperand(OpIdx).getReg();
236 Register OpTypeReg = getTypeReg(MRI, OpReg);
237 SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpTypeReg, MF);
238 if (!OpType || OpType->getOpcode() != SPIRV::OpTypePointer)
239 return;
240 SPIRVType *ElemType = GR.getSPIRVTypeForVReg(OpType->getOperand(2).getReg());
241 if (!ElemType || ElemType->getOpcode() != SPIRV::OpTypeStruct ||
242 ElemType->getNumOperands() != 2)
243 return;
244 // It's a structure-wrapper around another type with a single member field.
245 SPIRVType *MemberType =
246 GR.getSPIRVTypeForVReg(ElemType->getOperand(1).getReg());
247 if (!MemberType)
248 return;
249 unsigned MemberTypeOp = MemberType->getOpcode();
250 if (MemberTypeOp != SPIRV::OpTypeVector && MemberTypeOp != SPIRV::OpTypeInt &&
251 MemberTypeOp != SPIRV::OpTypeFloat && MemberTypeOp != SPIRV::OpTypeBool)
252 return;
253 // It's a structure-wrapper around a valid type. Insert a bitcast before the
254 // instruction to keep SPIR-V code valid.
255 SPIRV::StorageClass::StorageClass SC =
256 static_cast<SPIRV::StorageClass::StorageClass>(
257 OpType->getOperand(1).getImm());
258 MachineIRBuilder MIB(I);
259 SPIRVType *NewPtrType = GR.getOrCreateSPIRVPointerType(MemberType, MIB, SC);
260 doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType);
261}
262
263// Insert a bitcast before the function call instruction to keep SPIR-V code
264// valid when there is a type mismatch between actual and expected types of an
265// argument:
266// %formal = OpFunctionParameter %formal_type
267// ...
268// %res = OpFunctionCall %ty %fun %actual ...
269// implies that %actual is of %formal_type, and in case of opaque pointers.
270// We may need to insert a bitcast to ensure this.
272 MachineRegisterInfo *DefMRI,
273 MachineRegisterInfo *CallMRI,
274 SPIRVGlobalRegistry &GR, MachineInstr &FunCall,
275 MachineInstr *FunDef) {
276 if (FunDef->getOpcode() != SPIRV::OpFunction)
277 return;
278 unsigned OpIdx = 3;
279 for (FunDef = FunDef->getNextNode();
280 FunDef && FunDef->getOpcode() == SPIRV::OpFunctionParameter &&
281 OpIdx < FunCall.getNumOperands();
282 FunDef = FunDef->getNextNode(), OpIdx++) {
283 SPIRVType *DefPtrType = DefMRI->getVRegDef(FunDef->getOperand(1).getReg());
284 SPIRVType *DefElemType =
285 DefPtrType && DefPtrType->getOpcode() == SPIRV::OpTypePointer
286 ? GR.getSPIRVTypeForVReg(DefPtrType->getOperand(2).getReg(),
287 DefPtrType->getParent()->getParent())
288 : nullptr;
289 if (DefElemType) {
290 const Type *DefElemTy = GR.getTypeForSPIRVType(DefElemType);
291 // validatePtrTypes() works in the context if the call site
292 // When we process historical records about forward calls
293 // we need to switch context to the (forward) call site and
294 // then restore it back to the current machine function.
295 MachineFunction *CurMF =
296 GR.setCurrentFunc(*FunCall.getParent()->getParent());
297 validatePtrTypes(STI, CallMRI, GR, FunCall, OpIdx, DefElemType,
298 DefElemTy);
299 GR.setCurrentFunc(*CurMF);
300 }
301 }
302}
303
304// Ensure there is no mismatch between actual and expected arg types: calls
305// with a processed definition. Return Function pointer if it's a forward
306// call (ahead of definition), and nullptr otherwise.
308 MachineRegisterInfo *CallMRI,
310 MachineInstr &FunCall) {
311 const GlobalValue *GV = FunCall.getOperand(2).getGlobal();
312 const Function *F = dyn_cast<Function>(GV);
313 MachineInstr *FunDef =
314 const_cast<MachineInstr *>(GR.getFunctionDefinition(F));
315 if (!FunDef)
316 return F;
317 MachineRegisterInfo *DefMRI = &FunDef->getParent()->getParent()->getRegInfo();
318 validateFunCallMachineDef(STI, DefMRI, CallMRI, GR, FunCall, FunDef);
319 return nullptr;
320}
321
322// Ensure there is no mismatch between actual and expected arg types: calls
323// ahead of a processed definition.
326 MachineInstr &FunDef) {
327 const Function *F = GR.getFunctionByDefinition(&FunDef);
329 for (MachineInstr *FunCall : *FwdCalls) {
330 MachineRegisterInfo *CallMRI =
331 &FunCall->getParent()->getParent()->getRegInfo();
332 validateFunCallMachineDef(STI, DefMRI, CallMRI, GR, *FunCall, &FunDef);
333 }
334}
335
336// Validation of an access chain.
339 SPIRVType *BaseTypeInst = GR.getSPIRVTypeForVReg(I.getOperand(0).getReg());
340 if (BaseTypeInst && BaseTypeInst->getOpcode() == SPIRV::OpTypePointer) {
341 SPIRVType *BaseElemType =
342 GR.getSPIRVTypeForVReg(BaseTypeInst->getOperand(2).getReg());
343 validatePtrTypes(STI, MRI, GR, I, 2, BaseElemType);
344 }
345}
346
347// TODO: the logic of inserting additional bitcast's is to be moved
348// to pre-IRTranslation passes eventually
350 // finalizeLowering() is called twice (see GlobalISel/InstructionSelect.cpp)
351 // We'd like to avoid the needless second processing pass.
352 if (ProcessedMF.find(&MF) != ProcessedMF.end())
353 return;
354
357 GR.setCurrentFunc(MF);
358 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
360 for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
361 MBBI != MBBE;) {
362 MachineInstr &MI = *MBBI++;
363 switch (MI.getOpcode()) {
364 case SPIRV::OpAtomicLoad:
365 case SPIRV::OpAtomicExchange:
366 case SPIRV::OpAtomicCompareExchange:
367 case SPIRV::OpAtomicCompareExchangeWeak:
368 case SPIRV::OpAtomicIIncrement:
369 case SPIRV::OpAtomicIDecrement:
370 case SPIRV::OpAtomicIAdd:
371 case SPIRV::OpAtomicISub:
372 case SPIRV::OpAtomicSMin:
373 case SPIRV::OpAtomicUMin:
374 case SPIRV::OpAtomicSMax:
375 case SPIRV::OpAtomicUMax:
376 case SPIRV::OpAtomicAnd:
377 case SPIRV::OpAtomicOr:
378 case SPIRV::OpAtomicXor:
379 // for the above listed instructions
380 // OpAtomicXXX <ResType>, ptr %Op, ...
381 // implies that %Op is a pointer to <ResType>
382 case SPIRV::OpLoad:
383 // OpLoad <ResType>, ptr %Op implies that %Op is a pointer to <ResType>
384 validatePtrTypes(STI, MRI, GR, MI, 2,
385 GR.getSPIRVTypeForVReg(MI.getOperand(0).getReg()));
386 break;
387 case SPIRV::OpAtomicStore:
388 // OpAtomicStore ptr %Op, <Scope>, <Mem>, <Obj>
389 // implies that %Op points to the <Obj>'s type
390 validatePtrTypes(STI, MRI, GR, MI, 0,
391 GR.getSPIRVTypeForVReg(MI.getOperand(3).getReg()));
392 break;
393 case SPIRV::OpStore:
394 // OpStore ptr %Op, <Obj> implies that %Op points to the <Obj>'s type
395 validatePtrTypes(STI, MRI, GR, MI, 0,
396 GR.getSPIRVTypeForVReg(MI.getOperand(1).getReg()));
397 break;
398 case SPIRV::OpPtrCastToGeneric:
399 case SPIRV::OpGenericCastToPtr:
400 validateAccessChain(STI, MRI, GR, MI);
401 break;
402 case SPIRV::OpInBoundsPtrAccessChain:
403 if (MI.getNumOperands() == 4)
404 validateAccessChain(STI, MRI, GR, MI);
405 break;
406
407 case SPIRV::OpFunctionCall:
408 // ensure there is no mismatch between actual and expected arg types:
409 // calls with a processed definition
410 if (MI.getNumOperands() > 3)
411 if (const Function *F = validateFunCall(STI, MRI, GR, MI))
412 GR.addForwardCall(F, &MI);
413 break;
414 case SPIRV::OpFunction:
415 // ensure there is no mismatch between actual and expected arg types:
416 // calls ahead of a processed definition
417 validateForwardCalls(STI, MRI, GR, MI);
418 break;
419
420 // ensure that LLVM IR bitwise instructions result in logical SPIR-V
421 // instructions when applied to bool type
422 case SPIRV::OpBitwiseOrS:
423 case SPIRV::OpBitwiseOrV:
424 if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(),
425 SPIRV::OpTypeBool))
426 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalOr));
427 break;
428 case SPIRV::OpBitwiseAndS:
429 case SPIRV::OpBitwiseAndV:
430 if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(),
431 SPIRV::OpTypeBool))
432 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalAnd));
433 break;
434 case SPIRV::OpBitwiseXorS:
435 case SPIRV::OpBitwiseXorV:
436 if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(),
437 SPIRV::OpTypeBool))
438 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalNotEqual));
439 break;
440 case SPIRV::OpLifetimeStart:
441 case SPIRV::OpLifetimeStop:
442 if (MI.getOperand(1).getImm() > 0)
443 validateLifetimeStart(STI, MRI, GR, MI);
444 break;
445 case SPIRV::OpGroupAsyncCopy:
446 validateGroupAsyncCopyPtr(STI, MRI, GR, MI, 3);
447 validateGroupAsyncCopyPtr(STI, MRI, GR, MI, 4);
448 break;
449 case SPIRV::OpGroupWaitEvents:
450 // OpGroupWaitEvents ..., ..., <pointer to OpTypeEvent>
452 break;
453 case SPIRV::OpConstantI: {
454 SPIRVType *Type = GR.getSPIRVTypeForVReg(MI.getOperand(1).getReg());
455 if (Type->getOpcode() != SPIRV::OpTypeInt && MI.getOperand(2).isImm() &&
456 MI.getOperand(2).getImm() == 0) {
457 // Validate the null constant of a target extension type
458 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull));
459 for (unsigned i = MI.getNumOperands() - 1; i > 1; --i)
460 MI.removeOperand(i);
461 }
462 } break;
463 }
464 }
465 }
466 ProcessedMF.insert(&MF);
468}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator MBBI
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static void doInsertBitcast(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I, Register OpReg, unsigned OpIdx, SPIRVType *NewPtrType)
static void validateLifetimeStart(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I)
static void validateGroupAsyncCopyPtr(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I, unsigned OpIdx)
static void validateGroupWaitEventsPtr(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I)
Register getTypeReg(MachineRegisterInfo *MRI, Register OpReg)
void validateAccessChain(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I)
void validateFunCallMachineDef(const SPIRVSubtarget &STI, MachineRegisterInfo *DefMRI, MachineRegisterInfo *CallMRI, SPIRVGlobalRegistry &GR, MachineInstr &FunCall, MachineInstr *FunDef)
void validateForwardCalls(const SPIRVSubtarget &STI, MachineRegisterInfo *DefMRI, SPIRVGlobalRegistry &GR, MachineInstr &FunDef)
const Function * validateFunCall(const SPIRVSubtarget &STI, MachineRegisterInfo *CallMRI, SPIRVGlobalRegistry &GR, MachineInstr &FunCall)
static void validatePtrTypes(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR, MachineInstr &I, unsigned OpIdx, SPIRVType *ResType, const Type *ResTy=nullptr)
static SPIRVType * createNewPtrType(SPIRVGlobalRegistry &GR, MachineInstr &I, SPIRVType *OpType, bool ReuseType, bool EmitIR, SPIRVType *ResType, const Type *ResTy)
This class represents a function call, abstracting a target machine's calling convention.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:380
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
uint64_t getScalarSizeInBits() const
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:569
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:346
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:572
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:579
Flags
Flags values. These may be or'd together.
const GlobalValue * getGlobal() const
int64_t getImm() const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SPIRVType * getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const
void addForwardCall(const Function *F, MachineInstr *MI)
const Type * getTypeForSPIRVType(const SPIRVType *Ty) const
bool isBitcastCompatible(const SPIRVType *Type1, const SPIRVType *Type2) const
const MachineInstr * getFunctionDefinition(const Function *F)
SPIRVType * getPointeeType(SPIRVType *PtrType)
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
SmallPtrSet< MachineInstr *, 8 > * getForwardCalls(const Function *F)
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
MachineFunction * setCurrentFunc(MachineFunction &MF)
SPIRVType * getOrCreateSPIRVPointerType(SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SClass=SPIRV::StorageClass::Function)
const Function * getFunctionByDefinition(const MachineInstr *MI)
const SPIRVInstrInfo * getInstrInfo() const override
SPIRVGlobalRegistry * getSPIRVGlobalRegistry() const
const SPIRVRegisterInfo * getRegisterInfo() const override
const RegisterBankInfo * getRegBankInfo() const override
unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const override
Return the number of registers that this ValueType will eventually require.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:502
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:250
static TargetExtType * get(LLVMContext &Context, StringRef Name, ArrayRef< Type * > Types=std::nullopt, ArrayRef< unsigned > Ints=std::nullopt)
Return a target extension type having the specified name and optional type and integer parameters.
Definition: Type.cpp:784
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
static IntegerType * getInt8Ty(LLVMContext &C)
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:353
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:35
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:359
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:168
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:319
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:327
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:152