LLVM 23.0.0git
MachineLoopUtils.cpp
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1//=- MachineLoopUtils.cpp - Functions for manipulating loops ----------------=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
13#include <iterator>
14using namespace llvm;
15
16namespace {
17// MI's parent and BB are clones of each other. Find the equivalent copy of MI
18// in BB.
19MachineInstr &findEquivalentInstruction(MachineInstr &MI,
21 MachineBasicBlock *PB = MI.getParent();
22 unsigned Offset = std::distance(PB->instr_begin(), MachineBasicBlock::instr_iterator(MI));
23 return *std::next(BB->instr_begin(), Offset);
24}
25} // namespace
26
30 const TargetInstrInfo *TII) {
31 MachineFunction &MF = *Loop->getParent();
32 MachineBasicBlock *Preheader = *Loop->pred_begin();
33 if (Preheader == Loop)
34 Preheader = *std::next(Loop->pred_begin());
35 MachineBasicBlock *Exit = *Loop->succ_begin();
36 if (Exit == Loop)
37 Exit = *std::next(Loop->succ_begin());
38
39 MachineBasicBlock *NewBB = MF.CreateMachineBasicBlock(Loop->getBasicBlock());
40 if (Direction == LPD_Front)
41 MF.insert(Loop->getIterator(), NewBB);
42 else
43 MF.insert(std::next(Loop->getIterator()), NewBB);
44
46 auto InsertPt = NewBB->end();
47 for (MachineInstr &MI : *Loop) {
48 MachineInstr *NewMI = MF.CloneMachineInstr(&MI);
49 NewBB->insert(InsertPt, NewMI);
50 for (MachineOperand &MO : NewMI->defs()) {
51 Register OrigR = MO.getReg();
52 if (OrigR.isPhysical())
53 continue;
54 Register &R = Remaps[OrigR];
55 R = MRI.createVirtualRegister(MRI.getRegClass(OrigR));
56 MO.setReg(R);
57
58 if (Direction == LPD_Back) {
59 // Replace all uses outside the original loop with the new register.
60 // FIXME: is the use_iterator stable enough to mutate register uses
61 // while iterating?
63 for (auto &Use : MRI.use_operands(OrigR))
64 if (Use.getParent()->getParent() != Loop)
65 Uses.push_back(&Use);
66 for (auto *Use : Uses) {
67 const TargetRegisterClass *ConstrainRegClass =
68 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg()));
69 assert(ConstrainRegClass &&
70 "Expected a valid constrained register class!");
71 (void)ConstrainRegClass;
72 Use->setReg(R);
73 }
74 }
75 }
76 }
77
78 for (auto I = NewBB->getFirstNonPHI(); I != NewBB->end(); ++I)
79 for (MachineOperand &MO : I->uses())
80 if (MO.isReg())
81 if (auto It = Remaps.find(MO.getReg()); It != Remaps.end())
82 MO.setReg(It->second);
83
84 for (auto I = NewBB->begin(); I->isPHI(); ++I) {
85 MachineInstr &MI = *I;
86 unsigned LoopRegIdx = 3, InitRegIdx = 1;
87 if (MI.getOperand(2).getMBB() != Preheader)
88 std::swap(LoopRegIdx, InitRegIdx);
89 MachineInstr &OrigPhi = findEquivalentInstruction(MI, Loop);
90 assert(OrigPhi.isPHI());
91 if (Direction == LPD_Front) {
92 // When peeling front, we are only left with the initial value from the
93 // preheader.
94 Register R = MI.getOperand(LoopRegIdx).getReg();
95 if (auto It = Remaps.find(R); It != Remaps.end())
96 R = It->second;
97 OrigPhi.getOperand(InitRegIdx).setReg(R);
98 MI.removeOperand(LoopRegIdx + 1);
99 MI.removeOperand(LoopRegIdx + 0);
100 } else {
101 // When peeling back, the initial value is the loop-carried value from
102 // the original loop.
103 Register LoopReg = OrigPhi.getOperand(LoopRegIdx).getReg();
104 MI.getOperand(LoopRegIdx).setReg(LoopReg);
105 MI.removeOperand(InitRegIdx + 1);
106 MI.removeOperand(InitRegIdx + 0);
107 }
108 }
109
110 DebugLoc DL;
111 if (Direction == LPD_Front) {
112 Preheader->ReplaceUsesOfBlockWith(Loop, NewBB);
113 NewBB->addSuccessor(Loop);
114 Loop->replacePhiUsesWith(Preheader, NewBB);
115 if (auto PreheaderLayoutSuccessor = std::next(Preheader->getIterator());
116 PreheaderLayoutSuccessor != Preheader->getParent()->end())
117 Preheader->updateTerminator(&*PreheaderLayoutSuccessor);
118 TII->removeBranch(*NewBB);
119 TII->insertBranch(*NewBB, Loop, nullptr, {}, DL);
120 } else {
121 Loop->replaceSuccessor(Exit, NewBB);
122 Exit->replacePhiUsesWith(Loop, NewBB);
123 NewBB->addSuccessor(Exit);
124
125 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
127 bool CanAnalyzeBr = !TII->analyzeBranch(*Loop, TBB, FBB, Cond);
128 (void)CanAnalyzeBr;
129 assert(CanAnalyzeBr && "Must be able to analyze the loop branch!");
130 TII->removeBranch(*Loop);
131 TII->insertBranch(*Loop, TBB == Exit ? NewBB : TBB,
132 FBB == Exit ? NewBB : FBB, Cond, DL);
133 if (TII->removeBranch(*NewBB) > 0)
134 TII->insertBranch(*NewBB, Exit, nullptr, {}, DL);
135 }
136
137 return NewBB;
138}
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition MD5.cpp:57
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
Remove Loads Into Fake Uses
A debug info location.
Definition DebugLoc.h:123
iterator find(const_arg_type_t< KeyT > Val)
Definition DenseMap.h:178
iterator end()
Definition DenseMap.h:81
Represents a single loop in the control flow graph.
Definition LoopInfo.h:40
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
LLVM_ABI void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor)
Update the terminator instructions in block to account for changes to block layout which may have bee...
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
LLVM_ABI iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Instructions::iterator instr_iterator
LLVM_ABI void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Given a machine basic block that branched to 'Old', change the code and CFG so that it branches to 'N...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
void insert(iterator MBBI, MachineBasicBlock *MBB)
Representation of each machine instruction.
mop_range defs()
Returns all explicit operands that are register definitions.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
LLVM_ABI void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition Register.h:20
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition Register.h:83
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
A Use represents the edge between a Value definition and its users.
Definition Use.h:35
self_iterator getIterator()
Definition ilist_node.h:123
This is an optimization pass for GlobalISel generic memory operations.
Definition Types.h:26
@ Offset
Definition DWP.cpp:532
MachineBasicBlock * PeelSingleBlockLoop(LoopPeelDirection Direction, MachineBasicBlock *Loop, MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
Peels a single block loop.
@ LPD_Back
Peel the last iteration of the loop.
@ LPD_Front
Peel the first iteration of the loop.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition BitVector.h:872