20 switch (
MI->getOpcode()) {
37 int64_t &Off0, int64_t &Off1) {
58 return llabs(Off0 - Off1) < StoreSize;
70 return OriginalResult;
81 return OriginalResult;
static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1, int64_t &Off0, int64_t &Off1)
static bool needReorderStoreMI(const MachineInstr *MI)
static const MachineOperand & getLdStOffsetOp(const MachineInstr &MI)
Returns the immediate offset operator of a load/store.
static bool hasUnscaledLdStOffset(unsigned Opc)
Return true if it has an unscaled load/store offset.
static bool isPairedLdSt(const MachineInstr &MI)
Returns whether the instruction is a paired load/store.
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
static const MachineOperand & getLdStBaseOp(const MachineInstr &MI)
Returns the base register operator of a load/store.
bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) override
Apply a set of heuristics to a new candidate for PostRA scheduling.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MachineOperand class - Representation of each machine instruction operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
virtual bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand)
Apply a set of heuristics to a new candidate for PostRA scheduling.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
This is an optimization pass for GlobalISel generic memory operations.
Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of p...