27#define DEBUG_TYPE "ve-instr-info"
31#define GET_INSTRINFO_CTOR_DTOR
32#include "VEGenInstrInfo.inc"
35void VEInstrInfo::anchor() {}
38 :
VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {}
99#define BRKIND(NAME) (Opc == NAME##a || Opc == NAME##a_nt || Opc == NAME##a_t)
103 "Branch relative word/double/float always instructions should not be "
114#define BRKIND(NAME) \
115 (Opc == NAME##rr || Opc == NAME##rr_nt || Opc == NAME##rr_t || \
116 Opc == NAME##ir || Opc == NAME##ir_nt || Opc == NAME##ir_t)
126#define BRKIND(NAME) \
127 (Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t)
131 "Branch word/double/float always instructions should not be used!");
147 bool AllowModify)
const {
152 if (!isUnpredicatedTerminator(*
I))
157 unsigned LastOpc = LastInst->
getOpcode();
160 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
175 unsigned SecondLastOpc = SecondLastInst->
getOpcode();
182 LastInst = SecondLastInst;
184 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
189 SecondLastInst = &*
I;
190 SecondLastOpc = SecondLastInst->
getOpcode();
195 if (SecondLastInst &&
I !=
MBB.
begin() && isUnpredicatedTerminator(*--
I))
217 I->eraseFromParent();
230 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
232 "VE branch conditions should have three component!");
233 assert(!BytesAdded &&
"code size not handled");
236 assert(!FBB &&
"Unconditional branch with multiple successors!");
252 if (
TRI->getRegSizeInBits(Reg,
MRI) == 32) {
253 opc[0] = VE::BRCFWir;
254 opc[1] = VE::BRCFWrr;
256 opc[0] = VE::BRCFLir;
257 opc[1] = VE::BRCFLrr;
260 if (
TRI->getRegSizeInBits(Reg,
MRI) == 32) {
261 opc[0] = VE::BRCFSir;
262 opc[1] = VE::BRCFSrr;
264 opc[0] = VE::BRCFDir;
265 opc[1] = VE::BRCFDrr;
291 int *BytesRemoved)
const {
292 assert(!BytesRemoved &&
"code size not handled");
299 if (
I->isDebugValue())
306 I->eraseFromParent();
321 return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||
322 VE::F32RegClass.contains(Reg);
329 const unsigned *SubRegIdx,
333 for (
unsigned Idx = 0;
Idx != NumSubRegs; ++
Idx) {
336 assert(SubDest && SubSrc &&
"Bad sub-register");
343 }
else if (MCID.
getOpcode() == VE::ANDMmm) {
361 bool KillSrc,
bool RenamableDest,
362 bool RenamableSrc)
const {
368 }
else if (VE::V64RegClass.
contains(DestReg, SrcReg)) {
377 Register SubTmp =
TRI->getSubReg(TmpReg, VE::sub_i32);
387 }
else if (VE::VMRegClass.
contains(DestReg, SrcReg)) {
391 }
else if (VE::VM512RegClass.
contains(DestReg, SrcReg)) {
393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd};
394 unsigned int NumSubRegs = 2;
397 }
else if (VE::F128RegClass.
contains(DestReg, SrcReg)) {
399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd};
400 unsigned int NumSubRegs = 2;
417 int &FrameIndex)
const {
418 if (
MI.getOpcode() == VE::LDrii ||
419 MI.getOpcode() == VE::LDLSXrii ||
420 MI.getOpcode() == VE::LDUrii ||
421 MI.getOpcode() == VE::LDQrii ||
422 MI.getOpcode() == VE::LDVMrii ||
423 MI.getOpcode() == VE::LDVM512rii
425 if (
MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() &&
426 MI.getOperand(2).getImm() == 0 &&
MI.getOperand(3).isImm() &&
427 MI.getOperand(3).getImm() == 0) {
428 FrameIndex =
MI.getOperand(1).getIndex();
429 return MI.getOperand(0).getReg();
441 int &FrameIndex)
const {
442 if (
MI.getOpcode() == VE::STrii ||
443 MI.getOpcode() == VE::STLrii ||
444 MI.getOpcode() == VE::STUrii ||
445 MI.getOpcode() == VE::STQrii ||
446 MI.getOpcode() == VE::STVMrii ||
447 MI.getOpcode() == VE::STVM512rii
449 if (
MI.getOperand(0).isFI() &&
MI.getOperand(1).isImm() &&
450 MI.getOperand(1).getImm() == 0 &&
MI.getOperand(2).isImm() &&
451 MI.getOperand(2).getImm() == 0) {
452 FrameIndex =
MI.getOperand(0).getIndex();
453 return MI.getOperand(3).getReg();
461 Register SrcReg,
bool isKill,
int FI,
467 DL =
I->getDebugLoc();
476 if (RC == &VE::I64RegClass) {
483 }
else if (RC == &VE::I32RegClass) {
490 }
else if (RC == &VE::F32RegClass) {
497 }
else if (VE::F128RegClass.hasSubClassEq(RC)) {
504 }
else if (RC == &VE::VMRegClass) {
511 }
else if (VE::VM512RegClass.hasSubClassEq(RC)) {
530 DL =
I->getDebugLoc();
538 if (RC == &VE::I64RegClass) {
544 }
else if (RC == &VE::I32RegClass) {
550 }
else if (RC == &VE::F32RegClass) {
556 }
else if (VE::F128RegClass.hasSubClassEq(RC)) {
562 }
else if (RC == &VE::VMRegClass) {
568 }
else if (VE::VM512RegClass.hasSubClassEq(RC)) {
584 switch (
DefMI.getOpcode()) {
604 if (!
DefMI.getOperand(3).isImm())
607 ImmVal =
DefMI.getOperand(2).getImm() +
DefMI.getOperand(3).getImm();
640 unsigned NewUseOpcSImm7;
641 unsigned NewUseOpcMImm;
648#define INSTRKIND(NAME) \
650 NewUseOpcSImm7 = NAME##ri; \
651 NewUseOpcMImm = NAME##rm; \
652 InstType = rr2ri_rm; \
654#define NCINSTRKIND(NAME) \
656 NewUseOpcSImm7 = NAME##ir; \
657 NewUseOpcMImm = NAME##rm; \
658 InstType = rr2ir_rm; \
661 switch (
UseMI.getOpcode()) {
703 bool Commute =
false;
713 if (isInt<7>(ImmVal)) {
716 NewUseOpc = NewUseOpcSImm7;
719 NewUseOpc = NewUseOpcMImm;
727 if (!isInt<7>(ImmVal))
729 NewUseOpc = NewUseOpcSImm7;
736 NewUseOpc = NewUseOpcMImm;
744 bool DeleteDef =
MRI->hasOneNonDBGUse(Reg);
749 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
751 DefMI.eraseFromParent();
759 if (GlobalBaseReg != 0)
760 return GlobalBaseReg;
763 GlobalBaseReg = VE::SX15;
772 return GlobalBaseReg;
776 return (reg - VE::VMP0) * 2 + VE::VM0;
791 switch (
MI.getOpcode()) {
804 MI.eraseFromParent();
813 switch (
MI.getNumExplicitOperands()) {
818 MIB.
addReg(
MI.getOperand(1).getReg());
822 MIB.
addImm(
MI.getOperand(1).getImm());
824 MIB.
addReg(
MI.getOperand(2).getReg());
826 MIB.
addReg(
MI.getOperand(3).getReg());
830 MIB.
addImm(
MI.getOperand(1).getImm());
832 MIB.
addReg(
MI.getOperand(2).getReg());
837 MIB.
addReg(
MI.getOperand(4).getReg());
846 static const std::pair<unsigned, std::pair<unsigned, unsigned>> VFMKMap[] = {
847 {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}},
848 {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}},
849 {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}},
850 {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}},
851 {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}},
852 {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}},
855 unsigned Opcode =
MI.getOpcode();
859 if (Found == std::end(VFMKMap))
862 unsigned OpcodeUpper = (*Found).second.first;
863 unsigned OpcodeLower = (*Found).second.second;
873 MI.eraseFromParent();
877 switch (
MI.getOpcode()) {
878 case VE::EXTEND_STACK: {
881 case VE::EXTEND_STACK_GUARD: {
882 MI.eraseFromParent();
885 case VE::GETSTACKTOP: {
914 int64_t Imm =
MI.getOperand(1).getImm();
916 MI.getOpcode() == VE::LVMyir ||
MI.getOpcode() == VE::LVMyir_y;
917 Register Src = IsSrcReg ?
MI.getOperand(2).getReg() : VE::NoRegister;
918 int64_t MImm = IsSrcReg ? 0 :
MI.getOperand(2).getImm();
919 bool KillSrc = IsSrcReg ?
MI.getOperand(2).isKill() :
false;
927 switch (
MI.getOpcode()) {
941 assert(
MI.getOperand(0).getReg() ==
MI.getOperand(3).getReg() &&
942 "LVMyir_y has different register in 3rd operand");
950 assert(
MI.getOperand(0).getReg() ==
MI.getOperand(3).getReg() &&
951 "LVMyim_y has different register in 3rd operand");
959 MI.eraseFromParent();
966 bool KillSrc =
MI.getOperand(1).isKill();
967 int64_t Imm =
MI.getOperand(2).getImm();
982 MI.eraseFromParent();
1025 MF.
insert(It, syscallMBB);
1048 BuildMI(BB, dl,
TII.get(VE::LDrii), VE::SX61)
1055 BuildMI(BB, dl,
TII.get(VE::LEAzii), VE::SX63)
1077 MI.eraseFromParent();
1109 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
static bool isReg(const MCInst &MI, unsigned OpNo)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallVector class.
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
static bool IsIntegerCC(unsigned CC)
static void expandPseudoVFMK(const TargetInstrInfo &TI, MachineInstr &MI)
#define NCINSTRKIND(NAME)
static Register getVM512Lower(Register reg)
static void copyPhysSubRegs(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const MCInstrDesc &MCID, unsigned int NumSubRegs, const unsigned *SubRegIdx, const TargetRegisterInfo *TRI)
static bool IsAliasOfSX(Register Reg)
static Register getVM512Upper(Register reg)
static void expandPseudoLogM(MachineInstr &MI, const MCInstrDesc &MCID)
static void addOperandsForVFMK(MachineInstrBuilder &MIB, MachineInstr &MI, bool Upper)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
LLVM Basic Block Representation.
Describe properties that are true of each instruction in the target description file.
unsigned getOpcode() const
Return the opcode number for this descriptor.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Wrapper class representing physical registers. Should be passed by value.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
uint64_t getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineBasicBlock * getMBB() const
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Target - Wrapper for Target specific information.
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
} Stack Spill & Reload
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Register getGlobalBaseReg(MachineFunction *MF) const
} Optimization
const VERegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
VEInstrInfo(VESubtarget &ST)
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Stack Spill & Reload {.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Branch Analysis & Modification {.
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
} Branch Analysis & Modification
bool expandExtendStackPseudo(MachineInstr &MI) const
bool expandGetStackTopPseudo(MachineInstr &MI) const
void setGlobalBaseReg(Register Reg)
Register getGlobalBaseReg() const
uint64_t getAdjustedFrameSize(uint64_t FrameSize) const
Given a actual stack size as determined by FrameInfo, this function returns adjusted framesize which ...
const VEInstrInfo * getInstrInfo() const override
const VEFrameLowering * getFrameLowering() const override
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
static bool isCondBranchOpcode(int Opc)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isIndirectBranchOpcode(int Opc)
unsigned M1(unsigned Val)
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
static uint64_t val2MImm(uint64_t Val)
val2MImm - Convert an integer immediate value to target MImm immediate.
unsigned getKillRegState(bool B)
static uint64_t mimm2Val(uint64_t Val)
mimm2Val - Convert a target MImm immediate to an integer immediate value.
static bool isUncondBranchOpcode(int Opc)
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
static bool isMImmVal(uint64_t Val)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.