LLVM 20.0.0git
VEInstrInfo.h
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1//===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the VE implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H
14#define LLVM_LIB_TARGET_VE_VEINSTRINFO_H
15
16#include "VERegisterInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "VEGenInstrInfo.inc"
21
22namespace llvm {
23
24class VESubtarget;
25
26/// VEII - This namespace holds all of the Aurora VE target-specific
27/// per-instruction flags. These must match the corresponding definitions in
28/// VEInstrFormats.td.
29namespace VEII {
30enum {
31 // Aurora VE Instruction Flags. These flags describe the characteristics of
32 // the Aurora VE instructions for vector handling.
33
34 /// VE_Vector - This instruction is Vector Instruction.
35 VE_Vector = 0x1,
36
37 /// VE_VLInUse - This instruction has a vector register in its operands.
39
40 /// VE_VLMask/Shift - This is a bitmask that selects the index number where
41 /// an instruction holds vector length informatio (0 to 6, 7 means undef).n
44};
45
46#define HAS_VLINDEX(TSF) ((TSF)&VEII::VE_VLInUse)
47#define GET_VLINDEX(TSF) \
48 (HAS_VLINDEX(TSF) ? (int)(((TSF)&VEII::VE_VLMask) >> VEII::VE_VLShift) : -1)
49} // end namespace VEII
50
52 const VERegisterInfo RI;
53 virtual void anchor();
54
55public:
56 explicit VEInstrInfo(VESubtarget &ST);
57
58 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
59 /// such, whenever a client has an instance of instruction info, it should
60 /// always be able to get register info as well (through this method).
61 ///
62 const VERegisterInfo &getRegisterInfo() const { return RI; }
63
64 /// Branch Analysis & Modification {
68 bool AllowModify = false) const override;
69
71 int *BytesRemoved = nullptr) const override;
72
75 const DebugLoc &DL,
76 int *BytesAdded = nullptr) const override;
77
78 bool
80 /// } Branch Analysis & Modification
81
83 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
84 bool KillSrc) const override;
85
86 /// Stack Spill & Reload {
88 int &FrameIndex) const override;
90 int &FrameIndex) const override;
93 bool isKill, int FrameIndex,
94 const TargetRegisterClass *RC,
96 Register VReg) const override;
97
100 int FrameIndex, const TargetRegisterClass *RC,
101 const TargetRegisterInfo *TRI,
102 Register VReg) const override;
103 /// } Stack Spill & Reload
104
105 /// Optimization {
106
108 MachineRegisterInfo *MRI) const override;
109
110 /// } Optimization
111
113
114 // Lower pseudo instructions after register allocation.
115 bool expandPostRAPseudo(MachineInstr &MI) const override;
116
119};
120
121} // namespace llvm
122
123#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
} Stack Spill & Reload
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Register getGlobalBaseReg(MachineFunction *MF) const
} Optimization
const VERegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: VEInstrInfo.h:62
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Stack Spill & Reload {.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Branch Analysis & Modification {.
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool expandExtendStackPseudo(MachineInstr &MI) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
} Branch Analysis & Modification
bool expandGetStackTopPseudo(MachineInstr &MI) const
@ VE_VLShift
VE_VLMask/Shift - This is a bitmask that selects the index number where an instruction holds vector l...
Definition: VEInstrInfo.h:42
@ VE_VLInUse
VE_VLInUse - This instruction has a vector register in its operands.
Definition: VEInstrInfo.h:38
@ VE_Vector
VE_Vector - This instruction is Vector Instruction.
Definition: VEInstrInfo.h:35
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18