20#include "llvm/IR/IntrinsicsSPIRV.h"
24#define DEBUG_TYPE "spirv-builtins"
28#define GET_BuiltinGroup_DECL
29#include "SPIRVGenTables.inc"
33 InstructionSet::InstructionSet
Set;
39#define GET_DemangledBuiltins_DECL
40#define GET_DemangledBuiltins_IMPL
62 InstructionSet::InstructionSet
Set;
66#define GET_NativeBuiltins_DECL
67#define GET_NativeBuiltins_IMPL
85#define GET_GroupBuiltins_DECL
86#define GET_GroupBuiltins_IMPL
95#define GET_IntelSubgroupsBuiltins_DECL
96#define GET_IntelSubgroupsBuiltins_IMPL
103#define GET_AtomicFloatingBuiltins_DECL
104#define GET_AtomicFloatingBuiltins_IMPL
111#define GET_GroupUniformBuiltins_DECL
112#define GET_GroupUniformBuiltins_IMPL
116 InstructionSet::InstructionSet
Set;
120using namespace BuiltIn;
121#define GET_GetBuiltins_DECL
122#define GET_GetBuiltins_IMPL
126 InstructionSet::InstructionSet
Set;
130#define GET_ImageQueryBuiltins_DECL
131#define GET_ImageQueryBuiltins_IMPL
135 InstructionSet::InstructionSet
Set;
145 InstructionSet::InstructionSet
Set;
152using namespace FPRoundingMode;
153#define GET_ConvertBuiltins_DECL
154#define GET_ConvertBuiltins_IMPL
156using namespace InstructionSet;
157#define GET_VectorLoadStoreBuiltins_DECL
158#define GET_VectorLoadStoreBuiltins_IMPL
160#define GET_CLMemoryScope_DECL
161#define GET_CLSamplerAddressingMode_DECL
162#define GET_CLMemoryFenceFlags_DECL
163#define GET_ExtendedBuiltins_DECL
164#include "SPIRVGenTables.inc"
182static std::unique_ptr<const SPIRV::IncomingCall>
184 SPIRV::InstructionSet::InstructionSet Set,
189 std::string BuiltinName =
195 if (BuiltinName.find(
'<') && BuiltinName.back() ==
'>') {
196 BuiltinName = BuiltinName.substr(0, BuiltinName.find(
'<'));
197 BuiltinName = BuiltinName.substr(BuiltinName.find_last_of(
' ') + 1);
205 BuiltinName = BuiltinName.substr(0, BuiltinName.find(
"_R"));
210 DemangledCall.
slice(DemangledCall.
find(
'(') + 1, DemangledCall.
find(
')'));
211 BuiltinArgs.
split(BuiltinArgumentTypes,
',', -1,
false);
216 if ((Builtin = SPIRV::lookupBuiltin(BuiltinName, Set)))
217 return std::make_unique<SPIRV::IncomingCall>(
218 BuiltinName, Builtin, ReturnRegister, ReturnType,
Arguments);
223 if (BuiltinArgumentTypes.
size() >= 1) {
224 char FirstArgumentType = BuiltinArgumentTypes[0][0];
229 switch (FirstArgumentType) {
232 if (Set == SPIRV::InstructionSet::OpenCL_std)
234 else if (Set == SPIRV::InstructionSet::GLSL_std_450)
242 if (Set == SPIRV::InstructionSet::OpenCL_std)
244 else if (Set == SPIRV::InstructionSet::GLSL_std_450)
251 if (Set == SPIRV::InstructionSet::OpenCL_std ||
252 Set == SPIRV::InstructionSet::GLSL_std_450)
258 if (!Prefix.empty() &&
259 (Builtin = SPIRV::lookupBuiltin(Prefix + BuiltinName, Set)))
260 return std::make_unique<SPIRV::IncomingCall>(
261 BuiltinName, Builtin, ReturnRegister, ReturnType,
Arguments);
268 switch (FirstArgumentType) {
289 if (!Suffix.empty() &&
290 (Builtin = SPIRV::lookupBuiltin(BuiltinName + Suffix, Set)))
291 return std::make_unique<SPIRV::IncomingCall>(
292 BuiltinName, Builtin, ReturnRegister, ReturnType,
Arguments);
307static std::tuple<Register, SPIRVType *>
313 if (ResultType->
getOpcode() == SPIRV::OpTypeVector) {
328 return std::make_tuple(ResultRegister, BoolType);
339 if (ReturnType->getOpcode() == SPIRV::OpTypeVector) {
348 return MIRBuilder.
buildSelect(ReturnRegister, SourceRegister, TrueConst,
359 if (!DestinationReg.isValid()) {
360 DestinationReg =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
367 MIRBuilder.
buildLoad(DestinationReg, PtrRegister, PtrInfo,
Align());
368 return DestinationReg;
382 VariableType, MIRBuilder, SPIRV::StorageClass::Input);
388 SPIRV::StorageClass::Input,
nullptr, isConst,
389 hasLinkageTy, SPIRV::LinkageType::Import, MIRBuilder,
396 return LoadedRegister;
405 SPIRVGlobalRegistry *GR,
406 MachineIRBuilder &MIB,
407 MachineRegisterInfo &
MRI);
410static SPIRV::MemorySemantics::MemorySemantics
413 case std::memory_order::memory_order_relaxed:
414 return SPIRV::MemorySemantics::None;
415 case std::memory_order::memory_order_acquire:
416 return SPIRV::MemorySemantics::Acquire;
417 case std::memory_order::memory_order_release:
418 return SPIRV::MemorySemantics::Release;
419 case std::memory_order::memory_order_acq_rel:
420 return SPIRV::MemorySemantics::AcquireRelease;
421 case std::memory_order::memory_order_seq_cst:
422 return SPIRV::MemorySemantics::SequentiallyConsistent;
430 case SPIRV::CLMemoryScope::memory_scope_work_item:
431 return SPIRV::Scope::Invocation;
432 case SPIRV::CLMemoryScope::memory_scope_work_group:
433 return SPIRV::Scope::Workgroup;
434 case SPIRV::CLMemoryScope::memory_scope_device:
435 return SPIRV::Scope::Device;
436 case SPIRV::CLMemoryScope::memory_scope_all_svm_devices:
437 return SPIRV::Scope::CrossDevice;
438 case SPIRV::CLMemoryScope::memory_scope_sub_group:
439 return SPIRV::Scope::Subgroup;
452 SPIRV::Scope::Scope Scope,
456 if (CLScopeRegister.
isValid()) {
461 if (CLScope ==
static_cast<unsigned>(Scope)) {
462 MRI->setRegClass(CLScopeRegister, &SPIRV::IDRegClass);
463 return CLScopeRegister;
470 Register PtrRegister,
unsigned &Semantics,
473 if (SemanticsRegister.
isValid()) {
475 std::memory_order Order =
481 if (Order == Semantics) {
482 MRI->setRegClass(SemanticsRegister, &SPIRV::IDRegClass);
483 return SemanticsRegister;
494 if (TypeReg.isValid())
496 for (
Register ArgReg : Call->Arguments) {
497 if (!
MRI->getRegClassOrNull(ArgReg))
498 MRI->setRegClass(ArgReg, &SPIRV::IDRegClass);
507 if (Call->isSpirvOp())
510 assert(Call->Arguments.size() == 2 &&
511 "Need 2 arguments for atomic init translation");
515 .
addUse(Call->Arguments[0])
516 .
addUse(Call->Arguments[1]);
525 if (Call->isSpirvOp())
528 Register PtrRegister = Call->Arguments[0];
534 if (Call->Arguments.size() > 1) {
535 ScopeRegister = Call->Arguments[1];
541 if (Call->Arguments.size() > 2) {
543 MemSemanticsReg = Call->Arguments[2];
547 SPIRV::MemorySemantics::SequentiallyConsistent |
553 .
addDef(Call->ReturnRegister)
565 if (Call->isSpirvOp())
570 Register PtrRegister = Call->Arguments[0];
573 SPIRV::MemorySemantics::SequentiallyConsistent |
581 .
addUse(Call->Arguments[1]);
589 if (Call->isSpirvOp())
593 bool IsCmpxchg = Call->Builtin->Name.contains(
"cmpxchg");
596 Register ObjectPtr = Call->Arguments[0];
597 Register ExpectedArg = Call->Arguments[1];
598 Register Desired = Call->Arguments[2];
599 MRI->setRegClass(ObjectPtr, &SPIRV::IDRegClass);
600 MRI->setRegClass(ExpectedArg, &SPIRV::IDRegClass);
601 MRI->setRegClass(Desired, &SPIRV::IDRegClass);
603 LLT DesiredLLT =
MRI->getType(Desired);
606 SPIRV::OpTypePointer);
609 assert(IsCmpxchg ? ExpectedType == SPIRV::OpTypeInt
610 : ExpectedType == SPIRV::OpTypePointer);
615 auto StorageClass =
static_cast<SPIRV::StorageClass::StorageClass
>(
623 ? SPIRV::MemorySemantics::None
624 : SPIRV::MemorySemantics::SequentiallyConsistent | MemSemStorage;
627 ? SPIRV::MemorySemantics::None
628 : SPIRV::MemorySemantics::SequentiallyConsistent | MemSemStorage;
629 if (Call->Arguments.size() >= 4) {
630 assert(Call->Arguments.size() >= 5 &&
631 "Need 5+ args for explicit atomic cmpxchg");
638 if (MemOrdEq == MemSemEqual)
639 MemSemEqualReg = Call->Arguments[3];
640 if (MemOrdNeq == MemSemEqual)
641 MemSemUnequalReg = Call->Arguments[4];
642 MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
643 MRI->setRegClass(Call->Arguments[4], &SPIRV::IDRegClass);
647 if (!MemSemUnequalReg.
isValid())
651 auto Scope = IsCmpxchg ? SPIRV::Scope::Workgroup : SPIRV::Scope::Device;
652 if (Call->Arguments.size() >= 6) {
653 assert(Call->Arguments.size() == 6 &&
654 "Extra args for explicit atomic cmpxchg");
655 auto ClScope =
static_cast<SPIRV::CLMemoryScope
>(
658 if (ClScope ==
static_cast<unsigned>(Scope))
659 ScopeReg = Call->Arguments[5];
660 MRI->setRegClass(Call->Arguments[5], &SPIRV::IDRegClass);
670 Register Tmp = !IsCmpxchg ?
MRI->createGenericVirtualRegister(DesiredLLT)
671 : Call->ReturnRegister;
672 if (!
MRI->getRegClassOrNull(Tmp))
673 MRI->setRegClass(Tmp, &SPIRV::IDRegClass);
697 if (Call->isSpirvOp())
703 Call->Arguments.size() >= 4 ? Call->Arguments[3] :
Register();
705 assert(Call->Arguments.size() <= 4 &&
706 "Too many args for explicit atomic RMW");
707 ScopeRegister =
buildScopeReg(ScopeRegister, SPIRV::Scope::Workgroup,
708 MIRBuilder, GR,
MRI);
710 Register PtrRegister = Call->Arguments[0];
711 unsigned Semantics = SPIRV::MemorySemantics::None;
712 MRI->setRegClass(PtrRegister, &SPIRV::IDRegClass);
714 Call->Arguments.size() >= 3 ? Call->Arguments[2] :
Register();
716 Semantics, MIRBuilder, GR);
717 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
719 .
addDef(Call->ReturnRegister)
724 .
addUse(Call->Arguments[1]);
733 assert(Call->Arguments.size() == 4 &&
734 "Wrong number of atomic floating-type builtin");
738 Register PtrReg = Call->Arguments[0];
739 MRI->setRegClass(PtrReg, &SPIRV::IDRegClass);
741 Register ScopeReg = Call->Arguments[1];
742 MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
744 Register MemSemanticsReg = Call->Arguments[2];
745 MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
747 Register ValueReg = Call->Arguments[3];
748 MRI->setRegClass(ValueReg, &SPIRV::IDRegClass);
751 .
addDef(Call->ReturnRegister)
765 bool IsSet = Opcode == SPIRV::OpAtomicFlagTestAndSet;
767 if (Call->isSpirvOp())
772 Register PtrRegister = Call->Arguments[0];
773 unsigned Semantics = SPIRV::MemorySemantics::SequentiallyConsistent;
775 Call->Arguments.size() >= 2 ? Call->Arguments[1] :
Register();
777 Semantics, MIRBuilder, GR);
779 assert((Opcode != SPIRV::OpAtomicFlagClear ||
780 (Semantics != SPIRV::MemorySemantics::Acquire &&
781 Semantics != SPIRV::MemorySemantics::AcquireRelease)) &&
782 "Invalid memory order argument!");
785 Call->Arguments.size() >= 3 ? Call->Arguments[2] :
Register();
802 if (Call->isSpirvOp())
807 unsigned MemSemantics = SPIRV::MemorySemantics::None;
809 if (MemFlags & SPIRV::CLK_LOCAL_MEM_FENCE)
810 MemSemantics |= SPIRV::MemorySemantics::WorkgroupMemory;
812 if (MemFlags & SPIRV::CLK_GLOBAL_MEM_FENCE)
813 MemSemantics |= SPIRV::MemorySemantics::CrossWorkgroupMemory;
815 if (MemFlags & SPIRV::CLK_IMAGE_MEM_FENCE)
816 MemSemantics |= SPIRV::MemorySemantics::ImageMemory;
818 if (Opcode == SPIRV::OpMemoryBarrier) {
819 std::memory_order MemOrder =
823 MemSemantics |= SPIRV::MemorySemantics::SequentiallyConsistent;
827 if (MemFlags == MemSemantics) {
828 MemSemanticsReg = Call->Arguments[0];
829 MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
834 SPIRV::Scope::Scope Scope = SPIRV::Scope::Workgroup;
835 SPIRV::Scope::Scope MemScope = Scope;
836 if (Call->Arguments.size() >= 2) {
838 ((Opcode != SPIRV::OpMemoryBarrier && Call->Arguments.size() == 2) ||
839 (Opcode == SPIRV::OpMemoryBarrier && Call->Arguments.size() == 3)) &&
840 "Extra args for explicitly scoped barrier");
841 Register ScopeArg = (Opcode == SPIRV::OpMemoryBarrier) ? Call->Arguments[2]
842 : Call->Arguments[1];
843 SPIRV::CLMemoryScope CLScope =
846 if (!(MemFlags & SPIRV::CLK_LOCAL_MEM_FENCE) ||
847 (Opcode == SPIRV::OpMemoryBarrier))
850 if (CLScope ==
static_cast<unsigned>(Scope)) {
851 ScopeReg = Call->Arguments[1];
852 MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
860 if (Opcode != SPIRV::OpMemoryBarrier)
862 MIB.
addUse(MemSemanticsReg);
868 case SPIRV::Dim::DIM_1D:
869 case SPIRV::Dim::DIM_Buffer:
871 case SPIRV::Dim::DIM_2D:
872 case SPIRV::Dim::DIM_Cube:
873 case SPIRV::Dim::DIM_Rect:
875 case SPIRV::Dim::DIM_3D:
888 return arrayed ? numComps + 1 : numComps;
901 SPIRV::lookupExtendedBuiltin(Builtin->
Name, Builtin->
Set)->Number;
906 .
addDef(Call->ReturnRegister)
911 for (
auto Argument : Call->Arguments)
922 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
926 std::tie(CompareRegister, RelationType) =
934 for (
auto Argument : Call->Arguments)
938 return buildSelectInst(MIRBuilder, Call->ReturnRegister, CompareRegister,
939 Call->ReturnType, GR);
947 SPIRV::lookupGroupBuiltin(Builtin->
Name);
951 Register ConstRegister = Call->Arguments[0];
953 (void)ArgInstruction;
955 assert(ArgInstruction->getOpcode() == TargetOpcode::G_CONSTANT &&
956 "Only constant bool value args are supported");
963 Register GroupResultRegister = Call->ReturnRegister;
964 SPIRVType *GroupResultType = Call->ReturnType;
968 const bool HasBoolReturnTy =
974 std::tie(GroupResultRegister, GroupResultType) =
977 auto Scope = Builtin->
Name.
starts_with(
"sub_group") ? SPIRV::Scope::Subgroup
978 : SPIRV::Scope::Workgroup;
983 .
addDef(GroupResultRegister)
989 if (Call->Arguments.size() > 0) {
991 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
992 for (
unsigned i = 1; i < Call->Arguments.size(); i++) {
993 MIB.addUse(Call->Arguments[i]);
994 MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
1000 buildSelectInst(MIRBuilder, Call->ReturnRegister, GroupResultRegister,
1001 Call->ReturnType, GR);
1011 if (!ST->canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) {
1012 std::string DiagMsg = std::string(Builtin->
Name) +
1013 ": the builtin requires the following SPIR-V "
1014 "extension: SPV_INTEL_subgroups";
1018 SPIRV::lookupIntelSubgroupsBuiltin(Builtin->
Name);
1022 if (IntelSubgroups->
IsBlock) {
1025 if (Arg0Type->getOpcode() == SPIRV::OpTypeImage) {
1031 case SPIRV::OpSubgroupBlockReadINTEL:
1032 OpCode = SPIRV::OpSubgroupImageBlockReadINTEL;
1034 case SPIRV::OpSubgroupBlockWriteINTEL:
1035 OpCode = SPIRV::OpSubgroupImageBlockWriteINTEL;
1056 .
addDef(Call->ReturnRegister)
1058 for (
size_t i = 0; i < Call->Arguments.size(); ++i) {
1059 MIB.
addUse(Call->Arguments[i]);
1060 MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
1072 if (!ST->canUseExtension(
1073 SPIRV::Extension::SPV_KHR_uniform_group_instructions)) {
1074 std::string DiagMsg = std::string(Builtin->
Name) +
1075 ": the builtin requires the following SPIR-V "
1076 "extension: SPV_KHR_uniform_group_instructions";
1080 SPIRV::lookupGroupUniformBuiltin(Builtin->
Name);
1083 Register GroupResultReg = Call->ReturnRegister;
1084 MRI->setRegClass(GroupResultReg, &SPIRV::IDRegClass);
1087 Register ScopeReg = Call->Arguments[0];
1088 MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
1091 Register ConstGroupOpReg = Call->Arguments[1];
1093 if (!Const || Const->getOpcode() != TargetOpcode::G_CONSTANT)
1095 "expect a constant group operation for a uniform group instruction",
1098 if (!ConstOperand.
isCImm())
1104 Register ValueReg = Call->Arguments[2];
1105 MRI->setRegClass(ValueReg, &SPIRV::IDRegClass);
1112 MIB.addUse(ValueReg);
1146 SPIRV::BuiltIn::BuiltIn BuiltinValue,
1148 Register IndexRegister = Call->Arguments[0];
1149 const unsigned ResultWidth = Call->ReturnType->getOperand(1).getImm();
1157 Register ToTruncate = Call->ReturnRegister;
1160 bool IsConstantIndex =
1161 IndexInstruction->getOpcode() == TargetOpcode::G_CONSTANT;
1166 Register DefaultReg = Call->ReturnRegister;
1167 if (PointerSize != ResultWidth) {
1168 DefaultReg =
MRI->createGenericVirtualRegister(
LLT::scalar(PointerSize));
1169 MRI->setRegClass(DefaultReg, &SPIRV::IDRegClass);
1171 MIRBuilder.
getMF());
1172 ToTruncate = DefaultReg;
1176 MIRBuilder.
buildCopy(DefaultReg, NewRegister);
1184 Register Extracted = Call->ReturnRegister;
1185 if (!IsConstantIndex || PointerSize != ResultWidth) {
1186 Extracted =
MRI->createGenericVirtualRegister(
LLT::scalar(PointerSize));
1187 MRI->setRegClass(Extracted, &SPIRV::IDRegClass);
1194 ExtractInst.
addUse(LoadedVector).
addUse(IndexRegister);
1197 if (!IsConstantIndex) {
1206 MRI->setRegClass(CompareRegister, &SPIRV::IDRegClass);
1219 Register SelectionResult = Call->ReturnRegister;
1220 if (PointerSize != ResultWidth) {
1223 MRI->setRegClass(SelectionResult, &SPIRV::IDRegClass);
1225 MIRBuilder.
getMF());
1228 MIRBuilder.
buildSelect(SelectionResult, CompareRegister, Extracted,
1230 ToTruncate = SelectionResult;
1232 ToTruncate = Extracted;
1236 if (PointerSize != ResultWidth)
1246 SPIRV::BuiltIn::BuiltIn
Value =
1247 SPIRV::lookupGetBuiltin(Builtin->
Name, Builtin->
Set)->
Value;
1249 if (
Value == SPIRV::BuiltIn::GlobalInvocationId)
1255 if (Call->ReturnType->getOpcode() == SPIRV::OpTypeVector)
1262 LLType, Call->ReturnRegister);
1271 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1274 case SPIRV::OpStore:
1276 case SPIRV::OpAtomicLoad:
1278 case SPIRV::OpAtomicStore:
1280 case SPIRV::OpAtomicCompareExchange:
1281 case SPIRV::OpAtomicCompareExchangeWeak:
1284 case SPIRV::OpAtomicIAdd:
1285 case SPIRV::OpAtomicISub:
1286 case SPIRV::OpAtomicOr:
1287 case SPIRV::OpAtomicXor:
1288 case SPIRV::OpAtomicAnd:
1289 case SPIRV::OpAtomicExchange:
1291 case SPIRV::OpMemoryBarrier:
1293 case SPIRV::OpAtomicFlagTestAndSet:
1294 case SPIRV::OpAtomicFlagClear:
1306 unsigned Opcode = SPIRV::lookupAtomicFloatingBuiltin(Builtin->
Name)->Opcode;
1309 case SPIRV::OpAtomicFAddEXT:
1310 case SPIRV::OpAtomicFMinEXT:
1311 case SPIRV::OpAtomicFMaxEXT:
1324 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1333 bool IsVec = Opcode == SPIRV::OpTypeVector;
1335 MIRBuilder.
buildInstr(IsVec ? SPIRV::OpDot : SPIRV::OpFMulS)
1336 .
addDef(Call->ReturnRegister)
1338 .
addUse(Call->Arguments[0])
1339 .
addUse(Call->Arguments[1]);
1347 SPIRV::BuiltIn::BuiltIn
Value =
1348 SPIRV::lookupGetBuiltin(Builtin->
Name, Builtin->
Set)->
Value;
1351 assert(Call->ReturnType->getOpcode() == SPIRV::OpTypeInt);
1355 MIRBuilder, Call->ReturnType, GR,
Value, LLType, Call->ReturnRegister,
1363 SPIRV::BuiltIn::BuiltIn
Value =
1364 SPIRV::lookupGetBuiltin(Call->Builtin->Name, Call->Builtin->Set)->
Value;
1365 uint64_t IsDefault = (
Value == SPIRV::BuiltIn::GlobalSize ||
1366 Value == SPIRV::BuiltIn::WorkgroupSize ||
1367 Value == SPIRV::BuiltIn::EnqueuedWorkgroupSize);
1377 SPIRV::lookupImageQueryBuiltin(Builtin->
Name, Builtin->
Set)->Component;
1382 unsigned NumExpectedRetComponents =
RetTy->getOpcode() == SPIRV::OpTypeVector
1383 ?
RetTy->getOperand(2).getImm()
1388 Register QueryResult = Call->ReturnRegister;
1389 SPIRVType *QueryResultType = Call->ReturnType;
1390 if (NumExpectedRetComponents != NumActualRetComponents) {
1396 IntTy, NumActualRetComponents, MIRBuilder);
1401 IsDimBuf ? SPIRV::OpImageQuerySize : SPIRV::OpImageQuerySizeLod;
1406 .
addUse(Call->Arguments[0]);
1409 if (NumExpectedRetComponents == NumActualRetComponents)
1411 if (NumExpectedRetComponents == 1) {
1413 unsigned ExtractedComposite =
1414 Component == 3 ? NumActualRetComponents - 1 : Component;
1415 assert(ExtractedComposite < NumActualRetComponents &&
1416 "Invalid composite index!");
1417 MIRBuilder.
buildInstr(SPIRV::OpCompositeExtract)
1418 .
addDef(Call->ReturnRegister)
1421 .
addImm(ExtractedComposite);
1424 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpVectorShuffle)
1425 .
addDef(Call->ReturnRegister)
1429 for (
unsigned i = 0; i < NumExpectedRetComponents; ++i)
1430 MIB.
addImm(i < NumActualRetComponents ? i : 0xffffffff);
1438 assert(Call->ReturnType->getOpcode() == SPIRV::OpTypeInt &&
1439 "Image samples query result must be of int type!");
1444 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1446 Register Image = Call->Arguments[0];
1448 SPIRV::Dim::Dim ImageDimensionality =
static_cast<SPIRV::Dim::Dim
>(
1450 (void)ImageDimensionality;
1453 case SPIRV::OpImageQuerySamples:
1454 assert(ImageDimensionality == SPIRV::Dim::DIM_2D &&
1455 "Image must be of 2D dimensionality");
1457 case SPIRV::OpImageQueryLevels:
1458 assert((ImageDimensionality == SPIRV::Dim::DIM_1D ||
1459 ImageDimensionality == SPIRV::Dim::DIM_2D ||
1460 ImageDimensionality == SPIRV::Dim::DIM_3D ||
1461 ImageDimensionality == SPIRV::Dim::DIM_Cube) &&
1462 "Image must be of 1D/2D/3D/Cube dimensionality");
1467 .
addDef(Call->ReturnRegister)
1474static SPIRV::SamplerAddressingMode::SamplerAddressingMode
1476 switch (Bitmask & SPIRV::CLK_ADDRESS_MODE_MASK) {
1477 case SPIRV::CLK_ADDRESS_CLAMP:
1478 return SPIRV::SamplerAddressingMode::Clamp;
1479 case SPIRV::CLK_ADDRESS_CLAMP_TO_EDGE:
1480 return SPIRV::SamplerAddressingMode::ClampToEdge;
1481 case SPIRV::CLK_ADDRESS_REPEAT:
1482 return SPIRV::SamplerAddressingMode::Repeat;
1483 case SPIRV::CLK_ADDRESS_MIRRORED_REPEAT:
1484 return SPIRV::SamplerAddressingMode::RepeatMirrored;
1485 case SPIRV::CLK_ADDRESS_NONE:
1486 return SPIRV::SamplerAddressingMode::None;
1493 return (Bitmask & SPIRV::CLK_NORMALIZED_COORDS_TRUE) ? 1 : 0;
1496static SPIRV::SamplerFilterMode::SamplerFilterMode
1498 if (Bitmask & SPIRV::CLK_FILTER_LINEAR)
1499 return SPIRV::SamplerFilterMode::Linear;
1500 if (Bitmask & SPIRV::CLK_FILTER_NEAREST)
1501 return SPIRV::SamplerFilterMode::Nearest;
1502 return SPIRV::SamplerFilterMode::Nearest;
1509 Register Image = Call->Arguments[0];
1511 MRI->setRegClass(Image, &SPIRV::IDRegClass);
1512 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1515 if (HasOclSampler || HasMsaa)
1516 MRI->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
1517 if (HasOclSampler) {
1518 Register Sampler = Call->Arguments[1];
1532 Register SampledImage =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1543 bool NeedsExtraction =
false;
1544 if (TempType->
getOpcode() != SPIRV::OpTypeVector) {
1547 NeedsExtraction =
true;
1550 Register TempRegister =
MRI->createGenericVirtualRegister(LLType);
1551 MRI->setRegClass(TempRegister, &SPIRV::IDRegClass);
1554 MIRBuilder.
buildInstr(SPIRV::OpImageSampleExplicitLod)
1555 .
addDef(NeedsExtraction ? TempRegister : Call->ReturnRegister)
1558 .
addUse(Call->Arguments[2])
1559 .
addImm(SPIRV::ImageOperand::Lod)
1562 if (NeedsExtraction)
1563 MIRBuilder.
buildInstr(SPIRV::OpCompositeExtract)
1564 .
addDef(Call->ReturnRegister)
1568 }
else if (HasMsaa) {
1570 .
addDef(Call->ReturnRegister)
1573 .
addUse(Call->Arguments[1])
1574 .
addImm(SPIRV::ImageOperand::Sample)
1575 .
addUse(Call->Arguments[2]);
1578 .
addDef(Call->ReturnRegister)
1581 .
addUse(Call->Arguments[1]);
1593 .
addUse(Call->Arguments[0])
1594 .
addUse(Call->Arguments[1])
1595 .
addUse(Call->Arguments[2]);
1604 if (Call->Builtin->Name.contains_insensitive(
1605 "__translate_sampler_initializer")) {
1612 return Sampler.isValid();
1613 }
else if (Call->Builtin->Name.contains_insensitive(
"__spirv_SampledImage")) {
1615 Register Image = Call->Arguments[0];
1620 Call->ReturnRegister.isValid()
1621 ? Call->ReturnRegister
1622 :
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1627 .
addUse(Call->Arguments[1]);
1629 }
else if (Call->Builtin->Name.contains_insensitive(
1630 "__spirv_ImageSampleExplicitLod")) {
1632 std::string ReturnType = DemangledCall.
str();
1633 if (DemangledCall.
contains(
"_R")) {
1634 ReturnType = ReturnType.substr(ReturnType.find(
"_R") + 2);
1635 ReturnType = ReturnType.substr(0, ReturnType.find(
'('));
1642 std::string DiagMsg =
1643 "Unable to recognize SPIRV type name: " + ReturnType;
1646 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1647 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1648 MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
1650 MIRBuilder.
buildInstr(SPIRV::OpImageSampleExplicitLod)
1651 .
addDef(Call->ReturnRegister)
1653 .
addUse(Call->Arguments[0])
1654 .
addUse(Call->Arguments[1])
1655 .
addImm(SPIRV::ImageOperand::Lod)
1656 .
addUse(Call->Arguments[3]);
1664 MIRBuilder.
buildSelect(Call->ReturnRegister, Call->Arguments[0],
1665 Call->Arguments[1], Call->Arguments[2]);
1675 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1679 case SPIRV::OpSpecConstant: {
1683 buildOpDecorate(Call->ReturnRegister, MIRBuilder, SPIRV::Decoration::SpecId,
1686 Register ConstRegister = Call->Arguments[1];
1689 (Const->getOpcode() == TargetOpcode::G_CONSTANT ||
1690 Const->getOpcode() == TargetOpcode::G_FCONSTANT) &&
1691 "Argument should be either an int or floating-point constant");
1694 if (Call->ReturnType->getOpcode() == SPIRV::OpTypeBool) {
1695 assert(ConstOperand.
isCImm() &&
"Int constant operand is expected");
1697 ? SPIRV::OpSpecConstantTrue
1698 : SPIRV::OpSpecConstantFalse;
1701 .
addDef(Call->ReturnRegister)
1704 if (Call->ReturnType->getOpcode() != SPIRV::OpTypeBool) {
1705 if (Const->getOpcode() == TargetOpcode::G_CONSTANT)
1712 case SPIRV::OpSpecConstantComposite: {
1714 .
addDef(Call->ReturnRegister)
1716 for (
unsigned i = 0; i < Call->Arguments.size(); i++)
1717 MIB.
addUse(Call->Arguments[i]);
1729 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1736 Register TmpReg =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1740 unsigned NumArgs = Call->Arguments.size();
1742 Register GlobalWorkSize = Call->Arguments[NumArgs < 4 ? 1 : 2];
1743 MRI->setRegClass(GlobalWorkSize, &SPIRV::IDRegClass);
1745 NumArgs == 2 ?
Register(0) : Call->Arguments[NumArgs < 4 ? 2 : 3];
1747 MRI->setRegClass(LocalWorkSize, &SPIRV::IDRegClass);
1748 Register GlobalWorkOffset = NumArgs <= 3 ?
Register(0) : Call->Arguments[1];
1749 if (GlobalWorkOffset.
isValid())
1750 MRI->setRegClass(GlobalWorkOffset, &SPIRV::IDRegClass);
1754 if (SpvTy->
getOpcode() == SPIRV::OpTypePointer) {
1759 if (!
MRI->getRegClassOrNull(GWSPtr))
1760 MRI->setRegClass(GWSPtr, &SPIRV::IDRegClass);
1762 unsigned Size = Call->Builtin->Name.equals(
"ndrange_3D") ? 3 : 2;
1767 GlobalWorkSize =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1778 LocalWorkSize = Const;
1779 if (!GlobalWorkOffset.
isValid())
1780 GlobalWorkOffset = Const;
1788 .
addUse(GlobalWorkOffset);
1790 .
addUse(Call->Arguments[0])
1802 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST &&
1803 MI->getOperand(1).isReg());
1804 Register BitcastReg =
MI->getOperand(1).getReg();
1832 Register ValueReg =
MI->getOperand(0).getReg();
1837 assert(Ty &&
"Type is expected");
1849 if (
MI->getOpcode() == TargetOpcode::G_GLOBAL_VALUE)
1850 return MI->getOperand(1).getGlobal()->getType();
1852 "Blocks in OpenCL C must be traceable to allocation site");
1877 bool IsSpirvOp = Call->isSpirvOp();
1878 bool HasEvents = Call->Builtin->Name.contains(
"events") || IsSpirvOp;
1885 if (Call->Builtin->Name.find(
"_varargs") !=
StringRef::npos || IsSpirvOp) {
1886 const unsigned LocalSizeArrayIdx = HasEvents ? 9 : 6;
1887 Register GepReg = Call->Arguments[LocalSizeArrayIdx];
1894 assert(LocalSizeTy &&
"Local size type is expected");
1896 cast<ArrayType>(LocalSizeTy)->getNumElements();
1900 Int32Ty, MIRBuilder, SPIRV::StorageClass::Function);
1901 for (
unsigned I = 0;
I < LocalSizeNum; ++
I) {
1903 MRI->setType(
Reg, LLType);
1917 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpEnqueueKernel)
1918 .
addDef(Call->ReturnRegister)
1922 const unsigned BlockFIdx = HasEvents ? 6 : 3;
1923 for (
unsigned i = 0; i < BlockFIdx; i++)
1924 MIB.addUse(Call->Arguments[i]);
1931 MIB.addUse(NullPtr);
1932 MIB.addUse(NullPtr);
1940 Register BlockLiteralReg = Call->Arguments[BlockFIdx + 1];
1942 MIB.addUse(BlockLiteralReg);
1952 for (
unsigned i = 0; i < LocalSizes.
size(); i++)
1953 MIB.addUse(LocalSizes[i]);
1963 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1966 case SPIRV::OpRetainEvent:
1967 case SPIRV::OpReleaseEvent:
1970 case SPIRV::OpCreateUserEvent:
1971 case SPIRV::OpGetDefaultQueue:
1973 .
addDef(Call->ReturnRegister)
1975 case SPIRV::OpIsValidEvent:
1978 .
addDef(Call->ReturnRegister)
1980 .
addUse(Call->Arguments[0]);
1981 case SPIRV::OpSetUserEventStatus:
1985 .
addUse(Call->Arguments[0])
1986 .
addUse(Call->Arguments[1]);
1987 case SPIRV::OpCaptureEventProfilingInfo:
1992 .
addUse(Call->Arguments[0])
1993 .
addUse(Call->Arguments[1])
1994 .
addUse(Call->Arguments[2]);
1995 case SPIRV::OpBuildNDRange:
1997 case SPIRV::OpEnqueueKernel:
2010 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
2014 case SPIRV::OpGroupAsyncCopy:
2016 .
addDef(Call->ReturnRegister)
2019 .
addUse(Call->Arguments[0])
2020 .
addUse(Call->Arguments[1])
2021 .
addUse(Call->Arguments[2])
2023 .
addUse(Call->Arguments[3]);
2024 case SPIRV::OpGroupWaitEvents:
2027 .
addUse(Call->Arguments[0])
2028 .
addUse(Call->Arguments[1]);
2040 SPIRV::lookupConvertBuiltin(Call->Builtin->Name, Call->Builtin->Set);
2044 SPIRV::Decoration::SaturatedConversion, {});
2047 SPIRV::Decoration::FPRoundingMode,
2048 {(unsigned)Builtin->RoundingMode});
2050 std::string NeedExtMsg;
2051 bool IsRightComponentsNumber =
true;
2052 unsigned Opcode = SPIRV::OpNop;
2059 : SPIRV::OpSatConvertSToU;
2062 : SPIRV::OpSConvert;
2064 SPIRV::OpTypeFloat)) {
2069 if (!ST->canUseExtension(
2070 SPIRV::Extension::SPV_INTEL_bfloat16_conversion))
2071 NeedExtMsg =
"SPV_INTEL_bfloat16_conversion";
2072 IsRightComponentsNumber =
2075 Opcode = SPIRV::OpConvertBF16ToFINTEL;
2077 bool IsSourceSigned =
2079 Opcode = IsSourceSigned ? SPIRV::OpConvertSToF : SPIRV::OpConvertUToF;
2083 SPIRV::OpTypeFloat)) {
2090 if (!ST->canUseExtension(
2091 SPIRV::Extension::SPV_INTEL_bfloat16_conversion))
2092 NeedExtMsg =
"SPV_INTEL_bfloat16_conversion";
2093 IsRightComponentsNumber =
2096 Opcode = SPIRV::OpConvertFToBF16INTEL;
2099 : SPIRV::OpConvertFToU;
2102 SPIRV::OpTypeFloat)) {
2104 Opcode = SPIRV::OpFConvert;
2108 if (!NeedExtMsg.empty()) {
2109 std::string DiagMsg = std::string(Builtin->
Name) +
2110 ": the builtin requires the following SPIR-V "
2115 if (!IsRightComponentsNumber) {
2116 std::string DiagMsg =
2117 std::string(Builtin->
Name) +
2118 ": result and argument must have the same number of components";
2121 assert(Opcode != SPIRV::OpNop &&
2122 "Conversion between the types not implemented!");
2125 .
addDef(Call->ReturnRegister)
2127 .
addUse(Call->Arguments[0]);
2136 SPIRV::lookupVectorLoadStoreBuiltin(Call->Builtin->Name,
2137 Call->Builtin->Set);
2141 .
addDef(Call->ReturnRegister)
2143 .
addImm(
static_cast<uint32_t>(SPIRV::InstructionSet::OpenCL_std))
2145 for (
auto Argument : Call->Arguments)
2163 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
2164 bool IsLoad = Opcode == SPIRV::OpLoad;
2168 MIB.
addDef(Call->ReturnRegister);
2172 MIB.
addUse(Call->Arguments[0]);
2174 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2177 MIB.addUse(Call->Arguments[1]);
2178 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
2181 unsigned NumArgs = Call->Arguments.size();
2182 if ((IsLoad && NumArgs >= 2) || NumArgs >= 3) {
2184 MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::IDRegClass);
2186 if ((IsLoad && NumArgs >= 3) || NumArgs >= 4) {
2188 MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::IDRegClass);
2197 SPIRV::InstructionSet::InstructionSet Set,
2202 LLVM_DEBUG(
dbgs() <<
"Lowering builtin call: " << DemangledCall <<
"\n");
2207 if (OrigRetTy && !OrigRetTy->
isVoidTy()) {
2211 }
else if (OrigRetTy && OrigRetTy->
isVoidTy()) {
2218 std::unique_ptr<const IncomingCall> Call =
2219 lookupBuiltin(DemangledCall, Set, ReturnRegister, ReturnType, Args);
2223 return std::nullopt;
2227 assert(Args.size() >= Call->Builtin->MinNumArgs &&
2228 "Too few arguments to generate the builtin");
2229 if (Call->Builtin->MaxNumArgs && Args.size() > Call->Builtin->MaxNumArgs)
2230 LLVM_DEBUG(
dbgs() <<
"More arguments provided than required!\n");
2233 switch (Call->Builtin->Group) {
2234 case SPIRV::Extended:
2236 case SPIRV::Relational:
2240 case SPIRV::Variable:
2244 case SPIRV::AtomicFloating:
2246 case SPIRV::Barrier:
2252 case SPIRV::GetQuery:
2254 case SPIRV::ImageSizeQuery:
2256 case SPIRV::ImageMiscQuery:
2258 case SPIRV::ReadImage:
2260 case SPIRV::WriteImage:
2262 case SPIRV::SampleImage:
2266 case SPIRV::SpecConstant:
2268 case SPIRV::Enqueue:
2270 case SPIRV::AsyncCopy:
2272 case SPIRV::Convert:
2274 case SPIRV::VectorLoadStore:
2276 case SPIRV::LoadStore:
2278 case SPIRV::IntelSubgroups:
2280 case SPIRV::GroupUniform:
2290 DemangledCall.
slice(DemangledCall.
find(
'(') + 1, DemangledCall.
find(
')'));
2291 BuiltinArgs.
split(BuiltinArgsTypeStrs,
',', -1,
false);
2292 if (ArgIdx >= BuiltinArgsTypeStrs.
size())
2294 StringRef TypeStr = BuiltinArgsTypeStrs[ArgIdx].trim();
2301 assert(IsOCLBuiltinType &&
"Invalid OpenCL builtin prefix");
2318 unsigned VecElts = 0;
2332 TypeStr = TypeStr.
substr(0, TypeStr.
find(
']'));
2346#define GET_BuiltinTypes_DECL
2347#define GET_BuiltinTypes_IMPL
2354#define GET_OpenCLTypes_DECL
2355#define GET_OpenCLTypes_IMPL
2357#include "SPIRVGenTables.inc"
2365 if (
Name.starts_with(
"void"))
2367 else if (
Name.starts_with(
"int") ||
Name.starts_with(
"uint"))
2369 else if (
Name.starts_with(
"float"))
2371 else if (
Name.starts_with(
"half"))
2384 unsigned Opcode = TypeRecord->
Opcode;
2399 "Invalid number of parameters for SPIR-V pipe builtin!");
2402 SPIRV::AccessQualifier::AccessQualifier(
2408 const SPIRV::AccessQualifier::AccessQualifier Qualifier,
2411 "SPIR-V image builtin type must have sampled type parameter!");
2415 "Invalid number of parameters for SPIR-V image builtin!");
2418 MIRBuilder, SampledType,
2423 Qualifier == SPIRV::AccessQualifier::WriteOnly
2424 ? SPIRV::AccessQualifier::WriteOnly
2425 : SPIRV::AccessQualifier::AccessQualifier(
2433 OpaqueType, SPIRV::AccessQualifier::ReadOnly, MIRBuilder, GR);
2441 StringRef NameWithParameters = TypeName;
2448 SPIRV::lookupOpenCLType(NameWithParameters);
2451 NameWithParameters);
2459 "Unknown builtin opaque type!");
2463 if (!NameWithParameters.
contains(
'_'))
2467 unsigned BaseNameLength = NameWithParameters.
find(
'_') - 1;
2468 SplitString(NameWithParameters.
substr(BaseNameLength + 1), Parameters,
"_");
2471 bool HasTypeParameter = !
isDigit(Parameters[0][0]);
2472 if (HasTypeParameter)
2475 for (
unsigned i = HasTypeParameter ? 1 : 0; i < Parameters.size(); i++) {
2476 unsigned IntParameter = 0;
2477 bool ValidLiteral = !Parameters[i].getAsInteger(10, IntParameter);
2480 "Invalid format of SPIR-V builtin parameter literal!");
2484 NameWithParameters.
substr(0, BaseNameLength),
2485 TypeParameters, IntParameters);
2489 SPIRV::AccessQualifier::AccessQualifier AccessQual,
2520 switch (TypeRecord->
Opcode) {
2521 case SPIRV::OpTypeImage:
2524 case SPIRV::OpTypePipe:
2527 case SPIRV::OpTypeDeviceEvent:
2530 case SPIRV::OpTypeSampler:
2533 case SPIRV::OpTypeSampledImage:
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
AMDGPU Lower Kernel Arguments
static bool isDigit(const char C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
BaseType
A given derived pointer can have multiple base pointers through phi/selects.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
APInt bitcastToAPInt() const
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
uint64_t getZExtValue() const
Get zero extended value.
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
static ArrayType * get(Type *ElementType, uint64_t NumElements)
This static method is the primary way to construct an ArrayType.
@ ICMP_ULT
unsigned less than
const APFloat & getValueAPF() const
const APInt & getValue() const
Return the constant as an APInt value reference.
A parsed version of the target data layout string in and methods for querying it.
Tagged union holding either a T or a Error.
Class to represent fixed width SIMD vectors.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
This is an important class for using LLVM in a threaded context.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
LLVMContext & getContext() const
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
const DataLayout & getDataLayout() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MDNode * getMetadata() const
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
SPIRVType * getOrCreateOpTypePipe(MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccQual)
SPIRVType * getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const
SPIRVType * getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder)
Register getOrCreateConsIntVector(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR=true)
const Type * getTypeForSPIRVType(const SPIRVType *Ty) const
Register buildConstantSampler(Register Res, unsigned AddrMode, unsigned Param, unsigned FilerMode, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
unsigned getScalarOrVectorComponentCount(Register VReg) const
SPIRVType * getOrCreateOpTypeImage(MachineIRBuilder &MIRBuilder, SPIRVType *SampledType, SPIRV::Dim::Dim Dim, uint32_t Depth, uint32_t Arrayed, uint32_t Multisampled, uint32_t Sampled, SPIRV::ImageFormat::ImageFormat ImageFormat, SPIRV::AccessQualifier::AccessQualifier AccQual)
unsigned getPointerSize() const
SPIRVType * getOrCreateOpTypeByOpcode(const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode)
Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr)
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
bool isScalarOfType(Register VReg, unsigned TypeOpcode) const
Register buildGlobalVariable(Register Reg, SPIRVType *BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage, const MachineInstr *Init, bool IsConst, bool HasLinkageTy, SPIRV::LinkageType::LinkageType LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)
SPIRVType * getOrCreateOpTypeSampledImage(SPIRVType *ImageType, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVTypeByName(StringRef TypeStr, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SC=SPIRV::StorageClass::Function, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite)
SPIRVType * assignTypeToVReg(const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
SPIRVType * getOrCreateOpTypeDeviceEvent(MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVPointerType(SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SClass=SPIRV::StorageClass::Function)
SPIRVType * getOrCreateSPIRVVectorType(SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)
Register getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)
SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const
SPIRVType * getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder)
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr, bool EmitIR=true)
Register getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
unsigned getScalarOrVectorBitWidth(const SPIRVType *Type) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
bool consume_back(StringRef Suffix)
Returns true if this StringRef has the given suffix and removes that suffix.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
bool contains_insensitive(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
bool contains(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
bool consume_front(StringRef Prefix)
Returns true if this StringRef has the given prefix and removes that prefix.
size_t find_first_of(char C, size_t From=0) const
Find the first character in the string that is C, or npos if not found.
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
static constexpr size_t npos
Class to represent struct types.
static StructType * getTypeByName(LLVMContext &C, StringRef Name)
Return the type with the specified name, or null if there is none by that name.
static StructType * create(LLVMContext &Context, StringRef Name)
This creates an identified struct.
Class to represent target extensions types, which are generally unintrospectable from target-independ...
unsigned getNumIntParameters() const
static TargetExtType * get(LLVMContext &Context, StringRef Name, ArrayRef< Type * > Types=std::nullopt, ArrayRef< unsigned > Ints=std::nullopt)
Return a target extension type having the specified name and optional type and integer parameters.
Type * getTypeParameter(unsigned i) const
unsigned getNumTypeParameters() const
unsigned getIntParameter(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getHalfTy(LLVMContext &C)
StringRef getStructName() const
static Type * getVoidTy(LLVMContext &C)
static IntegerType * getInt8Ty(LLVMContext &C)
static IntegerType * getInt32Ty(LLVMContext &C)
static Type * getFloatTy(LLVMContext &C)
bool isVoidTy() const
Return true if this is 'void'.
LLVM Value Representation.
Value(Type *Ty, unsigned scid)
static VectorType * get(Type *ElementType, ElementCount EC)
This static method is the primary way to construct an VectorType.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
LLVMTypeRef LLVMVectorType(LLVMTypeRef ElementType, unsigned ElementCount)
Create a vector type that contains a defined type and has a specific number of elements.
Type * parseBuiltinCallArgumentBaseType(const StringRef DemangledCall, unsigned ArgIdx, LLVMContext &Ctx)
Parses the provided ArgIdx argument base type in the DemangledCall skeleton.
TargetExtType * parseBuiltinTypeNameToTargetExtType(std::string TypeName, LLVMContext &Context)
Translates a string representing a SPIR-V or OpenCL builtin type to a TargetExtType that can be furth...
std::optional< bool > lowerBuiltin(const StringRef DemangledCall, SPIRV::InstructionSet::InstructionSet Set, MachineIRBuilder &MIRBuilder, const Register OrigRet, const Type *OrigRetTy, const SmallVectorImpl< Register > &Args, SPIRVGlobalRegistry *GR)
SPIRVType * lowerBuiltinType(const Type *OpaqueType, SPIRV::AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
This is an optimization pass for GlobalISel generic memory operations.
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
static bool generateGetQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Register buildConstantIntReg(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, unsigned BitWidth=32)
static bool buildAtomicFlagInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building atomic flag instructions (e.g.
static Register buildBuiltinVariableLoad(MachineIRBuilder &MIRBuilder, SPIRVType *VariableType, SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, LLT LLType, Register Reg=Register(0), bool isConst=true, bool hasLinkageTy=true)
Helper function for building a load instruction for loading a builtin global variable of BuiltinValue...
static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRV::SamplerFilterMode::SamplerFilterMode getSamplerFilterModeFromBitmask(unsigned Bitmask)
static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic store instruction.
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
static const Type * getBlockStructType(Register ParamReg, MachineRegisterInfo *MRI)
static bool generateGroupInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static unsigned getNumComponentsForDim(SPIRV::Dim::Dim dim)
Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, MachineRegisterInfo &MRI)
Helper external function for inserting ASSIGN_TYPE instuction between Reg and its definition,...
static Register buildScopeReg(Register CLScopeRegister, SPIRV::Scope::Scope Scope, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI)
static std::tuple< Register, SPIRVType * > buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType, SPIRVGlobalRegistry *GR)
Helper function building either a resulting scalar or vector bool register depending on the expected ...
static unsigned getNumSizeComponents(SPIRVType *imgType)
Helper function for obtaining the number of size components.
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
static SPIRVType * getSampledImageType(const TargetExtType *OpaqueType, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
static bool generateDotOrFMulInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateSampleImageInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateBarrierInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateWaveInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getImageType(const TargetExtType *ExtensionType, const SPIRV::AccessQualifier::AccessQualifier Qualifier, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building barriers, i.e., memory/control ordering operations.
static bool generateAsyncCopy(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRV::Scope::Scope getSPIRVScope(SPIRV::CLMemoryScope ClScope)
static SPIRVType * getSamplerType(MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, LLT LowLevelType, Register DestinationReg=Register(0))
Helper function for building a load instruction loading into the DestinationReg.
static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
static bool buildSelectInst(MachineIRBuilder &MIRBuilder, Register ReturnRegister, Register SourceRegister, const SPIRVType *ReturnType, SPIRVGlobalRegistry *GR)
Helper function for building either a vector or scalar select instruction depending on the expected R...
static const Type * getMachineInstrType(MachineInstr *MI)
static SPIRV::SamplerAddressingMode::SamplerAddressingMode getSamplerAddressingModeFromBitmask(unsigned Bitmask)
static bool generateAtomicInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateConvertInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Register buildMemSemanticsReg(Register SemanticsRegister, Register PtrRegister, unsigned &Semantics, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static unsigned getConstFromIntrinsic(Register Reg, MachineRegisterInfo *MRI)
static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateSelectInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder)
static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic load instruction.
static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateSpecConstantInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getOrCreateSPIRVDeviceEventPointer(MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Type * parseBasicTypeName(StringRef &TypeName, LLVMContext &Ctx)
static bool generateVectorLoadStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, uint64_t DefaultValue)
static bool buildOpFromWrapper(MachineIRBuilder &MIRBuilder, unsigned Opcode, const SPIRV::IncomingCall *Call, Register TypeReg=Register(0))
static std::unique_ptr< const SPIRV::IncomingCall > lookupBuiltin(StringRef DemangledCall, SPIRV::InstructionSet::InstructionSet Set, Register ReturnRegister, const SPIRVType *ReturnType, const SmallVectorImpl< Register > &Arguments)
Looks up the demangled builtin call in the SPIRVBuiltins.td records using the provided DemangledCall ...
static bool buildAtomicFloatingRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic floating-type instruction.
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
constexpr unsigned BitWidth
const MachineInstr SPIRVType
static bool generateReadImageInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
bool hasBuiltinTypePrefix(StringRef Name)
static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Type * getMDOperandAsType(const MDNode *N, unsigned I)
static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic load instruction.
static SPIRV::MemorySemantics::MemorySemantics getSPIRVMemSemantics(std::memory_order MemOrder)
static bool generateRelationalInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool buildAtomicInitInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder)
Helper function for translating atomic init to OpStore.
static bool generateWriteImageInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getPipeType(const TargetExtType *ExtensionType, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Type * parseTypeString(const StringRef Name, LLVMContext &Context)
bool isSpvIntrinsic(const MachineInstr &MI, Intrinsic::ID IntrinsicID)
static bool generateAtomicFloatingInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateExtInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool buildNDRange(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getNonParameterizedType(const TargetExtType *ExtensionType, const SPIRV::BuiltinType *TypeRecord, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static MachineInstr * getBlockStructInstr(Register ParamReg, MachineRegisterInfo *MRI)
static unsigned getSamplerParamFromBitmask(unsigned Bitmask)
static bool buildAtomicCompareExchangeInst(const SPIRV::IncomingCall *Call, const SPIRV::DemangledBuiltin *Builtin, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic compare-exchange instruction.
std::string getLinkStringForBuiltIn(SPIRV::BuiltIn::BuiltIn BuiltInValue)
static bool generateBuiltinVar(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static const fltSemantics & IEEEsingle() LLVM_READNONE
This struct is a compact representation of a valid (non-zero power of two) alignment.
This class contains a discriminated union of information about pointers in memory operands,...
FPRoundingMode::FPRoundingMode RoundingMode
InstructionSet::InstructionSet Set
InstructionSet::InstructionSet Set
InstructionSet::InstructionSet Set
InstructionSet::InstructionSet Set
const SmallVectorImpl< Register > & Arguments
const std::string BuiltinName
const SPIRVType * ReturnType
const Register ReturnRegister
const DemangledBuiltin * Builtin
IncomingCall(const std::string BuiltinName, const DemangledBuiltin *Builtin, const Register ReturnRegister, const SPIRVType *ReturnType, const SmallVectorImpl< Register > &Arguments)
InstructionSet::InstructionSet Set
StringRef SpirvTypeLiteral
InstructionSet::InstructionSet Set
FPRoundingMode::FPRoundingMode RoundingMode