30#define GET_INSTRINFO_CTOR_DTOR
31#include "XCoreGenInstrInfo.inc"
46void XCoreInstrInfo::anchor() {}
54 return op.isImm() &&
op.getImm() == 0;
63 int &FrameIndex)
const {
64 int Opcode =
MI.getOpcode();
65 if (Opcode == XCore::LDWFI)
67 if ((
MI.getOperand(1).isFI()) &&
68 (
MI.getOperand(2).isImm()) &&
70 FrameIndex =
MI.getOperand(1).getIndex();
71 return MI.getOperand(0).getReg();
83 int &FrameIndex)
const {
84 int Opcode =
MI.getOpcode();
85 if (Opcode == XCore::STWFI)
87 if ((
MI.getOperand(1).isFI()) &&
88 (
MI.getOperand(2).isImm()) &&
90 FrameIndex =
MI.getOperand(1).getIndex();
91 return MI.getOperand(0).getReg();
101static inline bool IsBRU(
unsigned BrOpc) {
102 return BrOpc == XCore::BRFU_u6
103 || BrOpc == XCore::BRFU_lu6
104 || BrOpc == XCore::BRBU_u6
105 || BrOpc == XCore::BRBU_lu6;
108static inline bool IsBRT(
unsigned BrOpc) {
109 return BrOpc == XCore::BRFT_ru6
110 || BrOpc == XCore::BRFT_lru6
111 || BrOpc == XCore::BRBT_ru6
112 || BrOpc == XCore::BRBT_lru6;
115static inline bool IsBRF(
unsigned BrOpc) {
116 return BrOpc == XCore::BRFF_ru6
117 || BrOpc == XCore::BRFF_lru6
118 || BrOpc == XCore::BRBF_ru6
119 || BrOpc == XCore::BRBF_lru6;
127 return BrOpc == XCore::BR_JT
128 || BrOpc == XCore::BR_JT32;
137 }
else if (
IsBRF(BrOpc)) {
193 bool AllowModify)
const {
199 if (!isUnpredicatedTerminator(*
I))
206 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
229 if (SecondLastInst &&
I !=
MBB.
begin() && isUnpredicatedTerminator(*--
I))
232 unsigned SecondLastOpc = SecondLastInst->
getOpcode();
255 I->eraseFromParent();
263 I->eraseFromParent();
276 int *BytesAdded)
const {
278 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
280 "Unexpected number of components!");
281 assert(!BytesAdded &&
"code size not handled");
297 assert(
Cond.size() == 2 &&
"Unexpected number of components!");
307 assert(!BytesRemoved &&
"code size not handled");
317 I->eraseFromParent();
327 I->eraseFromParent();
335 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
336 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
338 if (GRDest && GRSrc) {
345 if (GRDest && SrcReg == XCore::SP) {
350 if (DestReg == XCore::SP && GRSrc) {
363 if (
I !=
MBB.
end() && !
I->isDebugInstr())
364 DL =
I->getDebugLoc();
385 if (
I !=
MBB.
end() && !
I->isDebugInstr())
386 DL =
I->getDebugLoc();
402 "Invalid XCore branch condition!");
408 return val < (1 << 6);
412 return val < (1 << 16);
420 return (
N >= 1 &&
N <= 8) ||
N == 16 ||
N == 24 ||
N == 32;
429 dl =
MI->getDebugLoc();
437 int Opcode =
isImmU6(
Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
static bool isZeroImm(const MachineOperand &Op)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
static bool isImmU16(unsigned val)
static bool isImmU6(unsigned val)
static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
GetCondFromBranchOpc - Return the XCore CC that matches the correspondent Branch instruction opcode.
static bool IsBRU(unsigned BrOpc)
static bool IsBR_JT(unsigned BrOpc)
static bool isImmMskBitp(unsigned val)
static bool IsBRT(unsigned BrOpc)
static bool IsBRF(unsigned BrOpc)
static bool IsCondBranch(unsigned BrOpc)
static unsigned GetCondBranchFromCond(XCore::CondCode CC)
GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This is an important base class in LLVM.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Wrapper class representing physical registers. Should be passed by value.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock * getMBB() const
static MachineOperand CreateImm(int64_t Val)
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static IntegerType * getInt32Ty(LLVMContext &C)
LLVM Value Representation.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isMask_32(uint32_t Value)
Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getKillRegState(bool B)
This struct is a compact representation of a valid (non-zero power of two) alignment.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.