30#include "llvm/IR/IntrinsicsAArch64.h"
33#include <initializer_list>
35#define DEBUG_TYPE "aarch64-legalinfo"
38using namespace LegalizeActions;
39using namespace LegalizeMutations;
40using namespace LegalityPredicates;
41using namespace MIPatternMatch;
45 using namespace TargetOpcode;
69 std::initializer_list<LLT> PackedVectorAllTypeList = {
75 std::initializer_list<LLT> ScalarAndPtrTypesList = {s8, s16, s32, s64, p0};
82 if (!ST.hasNEON() || !ST.hasFPARMv8()) {
89 const bool HasFP16 = ST.hasFullFP16();
90 const LLT &MinFPScalar = HasFP16 ? s16 : s32;
92 const bool HasCSSC = ST.hasCSSC();
93 const bool HasRCPC3 = ST.hasRCPC3();
96 {G_IMPLICIT_DEF, G_FREEZE, G_CONSTANT_FOLD_BARRIER})
97 .legalFor({p0, s8, s16, s32, s64})
98 .legalFor(PackedVectorAllTypeList)
110 .legalFor(PackedVectorAllTypeList)
121 .
legalFor({s32, s64, v4s16, v8s16, v2s32, v4s32, v2s64})
123 .clampScalar(0, s32, s64)
124 .clampNumElements(0, v4s16, v8s16)
125 .clampNumElements(0, v2s32, v4s32)
126 .clampNumElements(0, v2s64, v2s64)
127 .moreElementsToNextPow2(0);
130 .legalFor({s32, s64, v2s32, v2s64, v4s32, v4s16, v8s16, v16s8, v8s8})
131 .widenScalarToNextPow2(0)
139 return Query.
Types[0].getNumElements() <= 2;
144 return Query.
Types[0].getNumElements() <= 4;
149 return Query.
Types[0].getNumElements() <= 16;
156 const auto &SrcTy = Query.
Types[0];
157 const auto &AmtTy = Query.
Types[1];
158 return !SrcTy.isVector() && SrcTy.getSizeInBits() == 32 &&
159 AmtTy.getSizeInBits() == 32;
173 .widenScalarToNextPow2(0)
184 .
legalFor({{p0, s64}, {v2p0, v2s64}})
185 .clampScalarOrElt(1, s64, s64)
191 .legalFor({s32, s64})
193 .clampScalar(0, s32, s64)
198 .lowerFor({s8, s16, s32, s64, v2s64, v4s32, v2s32})
200 .clampScalarOrElt(0, s32, s64)
201 .clampNumElements(0, v2s32, v4s32)
202 .clampNumElements(0, v2s64, v2s64)
203 .moreElementsToNextPow2(0);
207 .widenScalarToNextPow2(0, 32)
212 .legalFor({s64, v8s16, v16s8, v4s32})
216 {G_SMIN, G_SMAX, G_UMIN, G_UMAX});
219 .
legalFor({s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
226 .
legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32});
237 {G_SADDE, G_SSUBE, G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO})
238 .legalFor({{s32, s32}, {s64, s32}})
239 .clampScalar(0, s32, s64)
244 G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM,
245 G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR,
246 G_FRINT, G_FNEARBYINT, G_INTRINSIC_TRUNC,
247 G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
248 .legalFor({MinFPScalar, s32, s64, v2s32, v4s32, v2s64})
250 const auto &Ty = Query.
Types[0];
251 return (Ty == v8s16 || Ty == v4s16) && HasFP16;
254 .minScalarOrElt(0, MinFPScalar)
266 .legalFor({{s64, MinFPScalar}, {s64, s32}, {s64, s64}})
267 .libcallFor({{s64, s128}})
268 .minScalarOrElt(1, MinFPScalar);
271 G_FLOG10, G_FTAN, G_FEXP, G_FEXP2, G_FEXP10})
276 .libcallFor({s32, s64});
304 for (
unsigned Op : {G_SEXTLOAD, G_ZEXTLOAD}) {
307 if (
Op == G_SEXTLOAD)
312 .legalForTypesWithMemDesc({{s32, p0, s8, 8},
320 {v2s32, p0, s64, 8}})
321 .widenScalarToNextPow2(0)
322 .clampScalar(0, s32, s64)
325 .unsupportedIfMemSizeNotPow2()
339 LoadActions.legalForTypesWithMemDesc({
341 {nxv16s8, p0, nxv16s8, 8},
342 {nxv8s16, p0, nxv8s16, 8},
343 {nxv4s32, p0, nxv4s32, 8},
344 {nxv2s64, p0, nxv2s64, 8},
350 StoreActions.legalForTypesWithMemDesc({
352 {nxv16s8, p0, nxv16s8, 8},
353 {nxv8s16, p0, nxv8s16, 8},
354 {nxv4s32, p0, nxv4s32, 8},
355 {nxv2s64, p0, nxv2s64, 8},
361 return HasRCPC3 && Query.
Types[0] == s128 &&
365 return Query.
Types[0] == s128 &&
368 .legalForTypesWithMemDesc({{s8, p0, s8, 8},
375 {v16s8, p0, s128, 8},
377 {v8s16, p0, s128, 8},
379 {v4s32, p0, s128, 8},
380 {v2s64, p0, s128, 8}})
382 .legalForTypesWithMemDesc(
383 {{s32, p0, s8, 8}, {s32, p0, s16, 8}, {s64, p0, s32, 8}})
384 .widenScalarToNextPow2(0, 8)
385 .clampMaxNumElements(0, s8, 16)
386 .clampMaxNumElements(0, s16, 8)
387 .clampMaxNumElements(0, s32, 4)
388 .clampMaxNumElements(0, s64, 2)
389 .clampMaxNumElements(0, p0, 2)
390 .lowerIfMemSizeNotByteSizePow2()
391 .clampScalar(0, s8, s64)
395 return Query.
Types[0].isScalar() &&
397 Query.
Types[0].getSizeInBits() > 32;
406 .customIf(IsPtrVecPred)
407 .scalarizeIf(
typeInSet(0, {v2s16, v2s8}), 0);
411 return HasRCPC3 && Query.
Types[0] == s128 &&
415 return Query.
Types[0] == s128 &&
418 .legalForTypesWithMemDesc(
419 {{s8, p0, s8, 8}, {s16, p0, s8, 8},
422 {s16, p0, s16, 8}, {s32, p0, s16, 8},
424 {s32, p0, s8, 8}, {s32, p0, s16, 8}, {s32, p0, s32, 8},
425 {s64, p0, s64, 8}, {s64, p0, s32, 8},
426 {p0, p0, s64, 8}, {s128, p0, s128, 8}, {v16s8, p0, s128, 8},
427 {v8s8, p0, s64, 8}, {v4s16, p0, s64, 8}, {v8s16, p0, s128, 8},
428 {v2s32, p0, s64, 8}, {v4s32, p0, s128, 8}, {v2s64, p0, s128, 8}})
429 .clampScalar(0, s8, s64)
431 return Query.
Types[0].isScalar() &&
435 .clampMaxNumElements(0, s8, 16)
436 .clampMaxNumElements(0, s16, 8)
437 .clampMaxNumElements(0, s32, 4)
438 .clampMaxNumElements(0, s64, 2)
439 .clampMaxNumElements(0, p0, 2)
440 .lowerIfMemSizeNotPow2()
447 .customIf(IsPtrVecPred)
448 .scalarizeIf(
typeInSet(0, {v2s16, v2s8}), 0);
463 {p0, v16s8, v16s8, 8},
464 {p0, v4s16, v4s16, 8},
465 {p0, v8s16, v8s16, 8},
466 {p0, v2s32, v2s32, 8},
467 {p0, v4s32, v4s32, 8},
468 {p0, v2s64, v2s64, 8},
474 auto IndexedLoadBasicPred = [=](
const LegalityQuery &Query) {
502 return MemTy == s8 || MemTy == s16;
504 return MemTy == s8 || MemTy == s16 || MemTy == s32;
512 .widenScalarToNextPow2(0)
516 const auto &Ty = Query.
Types[0];
517 if (HasFP16 && Ty == s16)
519 return Ty == s32 || Ty == s64 || Ty == s128;
521 .clampScalar(0, MinFPScalar, s128);
525 .
legalFor({{s32, s32}, {s32, s64}, {s32, p0}})
527 .clampScalar(1, s32, s64)
528 .clampScalar(0, s32, s32)
529 .minScalarEltSameAsIf(
544 .clampNumElements(1, v8s8, v16s8)
545 .clampNumElements(1, v4s16, v8s16)
546 .clampNumElements(1, v2s32, v4s32)
547 .clampNumElements(1, v2s64, v2s64)
558 const auto &Ty = Query.
Types[1];
559 return (Ty == v8s16 || Ty == v4s16) && Ty == Query.
Types[0] && HasFP16;
562 .clampScalar(0, s32, s32)
563 .clampScalarOrElt(1, MinFPScalar, s64)
564 .minScalarEltSameAsIf(
572 .clampNumElements(1, v4s16, v8s16)
573 .clampNumElements(1, v2s32, v4s32)
574 .clampMaxNumElements(1, s64, 2)
575 .moreElementsToNextPow2(1);
579 unsigned DstSize = Query.
Types[0].getSizeInBits();
582 if (Query.
Types[0].isVector())
585 if (DstSize < 8 || DstSize >= 128 || !
isPowerOf2_32(DstSize))
600 .legalIf(ExtLegalFunc)
601 .
legalFor({{v2s64, v2s32}, {v4s32, v4s16}, {v8s16, v8s8}})
602 .clampScalar(0, s64, s64)
609 return (Query.
Types[0].getScalarSizeInBits() >
610 Query.
Types[1].getScalarSizeInBits() * 2) &&
611 Query.
Types[0].isVector() &&
612 (Query.
Types[1].getScalarSizeInBits() == 8 ||
613 Query.
Types[1].getScalarSizeInBits() == 16);
615 .clampMinNumElements(1, s8, 8)
619 .
legalFor({{v2s32, v2s64}, {v4s16, v4s32}, {v8s8, v8s16}})
621 .clampMaxNumElements(0, s8, 8)
622 .clampMaxNumElements(0, s16, 4)
623 .clampMaxNumElements(0, s32, 2)
633 .clampMinNumElements(0, s8, 8)
634 .clampMinNumElements(0, s16, 4)
639 .legalFor(PackedVectorAllTypeList)
650 {{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
651 .libcallFor({{s16, s128}, {s32, s128}, {s64, s128}})
652 .clampNumElements(0, v4s16, v4s16)
658 {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
659 .clampNumElements(0, v4s32, v4s32)
665 .legalFor({{s32, s32},
674 (Query.
Types[1] == s16 || Query.
Types[1] == v4s16 ||
675 Query.
Types[1] == v8s16) &&
676 (Query.
Types[0] == s32 || Query.
Types[0] == s64 ||
677 Query.
Types[0] == v4s16 || Query.
Types[0] == v8s16);
685 return Query.
Types[1] == s16 && Query.
Types[0].getSizeInBits() > 64;
689 .widenScalarOrEltToNextPow2OrMinSize(0)
691 .widenScalarOrEltToNextPow2OrMinSize(1, HasFP16 ? 16 : 32)
694 return Query.
Types[0].getScalarSizeInBits() <= 64 &&
695 Query.
Types[0].getScalarSizeInBits() >
696 Query.
Types[1].getScalarSizeInBits();
701 return Query.
Types[1].getScalarSizeInBits() <= 64 &&
702 Query.
Types[0].getScalarSizeInBits() <
703 Query.
Types[1].getScalarSizeInBits();
706 .clampNumElements(0, v4s16, v8s16)
707 .clampNumElements(0, v2s32, v4s32)
708 .clampMaxNumElements(0, s64, 2)
710 {{s32, s128}, {s64, s128}, {s128, s128}, {s128, s32}, {s128, s64}});
713 .legalForCartesianProduct({s32, s64, v2s64, v4s32, v2s32})
716 (Query.
Types[0] == s16 || Query.
Types[0] == v4s16 ||
717 Query.
Types[0] == v8s16) &&
718 (Query.
Types[1] == s32 || Query.
Types[1] == s64 ||
719 Query.
Types[1] == v4s16 || Query.
Types[1] == v8s16);
721 .widenScalarToNextPow2(1)
728 return Query.
Types[0].getScalarSizeInBits() <
729 Query.
Types[1].getScalarSizeInBits();
734 return Query.
Types[0].getScalarSizeInBits() >
735 Query.
Types[1].getScalarSizeInBits();
738 .clampNumElements(0, v4s16, v8s16)
745 .clampScalar(0, s32, s32);
749 .
legalFor({{s32, s32}, {s64, s32}, {p0, s32}})
750 .widenScalarToNextPow2(0)
768 .
legalFor({{s64, p0}, {v2s64, v2p0}})
769 .widenScalarToNextPow2(0, 64)
774 return Query.
Types[0].getSizeInBits() != Query.
Types[1].getSizeInBits();
776 .legalFor({{p0, s64}, {v2p0, v2s64}});
783 .legalForCartesianProduct({s64, v8s8, v4s16, v2s32})
784 .legalForCartesianProduct({s128, v16s8, v8s16, v4s32, v2s64, v2p0})
786 return Query.
Types[0].isVector() != Query.
Types[1].isVector();
789 .clampNumElements(0, v8s8, v16s8)
790 .clampNumElements(0, v4s16, v8s16)
791 .clampNumElements(0, v2s32, v4s32)
800 .clampScalar(0, s8, s64)
808 return ST.outlineAtomics() && !ST.hasLSE();
816 return Query.
Types[0].getSizeInBits() == 128 &&
817 !UseOutlineAtomics(Query);
824 G_ATOMICRMW_SUB, G_ATOMICRMW_AND, G_ATOMICRMW_OR,
835 {G_ATOMICRMW_MIN, G_ATOMICRMW_MAX, G_ATOMICRMW_UMIN, G_ATOMICRMW_UMAX})
842 for (
unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
843 unsigned BigTyIdx =
Op == G_MERGE_VALUES ? 0 : 1;
844 unsigned LitTyIdx =
Op == G_MERGE_VALUES ? 1 : 0;
851 switch (Q.
Types[BigTyIdx].getSizeInBits()) {
859 switch (Q.
Types[LitTyIdx].getSizeInBits()) {
873 const LLT &EltTy = Query.
Types[1].getElementType();
874 return Query.
Types[0] != EltTy;
879 return VecTy == v2s16 || VecTy == v4s16 || VecTy == v8s16 ||
880 VecTy == v4s32 || VecTy == v2s64 || VecTy == v2s32 ||
881 VecTy == v8s8 || VecTy == v16s8 || VecTy == v2p0;
887 return Query.
Types[1].getNumElements() <= 2;
892 return Query.
Types[1].getNumElements() <= 4;
897 return Query.
Types[1].getNumElements() <= 8;
902 return Query.
Types[1].getNumElements() <= 16;
905 .minScalarOrElt(0, s8)
915 typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64, v2p0}))
933 .clampNumElements(0, v4s32, v4s32)
943 {s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
945 .widenScalarToNextPow2(1, 32)
946 .clampScalar(1, s32, s64)
947 .scalarSameSizeAs(0, 1);
953 .widenScalarToNextPow2(0, 32)
964 return (HasCSSC &&
typeInSet(0, {s32, s64})(Query));
967 return (!HasCSSC &&
typeInSet(0, {s32, s64})(Query));
979 {v2s64, v2p0, v2s32, v4s32, v4s16, v16s8, v8s8, v8s16}, DstTy);
984 return !Query.
Types[1].isVector();
988 return Query.
Types[0].isVector() && Query.
Types[1].isVector() &&
989 Query.
Types[0].getNumElements() >
990 Query.
Types[1].getNumElements();
996 return Query.
Types[0].isVector() && Query.
Types[1].isVector() &&
997 Query.
Types[0].getNumElements() <
998 Query.
Types[1].getNumElements();
1001 .widenScalarOrEltToNextPow2OrMinSize(0, 8)
1002 .clampNumElements(0, v8s8, v16s8)
1003 .clampNumElements(0, v4s16, v8s16)
1004 .clampNumElements(0, v4s32, v4s32)
1005 .clampNumElements(0, v2s64, v2s64);
1008 .
legalFor({{v4s32, v2s32}, {v8s16, v4s16}, {v16s8, v8s8}});
1025 .customForCartesianProduct({p0}, {s8}, {s64})
1029 .legalForCartesianProduct({p0}, {p0}, {s64})
1045 .legalFor({s32, s64});
1046 ABSActions.legalFor(PackedVectorAllTypeList)
1054 [=](
const LegalityQuery &Query) {
return std::make_pair(0, v4s16); })
1057 [=](
const LegalityQuery &Query) {
return std::make_pair(0, v2s32); })
1058 .clampNumElements(0, v8s8, v16s8)
1059 .clampNumElements(0, v4s16, v8s16)
1060 .clampNumElements(0, v2s32, v4s32)
1061 .clampNumElements(0, v2s64, v2s64)
1062 .moreElementsToNextPow2(0)
1069 .
legalFor({{s32, v2s32}, {s32, v4s32}, {s64, v2s64}})
1071 const auto &Ty = Query.
Types[1];
1072 return (Ty == v4s16 || Ty == v8s16) && HasFP16;
1074 .minScalarOrElt(0, MinFPScalar)
1105 .clampMaxNumElements(1, s64, 2)
1112 G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM})
1113 .legalFor({{s32, v4s32}, {s32, v2s32}, {s64, v2s64}})
1115 const auto &Ty = Query.
Types[1];
1116 return Query.
Types[0] == s16 && (Ty == v8s16 || Ty == v4s16) && HasFP16;
1118 .minScalarOrElt(0, MinFPScalar)
1132 {G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX})
1133 .legalFor({{s8, v8s8},
1141 return Query.
Types[1].isVector() &&
1142 Query.
Types[1].getElementType() != s8 &&
1143 Query.
Types[1].getNumElements() & 1;
1146 .clampMaxNumElements(1, s64, 2)
1154 {G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
1170 return std::make_pair(1, SrcTy.
divide(2));
1176 .customFor({{s32, s32}, {s32, s64}, {s64, s64}})
1180 .
legalFor({{s32, s64}, {s64, s64}})
1182 return Q.
Types[0].isScalar() && Q.
Types[1].getScalarSizeInBits() < 64;
1188 .customFor({{s32, s32}, {s64, s64}});
1194 .legalFor({{s32, s32},
1198 .customFor({{s128, s128},
1206 .legalFor({{v8s8, v8s8},
1208 .customFor({{s32, s32},
1217 .clampScalar(0, s32, s128)
1218 .widenScalarToNextPow2(0)
1219 .minScalarEltSameAsIf(always, 1, 0)
1220 .maxScalarEltSameAsIf(always, 1, 0);
1223 .legalFor({v2s64, v2s32, v4s32, v4s16, v8s16, v8s8, v16s8})
1224 .clampNumElements(0, v8s8, v16s8)
1234 .legalFor({{s64, s32}, {s64, s64}});
1250 G_GET_FPMODE, G_SET_FPMODE, G_RESET_FPMODE})
1258 verify(*ST.getInstrInfo());
1267 switch (
MI.getOpcode()) {
1271 case TargetOpcode::G_VAARG:
1272 return legalizeVaArg(
MI,
MRI, MIRBuilder);
1273 case TargetOpcode::G_LOAD:
1274 case TargetOpcode::G_STORE:
1275 return legalizeLoadStore(
MI,
MRI, MIRBuilder, Observer);
1276 case TargetOpcode::G_SHL:
1277 case TargetOpcode::G_ASHR:
1278 case TargetOpcode::G_LSHR:
1279 return legalizeShlAshrLshr(
MI,
MRI, MIRBuilder, Observer);
1280 case TargetOpcode::G_GLOBAL_VALUE:
1281 return legalizeSmallCMGlobalValue(
MI,
MRI, MIRBuilder, Observer);
1282 case TargetOpcode::G_SBFX:
1283 case TargetOpcode::G_UBFX:
1284 return legalizeBitfieldExtract(
MI,
MRI, Helper);
1285 case TargetOpcode::G_FSHL:
1286 case TargetOpcode::G_FSHR:
1287 return legalizeFunnelShift(
MI,
MRI, MIRBuilder, Observer, Helper);
1288 case TargetOpcode::G_ROTR:
1289 return legalizeRotate(
MI,
MRI, Helper);
1290 case TargetOpcode::G_CTPOP:
1291 return legalizeCTPOP(
MI,
MRI, Helper);
1292 case TargetOpcode::G_ATOMIC_CMPXCHG:
1293 return legalizeAtomicCmpxchg128(
MI,
MRI, Helper);
1294 case TargetOpcode::G_CTTZ:
1295 return legalizeCTTZ(
MI, Helper);
1296 case TargetOpcode::G_BZERO:
1297 case TargetOpcode::G_MEMCPY:
1298 case TargetOpcode::G_MEMMOVE:
1299 case TargetOpcode::G_MEMSET:
1300 return legalizeMemOps(
MI, Helper);
1301 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
1302 return legalizeExtractVectorElt(
MI,
MRI, Helper);
1303 case TargetOpcode::G_DYN_STACKALLOC:
1304 return legalizeDynStackAlloc(
MI, Helper);
1305 case TargetOpcode::G_PREFETCH:
1306 return legalizePrefetch(
MI, Helper);
1307 case TargetOpcode::G_ABS:
1309 case TargetOpcode::G_ICMP:
1310 return legalizeICMP(
MI,
MRI, MIRBuilder);
1321 assert(
MI.getOpcode() == TargetOpcode::G_FSHL ||
1322 MI.getOpcode() == TargetOpcode::G_FSHR);
1326 Register ShiftNo =
MI.getOperand(3).getReg();
1327 LLT ShiftTy =
MRI.getType(ShiftNo);
1332 LLT OperationTy =
MRI.getType(
MI.getOperand(0).getReg());
1336 if (!VRegAndVal || VRegAndVal->Value.urem(
BitWidth) == 0)
1342 Amount =
MI.getOpcode() == TargetOpcode::G_FSHL ?
BitWidth - Amount : Amount;
1346 if (ShiftTy.
getSizeInBits() == 64 &&
MI.getOpcode() == TargetOpcode::G_FSHR &&
1353 if (
MI.getOpcode() == TargetOpcode::G_FSHR) {
1355 MI.getOperand(3).setReg(Cast64.getReg(0));
1360 else if (
MI.getOpcode() == TargetOpcode::G_FSHL) {
1362 {
MI.getOperand(1).
getReg(),
MI.getOperand(2).getReg(),
1364 MI.eraseFromParent();
1373 Register SrcReg1 =
MI.getOperand(2).getReg();
1374 Register SrcReg2 =
MI.getOperand(3).getReg();
1375 LLT DstTy =
MRI.getType(DstReg);
1376 LLT SrcTy =
MRI.getType(SrcReg1);
1393 MIRBuilder.
buildNot(DstReg, CmpReg);
1395 MI.eraseFromParent();
1405 LLT AmtTy =
MRI.getType(AmtReg);
1411 MI.getOperand(2).setReg(NewAmt.getReg(0));
1416bool AArch64LegalizerInfo::legalizeSmallCMGlobalValue(
1419 assert(
MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE);
1424 auto &GlobalOp =
MI.getOperand(1);
1426 if (GlobalOp.isSymbol())
1428 const auto* GV = GlobalOp.getGlobal();
1429 if (GV->isThreadLocal())
1438 auto Offset = GlobalOp.getOffset();
1443 MRI.setRegClass(
ADRP.getReg(0), &AArch64::GPR64RegClass);
1460 "Should not have folded in an offset for a tagged global!");
1462 .addGlobalAddress(GV, 0x100000000,
1465 MRI.setRegClass(
ADRP.getReg(0), &AArch64::GPR64RegClass);
1469 .addGlobalAddress(GV,
Offset,
1471 MI.eraseFromParent();
1478 switch (IntrinsicID) {
1479 case Intrinsic::vacopy: {
1481 unsigned VaListSize =
1493 VaListSize,
Align(PtrSize)));
1497 VaListSize,
Align(PtrSize)));
1498 MI.eraseFromParent();
1501 case Intrinsic::get_dynamic_area_offset: {
1504 MI.eraseFromParent();
1507 case Intrinsic::aarch64_mops_memset_tag: {
1508 assert(
MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
1512 auto &
Value =
MI.getOperand(3);
1514 Value.setReg(ExtValueReg);
1517 case Intrinsic::aarch64_prefetch: {
1519 auto &AddrVal =
MI.getOperand(1);
1521 int64_t IsWrite =
MI.getOperand(2).getImm();
1522 int64_t
Target =
MI.getOperand(3).getImm();
1523 int64_t IsStream =
MI.getOperand(4).getImm();
1524 int64_t IsData =
MI.getOperand(5).getImm();
1526 unsigned PrfOp = (IsWrite << 4) |
1532 MI.eraseFromParent();
1535 case Intrinsic::aarch64_neon_uaddv:
1536 case Intrinsic::aarch64_neon_saddv:
1537 case Intrinsic::aarch64_neon_umaxv:
1538 case Intrinsic::aarch64_neon_smaxv:
1539 case Intrinsic::aarch64_neon_uminv:
1540 case Intrinsic::aarch64_neon_sminv: {
1543 bool IsSigned = IntrinsicID == Intrinsic::aarch64_neon_saddv ||
1544 IntrinsicID == Intrinsic::aarch64_neon_smaxv ||
1545 IntrinsicID == Intrinsic::aarch64_neon_sminv;
1547 auto OldDst =
MI.getOperand(0).getReg();
1548 auto OldDstTy =
MRI.getType(OldDst);
1549 LLT NewDstTy =
MRI.getType(
MI.getOperand(2).getReg()).getElementType();
1550 if (OldDstTy == NewDstTy)
1553 auto NewDst =
MRI.createGenericVirtualRegister(NewDstTy);
1556 MI.getOperand(0).setReg(NewDst);
1560 MIB.
buildExtOrTrunc(IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT,
1565 case Intrinsic::aarch64_neon_uaddlp:
1566 case Intrinsic::aarch64_neon_saddlp: {
1569 unsigned Opc = IntrinsicID == Intrinsic::aarch64_neon_uaddlp
1571 : AArch64::G_SADDLP;
1573 MI.eraseFromParent();
1577 case Intrinsic::aarch64_neon_uaddlv:
1578 case Intrinsic::aarch64_neon_saddlv: {
1582 unsigned Opc = IntrinsicID == Intrinsic::aarch64_neon_uaddlv
1584 : AArch64::G_SADDLV;
1587 LLT DstTy =
MRI.getType(DstReg);
1611 MI.eraseFromParent();
1615 case Intrinsic::aarch64_neon_smax:
1616 case Intrinsic::aarch64_neon_smin:
1617 case Intrinsic::aarch64_neon_umax:
1618 case Intrinsic::aarch64_neon_umin:
1619 case Intrinsic::aarch64_neon_fmax:
1620 case Intrinsic::aarch64_neon_fmin:
1621 case Intrinsic::aarch64_neon_fmaxnm:
1622 case Intrinsic::aarch64_neon_fminnm: {
1624 if (IntrinsicID == Intrinsic::aarch64_neon_smax)
1626 else if (IntrinsicID == Intrinsic::aarch64_neon_smin)
1628 else if (IntrinsicID == Intrinsic::aarch64_neon_umax)
1630 else if (IntrinsicID == Intrinsic::aarch64_neon_umin)
1632 else if (IntrinsicID == Intrinsic::aarch64_neon_fmax)
1633 MIB.
buildInstr(TargetOpcode::G_FMAXIMUM, {
MI.getOperand(0)},
1634 {
MI.getOperand(2),
MI.getOperand(3)});
1635 else if (IntrinsicID == Intrinsic::aarch64_neon_fmin)
1636 MIB.
buildInstr(TargetOpcode::G_FMINIMUM, {
MI.getOperand(0)},
1637 {
MI.getOperand(2),
MI.getOperand(3)});
1638 else if (IntrinsicID == Intrinsic::aarch64_neon_fmaxnm)
1639 MIB.
buildInstr(TargetOpcode::G_FMAXNUM, {
MI.getOperand(0)},
1640 {
MI.getOperand(2),
MI.getOperand(3)});
1641 else if (IntrinsicID == Intrinsic::aarch64_neon_fminnm)
1642 MIB.
buildInstr(TargetOpcode::G_FMINNUM, {
MI.getOperand(0)},
1643 {
MI.getOperand(2),
MI.getOperand(3)});
1644 MI.eraseFromParent();
1647 case Intrinsic::vector_reverse:
1655bool AArch64LegalizerInfo::legalizeShlAshrLshr(
1658 assert(
MI.getOpcode() == TargetOpcode::G_ASHR ||
1659 MI.getOpcode() == TargetOpcode::G_LSHR ||
1660 MI.getOpcode() == TargetOpcode::G_SHL);
1673 MI.getOperand(2).setReg(ExtCst.getReg(0));
1686 isShiftedInt<7, 3>(NewOffset)) {
1694bool AArch64LegalizerInfo::legalizeLoadStore(
1697 assert(
MI.getOpcode() == TargetOpcode::G_STORE ||
1698 MI.getOpcode() == TargetOpcode::G_LOAD);
1709 const LLT ValTy =
MRI.getType(ValReg);
1714 bool IsLoad =
MI.getOpcode() == TargetOpcode::G_LOAD;
1718 ST->hasLSE2() && ST->hasRCPC3() && (IsLoadAcquire || IsStoreRelease);
1724 Opcode = IsLoad ? AArch64::LDIAPPX : AArch64::STILPX;
1730 assert(ST->hasLSE2() &&
"ldp/stp not single copy atomic without +lse2");
1732 Opcode = IsLoad ? AArch64::LDPXi : AArch64::STPXi;
1737 NewI = MIRBuilder.
buildInstr(Opcode, {s64, s64}, {});
1743 Opcode, {}, {
Split->getOperand(0),
Split->getOperand(1)});
1747 NewI.
addUse(
MI.getOperand(1).getReg());
1758 *
MRI.getTargetRegisterInfo(),
1760 MI.eraseFromParent();
1766 LLVM_DEBUG(
dbgs() <<
"Tried to do custom legalization on wrong load/store");
1772 auto &MMO = **
MI.memoperands_begin();
1775 if (
MI.getOpcode() == TargetOpcode::G_STORE) {
1779 auto NewLoad = MIRBuilder.
buildLoad(NewTy,
MI.getOperand(1), MMO);
1782 MI.eraseFromParent();
1790 Align Alignment(
MI.getOperand(2).getImm());
1792 Register ListPtr =
MI.getOperand(1).getReg();
1794 LLT PtrTy =
MRI.getType(ListPtr);
1805 if (Alignment > PtrAlign) {
1809 auto ListTmp = MIRBuilder.
buildPtrAdd(PtrTy,
List, AlignMinus1.getReg(0));
1814 LLT ValTy =
MRI.getType(Dst);
1819 ValTy, std::max(Alignment, PtrAlign)));
1830 MI.eraseFromParent();
1834bool AArch64LegalizerInfo::legalizeBitfieldExtract(
1868 LLT Ty =
MRI.getType(Val);
1872 "Expected src and dst to have the same type!");
1880 auto Add = MIRBuilder.
buildAdd(s64, CTPOP1, CTPOP2);
1883 MI.eraseFromParent();
1887 if (!ST->hasNEON() ||
1888 MI.getMF()->getFunction().hasFnAttribute(Attribute::NoImplicitFloat)) {
1900 assert((
Size == 32 ||
Size == 64 ||
Size == 128) &&
"Expected only 32, 64, or 128 bit scalars!");
1915 Opc = Intrinsic::aarch64_neon_uaddlv;
1918 Opc = Intrinsic::aarch64_neon_uaddlp;
1921 Opc = Intrinsic::aarch64_neon_uaddlp;
1925 Opc = Intrinsic::aarch64_neon_uaddlp;
1930 Opc = Intrinsic::aarch64_neon_uaddlp;
1933 Opc = Intrinsic::aarch64_neon_uaddlp;
1939 for (
LLT HTy : HAddTys) {
1949 MI.eraseFromParent();
1953bool AArch64LegalizerInfo::legalizeAtomicCmpxchg128(
1957 auto Addr =
MI.getOperand(1).getReg();
1958 auto DesiredI = MIRBuilder.
buildUnmerge({s64, s64},
MI.getOperand(2));
1959 auto NewI = MIRBuilder.
buildUnmerge({s64, s64},
MI.getOperand(3));
1960 auto DstLo =
MRI.createGenericVirtualRegister(s64);
1961 auto DstHi =
MRI.createGenericVirtualRegister(s64);
1974 auto Ordering = (*
MI.memoperands_begin())->getMergedOrdering();
1978 Opcode = AArch64::CASPAX;
1981 Opcode = AArch64::CASPLX;
1985 Opcode = AArch64::CASPALX;
1988 Opcode = AArch64::CASPX;
1993 auto CASDst =
MRI.createGenericVirtualRegister(s128);
1994 auto CASDesired =
MRI.createGenericVirtualRegister(s128);
1995 auto CASNew =
MRI.createGenericVirtualRegister(s128);
1996 MIRBuilder.
buildInstr(TargetOpcode::REG_SEQUENCE, {CASDesired}, {})
1997 .addUse(DesiredI->getOperand(0).getReg())
1999 .
addUse(DesiredI->getOperand(1).getReg())
2000 .
addImm(AArch64::subo64);
2001 MIRBuilder.
buildInstr(TargetOpcode::REG_SEQUENCE, {CASNew}, {})
2005 .
addImm(AArch64::subo64);
2007 CAS = MIRBuilder.
buildInstr(Opcode, {CASDst}, {CASDesired, CASNew,
Addr});
2015 auto Ordering = (*
MI.memoperands_begin())->getMergedOrdering();
2019 Opcode = AArch64::CMP_SWAP_128_ACQUIRE;
2022 Opcode = AArch64::CMP_SWAP_128_RELEASE;
2026 Opcode = AArch64::CMP_SWAP_128;
2029 Opcode = AArch64::CMP_SWAP_128_MONOTONIC;
2033 auto Scratch =
MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2034 CAS = MIRBuilder.
buildInstr(Opcode, {DstLo, DstHi, Scratch},
2035 {
Addr, DesiredI->getOperand(0),
2036 DesiredI->getOperand(1), NewI->
getOperand(0),
2042 *
MRI.getTargetRegisterInfo(),
2046 MI.eraseFromParent();
2054 LLT Ty =
MRI.getType(
MI.getOperand(1).getReg());
2056 MIRBuilder.
buildCTLZ(
MI.getOperand(0).getReg(), BitReverse);
2057 MI.eraseFromParent();
2066 if (
MI.getOpcode() == TargetOpcode::G_MEMSET) {
2069 auto &
Value =
MI.getOperand(1);
2072 Value.setReg(ExtValueReg);
2079bool AArch64LegalizerInfo::legalizeExtractVectorElt(
2081 assert(
MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT);
2090bool AArch64LegalizerInfo::legalizeDynStackAlloc(
2106 Register AllocSize =
MI.getOperand(1).getReg();
2110 "Unexpected type for dynamic alloca");
2112 "Unexpected type for dynamic alloca");
2114 LLT PtrTy =
MRI.getType(Dst);
2120 MIRBuilder.
buildInstr(AArch64::PROBED_STACKALLOC_DYN, {}, {SPTmp});
2121 MRI.setRegClass(NewMI.getReg(0), &AArch64::GPR64commonRegClass);
2122 MIRBuilder.
setInsertPt(*NewMI->getParent(), NewMI);
2125 MI.eraseFromParent();
2132 auto &AddrVal =
MI.getOperand(0);
2134 int64_t IsWrite =
MI.getOperand(1).getImm();
2135 int64_t Locality =
MI.getOperand(2).getImm();
2136 int64_t
IsData =
MI.getOperand(3).getImm();
2138 bool IsStream = Locality == 0;
2139 if (Locality != 0) {
2140 assert(Locality <= 3 &&
"Prefetch locality out-of-range");
2144 Locality = 3 - Locality;
2147 unsigned PrfOp = (IsWrite << 4) | (!IsData << 3) | (Locality << 1) | IsStream;
2150 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
static void matchLDPSTPAddrMode(Register Root, Register &Base, int &Offset, MachineRegisterInfo &MRI)
This file declares the targeting of the Machinelegalizer class for AArch64.
This file declares the targeting of the RegisterBankInfo class for AArch64.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
Interface for Targets to specify which operations they can successfully select and how the others sho...
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, LostDebugLocObserver &LocObserver) const override
Called for instructions with the Custom LegalizationAction.
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
AArch64LegalizerInfo(const AArch64Subtarget &ST)
bool isTargetWindows() const
const AArch64InstrInfo * getInstrInfo() const override
bool isTargetDarwin() const
bool isTargetILP32() const
const AArch64TargetLowering * getTargetLowering() const override
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const RegisterBankInfo * getRegBankInfo() const override
Class for arbitrary precision integers.
APInt zext(unsigned width) const
Zero extend to a new width.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
int64_t getSExtValue() const
Get sign extended value.
StringRef getValueAsString() const
Return the attribute's value as a string.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
This class represents an Operation in the Expression.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Abstract class that contains various methods for clients to notify about changes.
virtual void changingInstr(MachineInstr &MI)=0
This instruction is about to be mutated in some way.
virtual void changedInstr(MachineInstr &MI)=0
This instruction was mutated in some way.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
static constexpr LLT scalable_vector(unsigned MinNumElements, unsigned ScalarSizeInBits)
Get a low-level scalable vector of some number of elements and element width.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
constexpr bool isPointerVector() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr unsigned getAddressSpace() const
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
constexpr LLT divide(int Factor) const
Return a type that is Factor times smaller.
void computeTables()
Compute any ancillary tables needed to quickly decide how an operation should be handled.
LegalizeRuleSet & minScalar(unsigned TypeIdx, const LLT Ty)
Ensure the scalar is at least as wide as Ty.
LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)
The instruction is legal when type index 0 is any type in the given list.
LegalizeRuleSet & unsupported()
The instruction is unsupported.
LegalizeRuleSet & scalarSameSizeAs(unsigned TypeIdx, unsigned SameSizeIdx)
Change the type TypeIdx to have the same scalar size as type SameSizeIdx.
LegalizeRuleSet & clampScalarOrElt(unsigned TypeIdx, const LLT MinTy, const LLT MaxTy)
Limit the range of scalar sizes to MinTy and MaxTy.
LegalizeRuleSet & libcallFor(std::initializer_list< LLT > Types)
LegalizeRuleSet & maxScalar(unsigned TypeIdx, const LLT Ty)
Ensure the scalar is at most as wide as Ty.
LegalizeRuleSet & minScalarOrElt(unsigned TypeIdx, const LLT Ty)
Ensure the scalar or element is at least as wide as Ty.
LegalizeRuleSet & clampMaxNumElements(unsigned TypeIdx, const LLT EltTy, unsigned MaxElements)
Limit the number of elements in EltTy vectors to at most MaxElements.
LegalizeRuleSet & clampMinNumElements(unsigned TypeIdx, const LLT EltTy, unsigned MinElements)
Limit the number of elements in EltTy vectors to at least MinElements.
LegalizeRuleSet & widenVectorEltsToVectorMinSize(unsigned TypeIdx, unsigned VectorSize)
Ensure the vector size is at least as wide as VectorSize by promoting the element.
LegalizeRuleSet & minScalarEltSameAsIf(LegalityPredicate Predicate, unsigned TypeIdx, unsigned LargeTypeIdx)
Conditionally widen the scalar or elt to match the size of another.
LegalizeRuleSet & customForCartesianProduct(std::initializer_list< LLT > Types)
LegalizeRuleSet & moreElementsToNextPow2(unsigned TypeIdx)
Add more elements to the vector to reach the next power of two.
LegalizeRuleSet & lower()
The instruction is lowered.
LegalizeRuleSet & moreElementsIf(LegalityPredicate Predicate, LegalizeMutation Mutation)
Add more elements to reach the type selected by the mutation if the predicate is true.
LegalizeRuleSet & lowerIf(LegalityPredicate Predicate)
The instruction is lowered if predicate is true.
LegalizeRuleSet & clampScalar(unsigned TypeIdx, const LLT MinTy, const LLT MaxTy)
Limit the range of scalar sizes to MinTy and MaxTy.
LegalizeRuleSet & custom()
Unconditionally custom lower.
LegalizeRuleSet & minScalarSameAs(unsigned TypeIdx, unsigned LargeTypeIdx)
Widen the scalar to match the size of another.
LegalizeRuleSet & unsupportedIf(LegalityPredicate Predicate)
LegalizeRuleSet & minScalarOrEltIf(LegalityPredicate Predicate, unsigned TypeIdx, const LLT Ty)
Ensure the scalar or element is at least as wide as Ty.
LegalizeRuleSet & widenScalarIf(LegalityPredicate Predicate, LegalizeMutation Mutation)
Widen the scalar to the one selected by the mutation if the predicate is true.
LegalizeRuleSet & clampNumElements(unsigned TypeIdx, const LLT MinTy, const LLT MaxTy)
Limit the number of elements for the given vectors to at least MinTy's number of elements and at most...
LegalizeRuleSet & maxScalarIf(LegalityPredicate Predicate, unsigned TypeIdx, const LLT Ty)
Conditionally limit the maximum size of the scalar.
LegalizeRuleSet & customIf(LegalityPredicate Predicate)
LegalizeRuleSet & widenScalarToNextPow2(unsigned TypeIdx, unsigned MinSize=0)
Widen the scalar to the next power of two that is at least MinSize.
LegalizeRuleSet & scalarize(unsigned TypeIdx)
LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)
The instruction is legal when type indexes 0 and 1 are both in the given list.
LegalizeRuleSet & legalForTypesWithMemDesc(std::initializer_list< LegalityPredicates::TypePairAndMemDesc > TypesAndMemDesc)
The instruction is legal when type indexes 0 and 1 along with the memory size and minimum alignment i...
LegalizeRuleSet & libcallIf(LegalityPredicate Predicate)
Like legalIf, but for the Libcall action.
LegalizeRuleSet & legalIf(LegalityPredicate Predicate)
The instruction is legal if predicate is true.
LegalizeResult lowerDynStackAlloc(MachineInstr &MI)
LegalizeResult lowerBitCount(MachineInstr &MI)
LegalizeResult lowerExtractInsertVectorElt(MachineInstr &MI)
Lower a vector extract or insert by writing the vector to a stack temporary and reloading the element...
LegalizeResult lowerAbsToCNeg(MachineInstr &MI)
const TargetLowering & getTargetLowering() const
LegalizeResult lowerFunnelShiftAsShifts(MachineInstr &MI)
@ Legalized
Instruction has been legalized and the MachineFunction changed.
@ UnableToLegalize
Some kind of error has occurred and we could not legalize this instruction.
GISelChangeObserver & Observer
To keep track of changes made by the LegalizerHelper.
Register getDynStackAllocTargetPtr(Register SPReg, Register AllocSize, Align Alignment, LLT PtrTy)
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)
Get the action definition builder for the given opcode.
const LegacyLegalizerInfo & getLegacyLegalizerInfo() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ZEXT Op.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_TRUNC Op.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Wrapper class representing virtual and physical registers.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
const TargetMachine & getTargetMachine() const
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Primary interface to the complete machine description for the target machine.
Target - Wrapper for Target specific information.
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
LegalityPredicate scalarOrEltWiderThan(unsigned TypeIdx, unsigned Size)
True iff the specified type index is a scalar or a vector with an element type that's wider than the ...
LegalityPredicate typeInSet(unsigned TypeIdx, std::initializer_list< LLT > TypesInit)
True iff the given type index is one of the specified types.
LegalityPredicate smallerThan(unsigned TypeIdx0, unsigned TypeIdx1)
True iff the first type index has a smaller total bit size than second type index.
LegalityPredicate atomicOrderingAtLeastOrStrongerThan(unsigned MMOIdx, AtomicOrdering Ordering)
True iff the specified MMO index has at an atomic ordering of at Ordering or stronger.
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
Predicate all(Predicate P0, Predicate P1)
True iff P0 and P1 are true.
LegalityPredicate typeIs(unsigned TypeIdx, LLT TypesInit)
True iff the given type index is the specified type.
Predicate predNot(Predicate P)
True iff P is false.
@ Bitcast
Perform the operation on a different, but equivalently sized type.
LegalizeMutation moreElementsToNextPow2(unsigned TypeIdx, unsigned Min=0)
Add more elements to the type for the given type index to the next power of.
LegalizeMutation scalarize(unsigned TypeIdx)
Break up the vector type for the given type index into the element type.
LegalizeMutation widenScalarOrEltToNextPow2(unsigned TypeIdx, unsigned Min=0)
Widen the scalar type or vector element type for the given type index to the next power of 2.
LegalizeMutation changeTo(unsigned TypeIdx, LLT Ty)
Select this specific type for the given type index.
LegalizeMutation changeElementSizeTo(unsigned TypeIdx, unsigned FromTypeIdx)
Change the scalar size or element size to have the same scalar size as type index FromIndex.
operand_type_match m_Reg()
ConstantMatch< APInt > m_ICst(APInt &Cst)
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, false > m_GPtrAdd(const LHS &L, const RHS &R)
This is an optimization pass for GlobalISel generic memory operations.
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
constexpr unsigned BitWidth
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
unsigned Log2(Align A)
Returns the log2 of the alignment.
std::function< bool(const LegalityQuery &)> LegalityPredicate
This struct is a compact representation of a valid (non-zero power of two) alignment.
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
ArrayRef< MemDesc > MMODescrs
Operations which require memory can use this to place requirements on the memory type for each MMO.
This class contains a discriminated union of information about pointers in memory operands,...