LLVM 20.0.0git
MipsFixupKinds.h
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1//===-- MipsFixupKinds.h - Mips Specific Fixup Entries ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSFIXUPKINDS_H
10#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSFIXUPKINDS_H
11
12#include "llvm/MC/MCFixup.h"
13
14namespace llvm {
15namespace Mips {
16 // Although most of the current fixup types reflect a unique relocation
17 // one can have multiple fixup types for a given relocation and thus need
18 // to be uniquely named.
19 //
20 // This table *must* be in the same order of
21 // MCFixupKindInfo Infos[Mips::NumTargetFixupKinds]
22 // in MipsAsmBackend.cpp.
23 //
24 enum Fixups {
25 // Branch fixups resulting in R_MIPS_16.
27
28 // Pure 32 bit data fixup resulting in - R_MIPS_32.
30
31 // Full 32 bit data relative data fixup resulting in - R_MIPS_REL32.
33
34 // Jump 26 bit fixup resulting in - R_MIPS_26.
36
37 // Pure upper 16 bit fixup resulting in - R_MIPS_HI16.
39
40 // Pure lower 16 bit fixup resulting in - R_MIPS_LO16.
42
43 // 16 bit fixup for GP offest resulting in - R_MIPS_GPREL16.
45
46 // 16 bit literal fixup resulting in - R_MIPS_LITERAL.
48
49 // Symbol fixup resulting in - R_MIPS_GOT16.
51
52 // PC relative branch fixup resulting in - R_MIPS_PC16.
54
55 // resulting in - R_MIPS_CALL16.
57
58 // resulting in - R_MIPS_GPREL32.
60
61 // resulting in - R_MIPS_SHIFT5.
63
64 // resulting in - R_MIPS_SHIFT6.
66
67 // Pure 64 bit data fixup resulting in - R_MIPS_64.
69
70 // resulting in - R_MIPS_TLS_GD.
72
73 // resulting in - R_MIPS_TLS_GOTTPREL.
75
76 // resulting in - R_MIPS_TLS_TPREL_HI16.
78
79 // resulting in - R_MIPS_TLS_TPREL_LO16.
81
82 // resulting in - R_MIPS_TLS_LDM.
84
85 // resulting in - R_MIPS_TLS_DTPREL_HI16.
87
88 // resulting in - R_MIPS_TLS_DTPREL_LO16.
90
91 // PC relative branch fixup resulting in - R_MIPS_PC16
93
94 // resulting in - R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16
95 // R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI16
98
99 // resulting in - R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16
100 // R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16
103
104 // resulting in - R_MIPS_PAGE
106
107 // resulting in - R_MIPS_GOT_OFST
109
110 // resulting in - R_MIPS_GOT_DISP
112
113 // resulting in - R_MIPS_HIGHER/R_MICROMIPS_HIGHER
116
117 // resulting in - R_MIPS_HIGHEST/R_MICROMIPS_HIGHEST
120
121 // resulting in - R_MIPS_GOT_HI16
123
124 // resulting in - R_MIPS_GOT_LO16
126
127 // resulting in - R_MIPS_CALL_HI16
129
130 // resulting in - R_MIPS_CALL_LO16
132
133 // resulting in - R_MIPS_PC18_S3
135
136 // resulting in - R_MIPS_PC19_S2
138
139 // resulting in - R_MIPS_PC21_S2
141
142 // resulting in - R_MIPS_PC26_S2
144
145 // resulting in - R_MIPS_PCHI16
147
148 // resulting in - R_MIPS_PCLO16
150
151 // resulting in - R_MICROMIPS_26_S1
153
154 // resulting in - R_MICROMIPS_HI16
156
157 // resulting in - R_MICROMIPS_LO16
159
160 // resulting in - R_MICROMIPS_GOT16
162
163 // resulting in - R_MICROMIPS_PC7_S1
165
166 // resulting in - R_MICROMIPS_PC10_S1
168
169 // resulting in - R_MICROMIPS_PC16_S1
171
172 // resulting in - R_MICROMIPS_PC26_S1
174
175 // resulting in - R_MICROMIPS_PC19_S2
177
178 // resulting in - R_MICROMIPS_PC18_S3
180
181 // resulting in - R_MICROMIPS_PC21_S1
183
184 // resulting in - R_MICROMIPS_CALL16
186
187 // resulting in - R_MICROMIPS_GOT_DISP
189
190 // resulting in - R_MICROMIPS_GOT_PAGE
192
193 // resulting in - R_MICROMIPS_GOT_OFST
195
196 // resulting in - R_MICROMIPS_TLS_GD
198
199 // resulting in - R_MICROMIPS_TLS_LDM
201
202 // resulting in - R_MICROMIPS_TLS_DTPREL_HI16
204
205 // resulting in - R_MICROMIPS_TLS_DTPREL_LO16
207
208 // resulting in - R_MICROMIPS_TLS_GOTTPREL.
210
211 // resulting in - R_MICROMIPS_TLS_TPREL_HI16
213
214 // resulting in - R_MICROMIPS_TLS_TPREL_LO16
216
217 // resulting in - R_MIPS_SUB/R_MICROMIPS_SUB
220
221 // resulting in - R_MIPS_JALR/R_MICROMIPS_JALR
224
225 // Marker
228 };
229} // namespace Mips
230} // namespace llvm
231
232
233#endif
@ fixup_MICROMIPS_TLS_TPREL_LO16
@ fixup_Mips_DTPREL_HI
@ fixup_MICROMIPS_PC7_S1
@ fixup_MICROMIPS_GOT_PAGE
@ fixup_MICROMIPS_PC16_S1
@ fixup_MICROMIPS_HIGHER
@ fixup_MICROMIPS_TLS_TPREL_HI16
@ fixup_MICROMIPS_PC21_S1
@ fixup_MICROMIPS_GPOFF_LO
@ fixup_MICROMIPS_PC19_S2
@ fixup_MICROMIPS_CALL16
@ fixup_MICROMIPS_TLS_LDM
@ fixup_MICROMIPS_GOT_OFST
@ fixup_MICROMIPS_TLS_DTPREL_HI16
@ fixup_MICROMIPS_PC10_S1
@ fixup_MICROMIPS_TLS_GD
@ fixup_MICROMIPS_HIGHEST
@ fixup_MICROMIPS_GOT_DISP
@ fixup_Mips_DTPREL_LO
@ fixup_MICROMIPS_PC18_S3
@ fixup_MICROMIPS_PC26_S1
@ fixup_MICROMIPS_GOTTPREL
@ fixup_MICROMIPS_TLS_DTPREL_LO16
@ fixup_Mips_Branch_PCRel
@ fixup_MICROMIPS_GPOFF_HI
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ FirstTargetFixupKind
Definition: MCFixup.h:45