13#define GET_SDNODE_DESC
14#include "RISCVGenSDNodeInfo.inc"
26 switch (
N->getOpcode()) {
29 case RISCVISD::TUPLE_EXTRACT:
30 assert(
N->getNumOperands() == 2 &&
"Expected three operands!");
32 N->getOperand(1).getValueType() == MVT::i32 &&
33 "Expected index to be an i32 target constant!");
35 case RISCVISD::TUPLE_INSERT:
36 assert(
N->getNumOperands() == 3 &&
"Expected three operands!");
38 N->getOperand(2).getValueType() == MVT::i32 &&
39 "Expected index to be an i32 target constant!");
41 case RISCVISD::VQDOT_VL:
42 case RISCVISD::VQDOTU_VL:
43 case RISCVISD::VQDOTSU_VL: {
44 assert(
N->getNumValues() == 1 &&
"Expected one result!");
45 assert(
N->getNumOperands() == 5 &&
"Expected five operands!");
46 EVT VT =
N->getValueType(0);
48 "Expected result to be an i32 scalable vector");
49 assert(
N->getOperand(0).getValueType() == VT &&
50 N->getOperand(1).getValueType() == VT &&
51 N->getOperand(2).getValueType() == VT &&
52 "Expected result and first 3 operands to have the same type!");
53 EVT MaskVT =
N->getOperand(3).getValueType();
57 "Expected mask VT to be an i1 scalable vector with same number of "
58 "elements as the result");
59 assert((
N->getOperand(4).getValueType() == MVT::i32 ||
60 N->getOperand(4).getValueType() == MVT::i64) &&
61 "Expect VL operand to be i32 or i64");
74 if (!Subtarget.hasVendorXqcilsm())
85 if (!(Alignment >= 4) || !((NumberOfBytesToWrite & 3) == 0))
90 int NumberOfWords = NumberOfBytesToWrite / 4;
97 SDValue Ops[] = {Chain, SrcValueReplicated, Dst,
104 DAG.
getVTList(MVT::Other), Ops, MVT::i32,
137 if (NumberOfWords >= 48)
140 if (NumberOfWords <= 16) {
142 return getSetwmiNode(NumberOfWords, 0);
145 if (NumberOfWords <= 32) {
147 OutChains.
push_back(getSetwmiNode(NumberOfWords - 16, 64));
148 OutChains.
push_back(getSetwmiNode(16, 0));
151 OutChains.
push_back(getSetwmiNode(NumberOfWords - 31, 124));
152 OutChains.
push_back(getSetwmiNode(15, 64));
153 OutChains.
push_back(getSetwmiNode(16, 0));
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
uint64_t getZExtValue() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
A description of a memory reference used in the backend.
@ MOVolatile
The memory access is volatile.
@ MOStore
The memory access writes data.
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo) const override
Emit target-specific code that performs a memset.
void verifyTargetNode(const SelectionDAG &DAG, const SDNode *N) const override
Checks that the given target-specific node is valid. Aborts if it is not.
~RISCVSelectionDAGInfo() override
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Proxy class that targets should inherit from if they wish to use the generated node descriptions.
void verifyTargetNode(const SelectionDAG &DAG, const SDNode *N) const override
Checks that the given target-specific node is valid. Aborts if it is not.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const TargetSubtargetInfo & getSubtarget() const
LLVM_ABI SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LLVM_ABI SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=LocationSize::precise(0), const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
MachineFunction & getMachineFunction() const
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
This struct is a compact representation of a valid (non-zero power of two) alignment.
ElementCount getVectorElementCount() const
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
This class contains a discriminated union of information about pointers in memory operands,...
MachinePointerInfo getWithOffset(int64_t O) const