LLVM 20.0.0git
llvm::AArch64PostRASchedStrategy Member List

This is the complete list of members for llvm::AArch64PostRASchedStrategy, including all inherited members.

AArch64PostRASchedStrategy(const MachineSchedContext *C)llvm::AArch64PostRASchedStrategyinline
Botllvm::PostGenericSchedulerprotected
BotCandllvm::PostGenericSchedulerprotected
BotHeightReduce enum valuellvm::GenericSchedulerBase
BotPathReduce enum valuellvm::GenericSchedulerBase
CandReason enum namellvm::GenericSchedulerBase
Cluster enum valuellvm::GenericSchedulerBase
Contextllvm::GenericSchedulerBaseprotected
DAGllvm::PostGenericSchedulerprotected
doMBBSchedRegionsTopDown() constllvm::MachineSchedStrategyinlinevirtual
dumpPolicy() constllvm::MachineSchedStrategyinlinevirtual
enterMBB(MachineBasicBlock *MBB)llvm::MachineSchedStrategyinlinevirtual
GenericSchedulerBase(const MachineSchedContext *C)llvm::GenericSchedulerBaseinlineprotected
getReasonStr(GenericSchedulerBase::CandReason Reason)llvm::GenericSchedulerBasestatic
initialize(ScheduleDAGMI *Dag) overridellvm::PostGenericSchedulervirtual
initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) overridellvm::PostGenericSchedulervirtual
leaveMBB()llvm::MachineSchedStrategyinlinevirtual
NextDefUse enum valuellvm::GenericSchedulerBase
NoCand enum valuellvm::GenericSchedulerBase
NodeOrder enum valuellvm::GenericSchedulerBase
Only1 enum valuellvm::GenericSchedulerBase
PhysReg enum valuellvm::GenericSchedulerBase
pickNode(bool &IsTopNode) overridellvm::PostGenericSchedulervirtual
pickNodeBidirectional(bool &IsTopNode)llvm::PostGenericScheduler
pickNodeFromQueue(SchedBoundary &Zone, SchedCandidate &Cand)llvm::PostGenericSchedulerprotected
PostGenericScheduler(const MachineSchedContext *C)llvm::PostGenericSchedulerinline
RegCritical enum valuellvm::GenericSchedulerBase
RegExcess enum valuellvm::GenericSchedulerBase
RegionPolicyllvm::PostGenericSchedulerprotected
registerRoots() overridellvm::PostGenericSchedulervirtual
RegMax enum valuellvm::GenericSchedulerBase
releaseBottomNode(SUnit *SU) overridellvm::PostGenericSchedulerinlinevirtual
releaseTopNode(SUnit *SU) overridellvm::PostGenericSchedulerinlinevirtual
Remllvm::GenericSchedulerBaseprotected
ResourceDemand enum valuellvm::GenericSchedulerBase
ResourceReduce enum valuellvm::GenericSchedulerBase
SchedModelllvm::GenericSchedulerBaseprotected
schedNode(SUnit *SU, bool IsTopNode) overridellvm::PostGenericSchedulervirtual
scheduleTree(unsigned SubtreeID) overridellvm::PostGenericSchedulerinlinevirtual
setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone, SchedBoundary *OtherZone)llvm::GenericSchedulerBaseprotected
shouldTrackLaneMasks() constllvm::MachineSchedStrategyinlinevirtual
shouldTrackPressure() const overridellvm::PostGenericSchedulerinlinevirtual
Stall enum valuellvm::GenericSchedulerBase
Topllvm::PostGenericSchedulerprotected
TopCandllvm::PostGenericSchedulerprotected
TopDepthReduce enum valuellvm::GenericSchedulerBase
TopPathReduce enum valuellvm::GenericSchedulerBase
traceCandidate(const SchedCandidate &Cand)llvm::GenericSchedulerBaseprotected
TRIllvm::GenericSchedulerBaseprotected
tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) overridellvm::AArch64PostRASchedStrategyprotectedvirtual
Weak enum valuellvm::GenericSchedulerBase
~MachineSchedStrategy()=defaultllvm::MachineSchedStrategyvirtual
~PostGenericScheduler() override=defaultllvm::PostGenericScheduler