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LLVM 20.0.0git
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This is the complete list of members for llvm::AArch64TargetLowering, including all inherited members.
| AArch64TargetLowering(const TargetMachine &TM, const AArch64Subtarget &STI) | llvm::AArch64TargetLowering | explicit |
| ABS enum value | llvm::TargetLoweringBase | |
| AddAnd enum value | llvm::TargetLoweringBase | |
| addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) | llvm::TargetLoweringBase | inlineprotected |
| AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) | llvm::TargetLoweringBase | inlineprotected |
| addRegisterClass(MVT VT, const TargetRegisterClass *RC) | llvm::TargetLoweringBase | inlineprotected |
| addressingModeSupportsTLS(const GlobalValue &) const | llvm::TargetLoweringBase | inlinevirtual |
| aggressivelyPreferBuildVectorSources(EVT VecVT) const | llvm::TargetLoweringBase | inlinevirtual |
| alignLoopsWithOptSize() const | llvm::TargetLoweringBase | inlinevirtual |
| allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | virtual |
| allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | |
| allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | |
| allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | |
| allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | |
| allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override | llvm::AArch64TargetLowering | virtual |
| allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast=nullptr) const override | llvm::AArch64TargetLowering | virtual |
| allowTruncateForTailCall(Type *FromTy, Type *ToTy) const | llvm::TargetLoweringBase | inlinevirtual |
| AndOrSETCCFoldKind enum name | llvm::TargetLoweringBase | |
| areJTsAllowed(const Function *Fn) const | llvm::TargetLoweringBase | inlinevirtual |
| areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) const | llvm::TargetLoweringBase | inlinevirtual |
| ArgListTy typedef | llvm::TargetLoweringBase | |
| AsmOperandInfoVector typedef | llvm::TargetLowering | |
| AtomicExpansionKind enum name | llvm::TargetLoweringBase | |
| BooleanContent enum name | llvm::TargetLoweringBase | |
| buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, SDValue N1, MutableArrayRef< int > Mask, SelectionDAG &DAG) const | llvm::TargetLowering | |
| BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) const | llvm::TargetLowering | |
| buildSDIVPow2WithCMov(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const | llvm::TargetLowering | |
| BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) const | llvm::TargetLowering | |
| C_Address enum value | llvm::TargetLowering | |
| C_Immediate enum value | llvm::TargetLowering | |
| C_Memory enum value | llvm::TargetLowering | |
| C_Other enum value | llvm::TargetLowering | |
| C_Register enum value | llvm::TargetLowering | |
| C_RegisterClass enum value | llvm::TargetLowering | |
| C_Unknown enum value | llvm::TargetLowering | |
| canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const | llvm::TargetLoweringBase | inlinevirtual |
| canCombineTruncStore(EVT ValVT, EVT MemVT, bool LegalOnly) const | llvm::TargetLoweringBase | inlinevirtual |
| canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const | llvm::TargetLowering | virtual |
| canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override | llvm::AArch64TargetLowering | virtual |
| canOpTrap(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | virtual |
| CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const | llvm::AArch64TargetLowering | |
| CCAssignFnForReturn(CallingConv::ID CC) const | llvm::AArch64TargetLowering | |
| changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InGlue, unsigned Condition, SDValue PStateSM=SDValue()) const | llvm::AArch64TargetLowering | |
| checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const | llvm::TargetLowering | inlinevirtual |
| CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const | llvm::TargetLowering | virtual |
| computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const | llvm::TargetLowering | virtual |
| computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override | llvm::AArch64TargetLowering | virtual |
| computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override | llvm::AArch64TargetLowering | virtual |
| computeRegisterProperties(const TargetRegisterInfo *TRI) | llvm::TargetLoweringBase | protected |
| ConstraintGroup typedef | llvm::TargetLowering | |
| ConstraintPair typedef | llvm::TargetLowering | |
| ConstraintType enum name | llvm::TargetLowering | |
| ConstraintWeight enum name | llvm::TargetLowering | |
| convertSelectOfConstantsToMath(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| convertSetCCLogicToBitwiseLogic(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override | llvm::AArch64TargetLowering | virtual |
| createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override | llvm::AArch64TargetLowering | virtual |
| createSelectForFMINNUM_FMAXNUM(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| CTTZTableLookup(SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned NumBitsPerElt) const | llvm::TargetLowering | |
| Custom enum value | llvm::TargetLoweringBase | |
| CW_Best enum value | llvm::TargetLowering | |
| CW_Better enum value | llvm::TargetLowering | |
| CW_Constant enum value | llvm::TargetLowering | |
| CW_Default enum value | llvm::TargetLowering | |
| CW_Good enum value | llvm::TargetLowering | |
| CW_Invalid enum value | llvm::TargetLowering | |
| CW_Memory enum value | llvm::TargetLowering | |
| CW_Okay enum value | llvm::TargetLowering | |
| CW_Register enum value | llvm::TargetLowering | |
| CW_SpecificReg enum value | llvm::TargetLowering | |
| decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const | llvm::TargetLoweringBase | inlinevirtual |
| Disabled enum value | llvm::TargetLoweringBase | |
| EmitAllocateZABuffer(MachineInstr &MI, MachineBasicBlock *BB) const | llvm::AArch64TargetLowering | |
| emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override | llvm::AArch64TargetLowering | virtual |
| emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const | llvm::TargetLoweringBase | inlinevirtual |
| emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) const | llvm::TargetLoweringBase | inlinevirtual |
| EmitDynamicProbedAlloc(MachineInstr &MI, MachineBasicBlock *MBB) const | llvm::AArch64TargetLowering | |
| emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const | llvm::TargetLoweringBase | inlinevirtual |
| emitExpandAtomicRMW(AtomicRMWInst *AI) const | llvm::TargetLoweringBase | inlinevirtual |
| EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const | llvm::AArch64TargetLowering | |
| EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const | llvm::AArch64TargetLowering | |
| EmitInitTPIDR2Object(MachineInstr &MI, MachineBasicBlock *BB) const | llvm::AArch64TargetLowering | |
| EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override | llvm::AArch64TargetLowering | virtual |
| EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override | llvm::AArch64TargetLowering | virtual |
| emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const | llvm::TargetLoweringBase | virtual |
| emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override | llvm::AArch64TargetLowering | virtual |
| EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const | llvm::AArch64TargetLowering | |
| emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const | llvm::TargetLoweringBase | protected |
| emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const | llvm::TargetLowering | inlinevirtual |
| emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override | llvm::AArch64TargetLowering | virtual |
| EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const | llvm::AArch64TargetLowering | |
| emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const | llvm::TargetLoweringBase | virtual |
| EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const | llvm::AArch64TargetLowering | |
| EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const | llvm::AArch64TargetLowering | |
| EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, bool Op0IsDef) const | llvm::AArch64TargetLowering | |
| enableAggressiveFMAFusion(EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| llvm::TargetLowering::enableAggressiveFMAFusion(LLT Ty) const | llvm::TargetLoweringBase | inlinevirtual |
| Enabled enum value | llvm::TargetLoweringBase | |
| enableExtLdPromotion() const | llvm::TargetLoweringBase | inline |
| EnableExtLdPromotion | llvm::TargetLoweringBase | protected |
| Expand enum value | llvm::TargetLoweringBase | |
| expandABD(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandABS(SDNode *N, SelectionDAG &DAG, bool IsNegative=false) const | llvm::TargetLowering | |
| expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandAVG(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandBSWAP(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandCMP(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandCTLZ(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandCTPOP(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandCTTZ(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandDIVREMByConstant(SDNode *N, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue()) const | llvm::TargetLowering | |
| expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, SDValue LHS, SDValue RHS, unsigned Scale, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFMINIMUM_FMAXIMUM(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFP_ROUND(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFunnelShift(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| ExpandInlineAsm(CallInst *) const | llvm::TargetLowering | inlinevirtual |
| expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandIS_FPCLASS(EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const | llvm::TargetLowering | |
| expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const | llvm::TargetLowering | |
| expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandREM(SDNode *Node, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandROT(SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandRoundInexactToOdd(EVT ResultVT, SDValue Op, const SDLoc &DL, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandShiftParts(SDNode *N, SDValue &Lo, SDValue &Hi, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandShlSat(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVecReduce(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVECTOR_COMPRESS(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVectorNaryOpBySplitting(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVectorSplice(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVPCTLZ(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVPCTPOP(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVPCTTZ(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandVPCTTZElements(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| fallBackToDAGISel(const Instruction &Inst) const override | llvm::AArch64TargetLowering | virtual |
| findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const | llvm::TargetLowering | virtual |
| findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const | llvm::TargetLoweringBase | protectedvirtual |
| forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl, bool Signed, EVT WideVT, const SDValue LL, const SDValue LH, const SDValue RL, const SDValue RH, SDValue &Lo, SDValue &Hi) const | llvm::TargetLowering | |
| forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl, bool Signed, const SDValue LHS, const SDValue RHS, SDValue &Lo, SDValue &Hi) const | llvm::TargetLowering | |
| functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override | llvm::AArch64TargetLowering | virtual |
| GatherAllAliasesMaxDepth | llvm::TargetLoweringBase | protected |
| generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) const override | llvm::AArch64TargetLowering | virtual |
| getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const | llvm::TargetLoweringBase | inlinevirtual |
| getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const | llvm::TargetLoweringBase | inlinevirtual |
| getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override | llvm::AArch64TargetLowering | virtual |
| getAtomicLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const | llvm::TargetLoweringBase | |
| getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const | llvm::TargetLoweringBase | |
| getBooleanContents(bool isVec, bool isFloat) const | llvm::TargetLoweringBase | inline |
| getBooleanContents(EVT Type) const | llvm::TargetLoweringBase | inline |
| getBypassSlowDivWidths() const | llvm::TargetLoweringBase | inline |
| getByValTypeAlignment(Type *Ty, const DataLayout &DL) const | llvm::TargetLoweringBase | virtual |
| getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const | llvm::TargetLowering | inline |
| getCheaperOrNeutralNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, const NegatibleCost CostThreshold=NegatibleCost::Neutral, unsigned Depth=0) const | llvm::TargetLowering | inline |
| getCmpLibcallCC(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
| getCmpLibcallReturnType() const | llvm::TargetLoweringBase | virtual |
| getCondCodeAction(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
| getConstraintPreferences(AsmOperandInfo &OpInfo) const | llvm::TargetLowering | |
| getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const | llvm::TargetLoweringBase | inlinevirtual |
| getCustomOperationAction(SDNode &Op) const | llvm::TargetLoweringBase | inlinevirtual |
| getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const | llvm::TargetLoweringBase | protected |
| getDivRefinementSteps(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
| getExceptionPointerRegister(const Constant *PersonalityFn) const override | llvm::AArch64TargetLowering | virtual |
| getExceptionSelectorRegister(const Constant *PersonalityFn) const override | llvm::AArch64TargetLowering | virtual |
| getExtendForAtomicCmpSwapArg() const | llvm::TargetLoweringBase | inlinevirtual |
| getExtendForAtomicOps() const | llvm::TargetLoweringBase | inlinevirtual |
| getExtendForContent(BooleanContent Content) | llvm::TargetLoweringBase | inlinestatic |
| getFenceOperandTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inlinevirtual |
| getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const | llvm::TargetLoweringBase | inline |
| getFrameIndexTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| getGatherAllAliasesMaxDepth() const | llvm::TargetLoweringBase | inline |
| getIndexedLoadAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
| getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
| getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
| getIndexedStoreAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
| getIRStackGuard(IRBuilderBase &IRB) const override | llvm::AArch64TargetLowering | virtual |
| getJumpConditionMergingParams(Instruction::BinaryOps, const Value *, const Value *) const | llvm::TargetLoweringBase | inlinevirtual |
| getJumpTableEncoding() const | llvm::TargetLowering | virtual |
| getJumpTableRegTy(const DataLayout &DL) const | llvm::TargetLowering | inlinevirtual |
| getLibcallCallingConv(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
| getLibcallName(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
| getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const | llvm::TargetLoweringBase | |
| getMaxAtomicSizeInBitsSupported() const | llvm::TargetLoweringBase | inline |
| getMaxDivRemBitWidthSupported() const | llvm::TargetLoweringBase | inline |
| getMaxExpandSizeMemcmp(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxGluedStoresPerMemcpy() const | llvm::TargetLoweringBase | inlinevirtual |
| getMaximumJumpTableSize() const | llvm::TargetLoweringBase | |
| getMaxLargeFPConvertBitWidthSupported() const | llvm::TargetLoweringBase | inline |
| getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const | llvm::TargetLoweringBase | virtual |
| getMaxStoresPerMemcpy(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxStoresPerMemmove(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxStoresPerMemset(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxSupportedInterleaveFactor() const override | llvm::AArch64TargetLowering | inlinevirtual |
| getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
| getMinCmpXchgSizeInBits() const | llvm::TargetLoweringBase | inline |
| getMinFunctionAlignment() const | llvm::TargetLoweringBase | inline |
| getMinimumJumpTableDensity(bool OptForSize) const | llvm::TargetLoweringBase | |
| getMinStackArgumentAlignment() const | llvm::TargetLoweringBase | inline |
| getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const | llvm::TargetLowering | virtual |
| getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const | llvm::TargetLowering | inline |
| getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) const | llvm::AArch64TargetLowering | |
| getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const | llvm::TargetLoweringBase | inlinevirtual |
| getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| getOperationAction(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override | llvm::AArch64TargetLowering | virtual |
| getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override | llvm::AArch64TargetLowering | virtual |
| getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const | llvm::TargetLowering | virtual |
| getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const | llvm::TargetLoweringBase | inlinevirtual |
| getPointerTy(const DataLayout &DL, uint32_t AS=0) const override | llvm::AArch64TargetLowering | inlinevirtual |
| getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) const override | llvm::AArch64TargetLowering | virtual |
| getPreferredShiftAmountTy(LLT ShiftValueTy) const | llvm::TargetLoweringBase | inlinevirtual |
| getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const | llvm::TargetLoweringBase | virtual |
| getPreferredVectorAction(MVT VT) const override | llvm::AArch64TargetLowering | virtual |
| getPrefFunctionAlignment() const | llvm::TargetLoweringBase | inline |
| getPrefLoopAlignment(MachineLoop *ML=nullptr) const | llvm::TargetLoweringBase | virtual |
| getProgramPointerTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| getPromotedVTForPredicate(EVT VT) const | llvm::AArch64TargetLowering | |
| getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
| getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
| getRedZoneSize(const Function &F) const | llvm::AArch64TargetLowering | inline |
| getRegClassFor(MVT VT, bool isDivergent=false) const | llvm::TargetLoweringBase | inlinevirtual |
| getRegisterType(MVT VT) const | llvm::TargetLoweringBase | inline |
| getRegisterType(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| getRepRegClassCostFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getRepRegClassFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getRoundingControlRegisters() const override | llvm::AArch64TargetLowering | virtual |
| getSafeStackPointerLocation(IRBuilderBase &IRB) const override | llvm::AArch64TargetLowering | virtual |
| getScalarShiftAmountTy(const DataLayout &DL, EVT) const override | llvm::AArch64TargetLowering | virtual |
| getSchedulingPreference() const | llvm::TargetLoweringBase | inline |
| getSchedulingPreference(SDNode *) const | llvm::TargetLoweringBase | inlinevirtual |
| getScratchRegisters(CallingConv::ID CC) const override | llvm::AArch64TargetLowering | virtual |
| getSDagStackGuard(const Module &M) const override | llvm::AArch64TargetLowering | virtual |
| getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const | llvm::TargetLoweringBase | |
| getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
| getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
| getSSPStackGuardCheck(const Module &M) const override | llvm::AArch64TargetLowering | virtual |
| getStackPointerRegisterToSaveRestore() const | llvm::TargetLoweringBase | inline |
| getStackProbeSymbolName(const MachineFunction &MF) const | llvm::TargetLoweringBase | inlinevirtual |
| getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const | llvm::TargetLoweringBase | |
| getStrictFPOperationAction(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| getTargetConstantFromLoad(LoadSDNode *LD) const | llvm::TargetLowering | virtual |
| getTargetMachine() const | llvm::TargetLoweringBase | inline |
| getTargetMMOFlags(const Instruction &I) const override | llvm::AArch64TargetLowering | virtual |
| llvm::TargetLowering::getTargetMMOFlags(const MemSDNode &Node) const | llvm::TargetLoweringBase | inlinevirtual |
| getTargetNodeName(unsigned Opcode) const override | llvm::AArch64TargetLowering | virtual |
| getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override | llvm::AArch64TargetLowering | virtual |
| getTruncStoreAction(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| getTypeAction(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeAction(MVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeConversion(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | |
| getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const | llvm::TargetLowering | inlinevirtual |
| getTypeToExpandTo(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeToPromoteTo(unsigned Op, MVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeToTransformTo(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getVaListSizeInBits(const DataLayout &DL) const override | llvm::AArch64TargetLowering | virtual |
| getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
| getValueTypeActions() const | llvm::TargetLoweringBase | inline |
| getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const | llvm::TargetLowering | |
| getVectorIdxTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inlinevirtual |
| getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, EVT SubVecVT, SDValue Index) const | llvm::TargetLowering | |
| getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const | llvm::TargetLoweringBase | |
| getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override | llvm::AArch64TargetLowering | virtual |
| getVPExplicitVectorLengthTy() const | llvm::TargetLoweringBase | inlinevirtual |
| HandleByVal(CCState *, unsigned &, Align) const | llvm::TargetLowering | inlinevirtual |
| hasAndNot(SDValue Y) const override | llvm::AArch64TargetLowering | inlinevirtual |
| hasAndNotCompare(SDValue V) const override | llvm::AArch64TargetLowering | inlinevirtual |
| hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| hasBitTest(SDValue X, SDValue Y) const | llvm::TargetLoweringBase | inlinevirtual |
| hasExtractBitsInsn() const | llvm::TargetLoweringBase | inline |
| hasFastEqualityCompare(unsigned NumBits) const | llvm::TargetLoweringBase | inlinevirtual |
| hasInlineStackProbe(const MachineFunction &MF) const override | llvm::AArch64TargetLowering | virtual |
| hasMultipleConditionRegisters() const | llvm::TargetLoweringBase | inline |
| hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override | llvm::AArch64TargetLowering | virtual |
| hasStackProbeSymbol(const MachineFunction &MF) const | llvm::TargetLoweringBase | inlinevirtual |
| hasStandaloneRem(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| hasTargetDAGCombine(ISD::NodeType NT) const | llvm::TargetLoweringBase | inline |
| hasVectorBlend() const | llvm::TargetLoweringBase | inlinevirtual |
| IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const | llvm::TargetLowering | |
| initActions() | llvm::TargetLoweringBase | protected |
| initializeSplitCSR(MachineBasicBlock *Entry) const override | llvm::AArch64TargetLowering | virtual |
| insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override | llvm::AArch64TargetLowering | virtual |
| insertSSPDeclarations(Module &M) const override | llvm::AArch64TargetLowering | virtual |
| InstructionOpcodeToISD(unsigned Opcode) const | llvm::TargetLoweringBase | |
| isAllActivePredicate(SelectionDAG &DAG, SDValue N) const | llvm::AArch64TargetLowering | |
| isAtomicLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isBeneficialToExpandPowI(int64_t Exponent, bool OptForSize) const | llvm::TargetLoweringBase | inline |
| isBinOp(unsigned Opcode) const | llvm::TargetLoweringBase | inlinevirtual |
| isCheapToSpeculateCtlz(Type *) const override | llvm::AArch64TargetLowering | inlinevirtual |
| isCheapToSpeculateCttz(Type *) const override | llvm::AArch64TargetLowering | inlinevirtual |
| isCommutativeBinOp(unsigned Opcode) const | llvm::TargetLoweringBase | inlinevirtual |
| isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override | llvm::AArch64TargetLowering | virtual |
| isComplexDeinterleavingSupported() const override | llvm::AArch64TargetLowering | virtual |
| isCondCodeLegal(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
| isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
| isConstFalseVal(SDValue N) const | llvm::TargetLowering | |
| isConstTrueVal(SDValue N) const | llvm::TargetLowering | |
| isCtlzFast() const | llvm::TargetLoweringBase | inlinevirtual |
| isCtpopFast(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const | llvm::TargetLowering | inlinevirtual |
| isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override | llvm::AArch64TargetLowering | virtual |
| llvm::TargetLowering::isDesirableToCommuteWithShift(const MachineInstr &MI, bool IsAfterLegal) const | llvm::TargetLowering | inlinevirtual |
| isDesirableToCommuteXorWithShift(const SDNode *N) const override | llvm::AArch64TargetLowering | virtual |
| IsDesirableToPromoteOp(SDValue, EVT &) const | llvm::TargetLowering | inlinevirtual |
| isDesirableToPullExtFromShl(const MachineInstr &MI) const override | llvm::AArch64TargetLowering | inlinevirtual |
| isDesirableToTransformToIntegerOp(unsigned, EVT) const | llvm::TargetLowering | inlinevirtual |
| isEqualityCmpFoldedWithSignedCmp() const | llvm::TargetLoweringBase | inlinevirtual |
| isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const | llvm::TargetLowering | |
| isExtFree(const Instruction *I) const | llvm::TargetLoweringBase | inline |
| isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override | llvm::AArch64TargetLowering | virtual |
| isExtractVecEltCheap(EVT VT, unsigned Index) const | llvm::TargetLoweringBase | inlinevirtual |
| isFAbsFree(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFMADLegal(const MachineInstr &MI, LLT Ty) const | llvm::TargetLoweringBase | inlinevirtual |
| isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const | llvm::TargetLoweringBase | inlinevirtual |
| isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override | llvm::AArch64TargetLowering | virtual |
| llvm::TargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, LLT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFNegFree(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const | llvm::TargetLoweringBase | inlinevirtual |
| isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFPExtFree(EVT DestVT, EVT SrcVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override | llvm::AArch64TargetLowering | virtual |
| isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const | llvm::TargetLoweringBase | virtual |
| isFsqrtCheap(SDValue X, SelectionDAG &DAG) const | llvm::TargetLoweringBase | inlinevirtual |
| isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const | llvm::TargetLowering | virtual |
| isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const | llvm::TargetLowering | virtual |
| isIndexedLoadLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
| isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
| isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
| isIndexedStoreLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
| isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const | llvm::TargetLowering | inlinevirtual |
| isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const | llvm::TargetLowering | |
| isIntDivCheap(EVT VT, AttributeList Attr) const override | llvm::AArch64TargetLowering | virtual |
| isJumpExpensive() const | llvm::TargetLoweringBase | inline |
| isJumpTableRelative() const | llvm::TargetLoweringBase | virtual |
| isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| isLegalAddImmediate(int64_t) const override | llvm::AArch64TargetLowering | virtual |
| isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override | llvm::AArch64TargetLowering | virtual |
| isLegalAddScalableImmediate(int64_t) const override | llvm::AArch64TargetLowering | virtual |
| isLegalICmpImmediate(int64_t) const override | llvm::AArch64TargetLowering | virtual |
| isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const | llvm::AArch64TargetLowering | |
| isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const | llvm::TargetLoweringBase | protected |
| isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const | llvm::TargetLoweringBase | inlinevirtual |
| isLegalStoreImmediate(int64_t Value) const | llvm::TargetLoweringBase | inlinevirtual |
| isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const | llvm::TargetLoweringBase | virtual |
| isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override | llvm::AArch64TargetLowering | virtual |
| isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override | llvm::AArch64TargetLowering | virtual |
| isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const | llvm::TargetLoweringBase | inlinevirtual |
| isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override | llvm::AArch64TargetLowering | virtual |
| isOperationCustom(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationExpand(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationLegal(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const | llvm::TargetLoweringBase | inline |
| isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const | llvm::TargetLoweringBase | inline |
| isOperationLegalOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const | llvm::TargetLoweringBase | inline |
| isOpSuitableForLDPSTP(const Instruction *I) const | llvm::AArch64TargetLowering | |
| isOpSuitableForLSE128(const Instruction *I) const | llvm::AArch64TargetLowering | |
| isOpSuitableForRCPC3(const Instruction *I) const | llvm::AArch64TargetLowering | |
| isPaddedAtMostSignificantBitsWhenStored(EVT VT) const | llvm::TargetLoweringBase | inline |
| isPositionIndependent() const | llvm::TargetLowering | |
| isPredictableSelectExpensive() const | llvm::TargetLoweringBase | inline |
| isProfitableToCombineMinNumMaxNum(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| isProfitableToHoist(Instruction *I) const override | llvm::AArch64TargetLowering | virtual |
| isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override | llvm::AArch64TargetLowering | virtual |
| llvm::TargetLowering::isReassocProfitable(MachineRegisterInfo &MRI, Register N0, Register N1) const | llvm::TargetLowering | inlinevirtual |
| isSafeMemOpType(MVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isSDNodeAlwaysUniform(const SDNode *N) const | llvm::TargetLowering | inlinevirtual |
| isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const | llvm::TargetLowering | inlinevirtual |
| isSelectSupported(SelectSupportKind) const | llvm::TargetLoweringBase | inlinevirtual |
| isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const | llvm::TargetLoweringBase | inlinevirtual |
| isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| isSlowDivBypassed() const | llvm::TargetLoweringBase | inline |
| isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const | llvm::TargetLoweringBase | inlinevirtual |
| IsStrictFPEnabled | llvm::TargetLoweringBase | protected |
| isStrictFPEnabled() const | llvm::TargetLoweringBase | inline |
| isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const | llvm::TargetLoweringBase | virtual |
| isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const | llvm::TargetLoweringBase | inlinevirtual |
| isTruncateFree(Type *Ty1, Type *Ty2) const override | llvm::AArch64TargetLowering | virtual |
| isTruncateFree(EVT VT1, EVT VT2) const override | llvm::AArch64TargetLowering | virtual |
| llvm::TargetLowering::isTruncateFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) const | llvm::TargetLoweringBase | inlinevirtual |
| llvm::TargetLowering::isTruncateFree(SDValue Val, EVT VT2) const | llvm::TargetLoweringBase | inlinevirtual |
| isTruncStoreLegal(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isTypeDesirableForOp(unsigned Opc, EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| isTypeLegal(EVT VT) const | llvm::TargetLoweringBase | inline |
| isVectorClearMaskLegal(ArrayRef< int > M, EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| isVScaleKnownToBeAPowerOfTwo() const override | llvm::AArch64TargetLowering | inlinevirtual |
| isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode, EVT) const | llvm::TargetLowering | inlinevirtual |
| isZExtFree(Type *Ty1, Type *Ty2) const override | llvm::AArch64TargetLowering | virtual |
| isZExtFree(EVT VT1, EVT VT2) const override | llvm::AArch64TargetLowering | virtual |
| isZExtFree(SDValue Val, EVT VT2) const override | llvm::AArch64TargetLowering | virtual |
| llvm::TargetLowering::isZExtFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) const | llvm::TargetLoweringBase | inlinevirtual |
| joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const | llvm::TargetLowering | inlinevirtual |
| Legal enum value | llvm::TargetLoweringBase | |
| LegalizeAction enum name | llvm::TargetLoweringBase | |
| LegalizeKind typedef | llvm::TargetLoweringBase | |
| LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, SDValue Mask, SDValue EVL, bool &NeedInvert, const SDLoc &dl, SDValue &Chain, bool IsSignaling=false) const | llvm::TargetLowering | |
| LegalizeTypeAction enum name | llvm::TargetLoweringBase | |
| LibCall enum value | llvm::TargetLoweringBase | |
| LowerCallTo(CallLoweringInfo &CLI) const | llvm::TargetLowering | |
| lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const | llvm::TargetLowering | |
| LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const | llvm::TargetLowering | inlinevirtual |
| lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, LoadInst *LI, SmallVectorImpl< Instruction * > &DeadInsts) const override | llvm::AArch64TargetLowering | virtual |
| lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const | llvm::TargetLoweringBase | inlinevirtual |
| lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override | llvm::AArch64TargetLowering | virtual |
| lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override | llvm::AArch64TargetLowering | virtual |
| lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI, SmallVectorImpl< Instruction * > &DeadInsts) const override | llvm::AArch64TargetLowering | virtual |
| LowerOperation(SDValue Op, SelectionDAG &DAG) const override | llvm::AArch64TargetLowering | virtual |
| LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const | llvm::TargetLowering | |
| markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const | llvm::TargetLoweringBase | inlinevirtual |
| MaxGluedStoresPerMemcpy | llvm::TargetLoweringBase | protected |
| MaxLoadsPerMemcmp | llvm::TargetLoweringBase | protected |
| MaxLoadsPerMemcmpOptSize | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemcpy | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemcpyOptSize | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemmove | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemmoveOptSize | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemset | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemsetOptSize | llvm::TargetLoweringBase | protected |
| mergeStoresAfterLegalization(EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| MulExpansionKind enum name | llvm::TargetLoweringBase | |
| needsFixedCatchObjects() const override | llvm::AArch64TargetLowering | virtual |
| NegatibleCost enum name | llvm::TargetLoweringBase | |
| None enum value | llvm::TargetLoweringBase | |
| NotAnd enum value | llvm::TargetLoweringBase | |
| operator=(const TargetLowering &)=delete | llvm::TargetLowering | |
| llvm::TargetLoweringBase::operator=(const TargetLoweringBase &)=delete | llvm::TargetLoweringBase | |
| optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override | llvm::AArch64TargetLowering | virtual |
| optimizeFMulOrFDivAsShiftAddBitcast(SDNode *N, SDValue FPConst, SDValue IntPow2) const | llvm::TargetLoweringBase | inlinevirtual |
| parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const | llvm::TargetLowering | |
| ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const | llvm::TargetLowering | virtual |
| PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override | llvm::AArch64TargetLowering | virtual |
| PredictableSelectIsExpensive | llvm::TargetLoweringBase | protected |
| preferABDSToABSWithNSW(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| preferedOpcodeForCmpEqPiecesOfOperand(EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) const | llvm::TargetLoweringBase | inlinevirtual |
| preferIncOfAddToSubOfNot(EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override | llvm::AArch64TargetLowering | virtual |
| preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) const | llvm::TargetLoweringBase | inlinevirtual |
| preferZeroCompareBranch() const | llvm::TargetLoweringBase | inlinevirtual |
| prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const | llvm::TargetLowering | inlinevirtual |
| Promote enum value | llvm::TargetLoweringBase | |
| promoteTargetBoolean(SelectionDAG &DAG, SDValue Bool, EVT ValVT) const | llvm::TargetLoweringBase | inline |
| rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| ReciprocalEstimate enum name | llvm::TargetLoweringBase | |
| ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const | llvm::AArch64TargetLowering | |
| reduceSelectOfFPConstantLoads(EVT CmpOpVT) const | llvm::TargetLoweringBase | inlinevirtual |
| requiresUniformRegister(MachineFunction &MF, const Value *) const | llvm::TargetLoweringBase | inlinevirtual |
| ScalarCondVectorVal enum value | llvm::TargetLoweringBase | |
| scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const | llvm::TargetLowering | |
| scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const | llvm::TargetLowering | |
| ScalarValSelect enum value | llvm::TargetLoweringBase | |
| SelectSupportKind enum name | llvm::TargetLoweringBase | |
| setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setBooleanContents(BooleanContent Ty) | llvm::TargetLoweringBase | inlineprotected |
| setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) | llvm::TargetLoweringBase | inlineprotected |
| setBooleanVectorContents(BooleanContent Ty) | llvm::TargetLoweringBase | inlineprotected |
| setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) | llvm::TargetLoweringBase | inline |
| setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setCondCodeAction(ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setHasExtractBitsInsn(bool hasExtractInsn=true) | llvm::TargetLoweringBase | inlineprotected |
| setHasMultipleConditionRegisters(bool hasManyRegs=true) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedLoadAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedStoreAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setJumpIsExpensive(bool isExpensive=true) | llvm::TargetLoweringBase | protected |
| setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) | llvm::TargetLoweringBase | inline |
| setLibcallName(RTLIB::Libcall Call, const char *Name) | llvm::TargetLoweringBase | inline |
| setLibcallName(ArrayRef< RTLIB::Libcall > Calls, const char *Name) | llvm::TargetLoweringBase | inline |
| setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
| setMaxBytesForAlignment(unsigned MaxBytes) | llvm::TargetLoweringBase | inlineprotected |
| setMaxDivRemBitWidthSupported(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
| setMaximumJumpTableSize(unsigned) | llvm::TargetLoweringBase | protected |
| setMaxLargeFPConvertBitWidthSupported(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
| setMinCmpXchgSizeInBits(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
| setMinFunctionAlignment(Align Alignment) | llvm::TargetLoweringBase | inlineprotected |
| setMinimumJumpTableEntries(unsigned Val) | llvm::TargetLoweringBase | protected |
| setMinStackArgumentAlignment(Align Alignment) | llvm::TargetLoweringBase | inlineprotected |
| setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setOperationAction(ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) | llvm::TargetLoweringBase | inlineprotected |
| setOperationPromotedToType(ArrayRef< unsigned > Ops, MVT OrigVT, MVT DestVT) | llvm::TargetLoweringBase | inlineprotected |
| setPrefFunctionAlignment(Align Alignment) | llvm::TargetLoweringBase | inlineprotected |
| setPrefLoopAlignment(Align Alignment) | llvm::TargetLoweringBase | inlineprotected |
| setSchedulingPreference(Sched::Preference Pref) | llvm::TargetLoweringBase | inlineprotected |
| setStackPointerRegisterToSaveRestore(Register R) | llvm::TargetLoweringBase | inlineprotected |
| setSupportsUnalignedAtomics(bool UnalignedSupported) | llvm::TargetLoweringBase | inlineprotected |
| setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs) | llvm::TargetLoweringBase | inlineprotected |
| setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const | llvm::TargetLoweringBase | inlinevirtual |
| ShiftLegalizationStrategy enum name | llvm::TargetLoweringBase | |
| shouldAlignPointerArgs(CallInst *, unsigned &, Align &) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldAvoidTransformToShift(EVT VT, unsigned Amount) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldCastAtomicLoadInIR(LoadInst *LI) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldCastAtomicRMWIInIR(AtomicRMWInst *RMWI) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldCastAtomicStoreInIR(StoreInst *SI) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldConsiderGEPOffsetSplit() const override | llvm::AArch64TargetLowering | virtual |
| shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override | llvm::AArch64TargetLowering | virtual |
| shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| shouldConvertPhiType(Type *From, Type *To) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldConvertSplatType(ShuffleVectorInst *SVI) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override | llvm::AArch64TargetLowering | virtual |
| shouldExpandAtomicLoadInIR(LoadInst *LI) const override | llvm::AArch64TargetLowering | virtual |
| shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override | llvm::AArch64TargetLowering | virtual |
| shouldExpandAtomicStoreInIR(StoreInst *SI) const override | llvm::AArch64TargetLowering | virtual |
| shouldExpandCmpUsingSelects(EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| shouldExpandCttzElements(EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override | llvm::AArch64TargetLowering | virtual |
| shouldExpandGetVectorLength(EVT CountVT, unsigned VF, bool IsScalable) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandPartialReductionIntrinsic(const IntrinsicInst *I) const override | llvm::AArch64TargetLowering | virtual |
| shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const override | llvm::AArch64TargetLowering | virtual |
| shouldExtendTypeInLibCall(EVT Type) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override | llvm::AArch64TargetLowering | virtual |
| shouldFoldMaskToVariableShiftPair(SDValue X) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override | llvm::AArch64TargetLowering | virtual |
| shouldFoldSelectWithSingleBitTest(EVT VT, const APInt &AndMask) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override | llvm::AArch64TargetLowering | inlinevirtual |
| shouldInsertFencesForAtomic(const Instruction *I) const override | llvm::AArch64TargetLowering | virtual |
| shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override | llvm::AArch64TargetLowering | virtual |
| shouldKeepZExtForFP16Conv() const | llvm::TargetLoweringBase | inlinevirtual |
| shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override | llvm::AArch64TargetLowering | virtual |
| shouldReassociateReduction(unsigned RedOpc, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override | llvm::AArch64TargetLowering | virtual |
| shouldRemoveRedundantExtend(SDValue Op) const override | llvm::AArch64TargetLowering | virtual |
| ShouldShrinkFPConstant(EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldSimplifyDemandedVectorElts(SDValue Op, const TargetLoweringOpt &TLO) const | llvm::TargetLowering | inlinevirtual |
| shouldSplatInsEltVarIndex(EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const | llvm::TargetLowering | inlinevirtual |
| shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override | llvm::AArch64TargetLowering | inlinevirtual |
| shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const | llvm::TargetLoweringBase | inlinevirtual |
| ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const | llvm::TargetLowering | |
| ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, TargetLoweringOpt &TLO) const | llvm::TargetLowering | |
| ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &DemandedBits, TargetLoweringOpt &TLO) const | llvm::TargetLowering | |
| signExtendConstant(const ConstantInt *C) const | llvm::TargetLoweringBase | inlinevirtual |
| SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const | llvm::TargetLowering | |
| SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const | llvm::TargetLowering | |
| SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, DAGCombinerInfo &DCI) const | llvm::TargetLowering | |
| SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, DAGCombinerInfo &DCI) const | llvm::TargetLowering | |
| SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const | llvm::TargetLowering | |
| SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, DAGCombinerInfo &DCI) const | llvm::TargetLowering | |
| SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | |
| SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | |
| SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const | llvm::TargetLowering | virtual |
| SimplifyMultipleUseDemandedVectorElts(SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | |
| SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const | llvm::TargetLowering | |
| softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) const | llvm::TargetLowering | |
| softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling=false) const | llvm::TargetLowering | |
| splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const | llvm::TargetLowering | inlinevirtual |
| storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const | llvm::TargetLoweringBase | inlinevirtual |
| supportKCFIBundles() const override | llvm::AArch64TargetLowering | inlinevirtual |
| supportPtrAuthBundles() const override | llvm::AArch64TargetLowering | inlinevirtual |
| supportSplitCSR(MachineFunction *MF) const override | llvm::AArch64TargetLowering | inlinevirtual |
| supportsUnalignedAtomics() const | llvm::TargetLoweringBase | inline |
| supportSwiftError() const override | llvm::AArch64TargetLowering | inlinevirtual |
| TargetLowering(const TargetLowering &)=delete | llvm::TargetLowering | |
| TargetLowering(const TargetMachine &TM) | llvm::TargetLowering | explicit |
| TargetLoweringBase(const TargetMachine &TM) | llvm::TargetLoweringBase | explicit |
| TargetLoweringBase(const TargetLoweringBase &)=delete | llvm::TargetLoweringBase | |
| targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override | llvm::AArch64TargetLowering | virtual |
| TypeExpandFloat enum value | llvm::TargetLoweringBase | |
| TypeExpandInteger enum value | llvm::TargetLoweringBase | |
| TypeLegal enum value | llvm::TargetLoweringBase | |
| TypePromoteFloat enum value | llvm::TargetLoweringBase | |
| TypePromoteInteger enum value | llvm::TargetLoweringBase | |
| TypeScalarizeScalableVector enum value | llvm::TargetLoweringBase | |
| TypeScalarizeVector enum value | llvm::TargetLoweringBase | |
| TypeSoftenFloat enum value | llvm::TargetLoweringBase | |
| TypeSoftPromoteHalf enum value | llvm::TargetLoweringBase | |
| TypeSplitVector enum value | llvm::TargetLoweringBase | |
| TypeWidenVector enum value | llvm::TargetLoweringBase | |
| UndefinedBooleanContent enum value | llvm::TargetLoweringBase | |
| Unspecified enum value | llvm::TargetLoweringBase | |
| unwrapAddress(SDValue N) const | llvm::TargetLowering | inlinevirtual |
| useFPRegsForHalfType() const | llvm::TargetLoweringBase | inlinevirtual |
| useLoadStackGuardNode(const Module &M) const override | llvm::AArch64TargetLowering | virtual |
| useSoftFloat() const | llvm::TargetLoweringBase | inlinevirtual |
| useStackGuardXorFP() const | llvm::TargetLoweringBase | inlinevirtual |
| useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON=false) const | llvm::AArch64TargetLowering | |
| VectorMaskSelect enum value | llvm::TargetLoweringBase | |
| verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const | llvm::TargetLowering | |
| verifyTargetSDNode(const SDNode *N) const override | llvm::AArch64TargetLowering | virtual |
| visitMaskedLoad(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue &NewLoad, SDValue Ptr, SDValue PassThru, SDValue Mask) const | llvm::TargetLowering | inlinevirtual |
| visitMaskedStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue Ptr, SDValue Val, SDValue Mask) const | llvm::TargetLowering | inlinevirtual |
| ZeroOrNegativeOneBooleanContent enum value | llvm::TargetLoweringBase | |
| ZeroOrOneBooleanContent enum value | llvm::TargetLoweringBase | |
| ~TargetLoweringBase()=default | llvm::TargetLoweringBase | virtual |
1.9.6