#include "Target/AArch64/AArch64ISelLowering.h"
Public Member Functions | |
| AArch64TargetLowering (const TargetMachine &TM, const AArch64Subtarget &STI) | |
| bool | isReassocProfitable (SelectionDAG &DAG, SDValue N0, SDValue N1) const override |
| Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y), c1) where N0 is (op x, c1) and N1 is y. | |
| CCAssignFn * | CCAssignFnForCall (CallingConv::ID CC, bool IsVarArg) const |
| Selects the correct CCAssignFn for a given CallingConvention value. | |
| CCAssignFn * | CCAssignFnForReturn (CallingConv::ID CC) const |
| Selects the correct CCAssignFn for a given CallingConvention value. | |
| void | computeKnownBitsForTargetNode (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override |
| Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. | |
| unsigned | ComputeNumSignBitsForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override |
| This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner. | |
| MVT | getPointerTy (const DataLayout &DL, uint32_t AS=0) const override |
| Return the pointer type for the given address space, defaults to the pointer type from the data layout. | |
| bool | targetShrinkDemandedConstant (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override |
| MVT | getScalarShiftAmountTy (const DataLayout &DL, EVT) const override |
| Return the type to use for a scalar shift opcode, given the shifted amount type. | |
| bool | allowsMisalignedMemoryAccesses (EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override |
| Returns true if the target allows unaligned memory accesses of the specified type. | |
| bool | allowsMisalignedMemoryAccesses (LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast=nullptr) const override |
| LLT variant. | |
| SDValue | LowerOperation (SDValue Op, SelectionDAG &DAG) const override |
| Provide custom lowering hooks for some operations. | |
| const char * | getTargetNodeName (unsigned Opcode) const override |
| This method returns the name of a target specific DAG node. | |
| SDValue | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override |
| This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. | |
| FastISel * | createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override |
| This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. | |
| bool | isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const override |
| Return true if folding a constant offset with the given GlobalAddress is legal. | |
| bool | isFPImmLegal (const APFloat &Imm, EVT VT, bool ForCodeSize) const override |
| Returns true if the target can instruction select the specified FP immediate natively. | |
| bool | isShuffleMaskLegal (ArrayRef< int > M, EVT VT) const override |
| Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded. | |
| bool | isVectorClearMaskLegal (ArrayRef< int > M, EVT VT) const override |
| Similar to isShuffleMaskLegal. | |
| EVT | getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const override |
| Return the ISD::SETCC ValueType. | |
| SDValue | ReconstructShuffle (SDValue Op, SelectionDAG &DAG) const |
| MachineBasicBlock * | EmitF128CSEL (MachineInstr &MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitLoweredCatchRet (MachineInstr &MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitDynamicProbedAlloc (MachineInstr &MI, MachineBasicBlock *MBB) const |
| MachineBasicBlock * | EmitTileLoad (unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitFill (MachineInstr &MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitZAInstr (unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitZTInstr (MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, bool Op0IsDef) const |
| MachineBasicBlock * | EmitZero (MachineInstr &MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitInitTPIDR2Object (MachineInstr &MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitAllocateZABuffer (MachineInstr &MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitInstrWithCustomInserter (MachineInstr &MI, MachineBasicBlock *MBB) const override |
| This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. | |
| bool | getTgtMemIntrinsic (IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override |
| getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes. | |
| bool | shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override |
| Return true if it is profitable to reduce a load to a smaller type. | |
| bool | shouldRemoveRedundantExtend (SDValue Op) const override |
| Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant, and use x directly. | |
| bool | isTruncateFree (Type *Ty1, Type *Ty2) const override |
| Return true if it's free to truncate a value of type FromTy to type ToTy. | |
| bool | isTruncateFree (EVT VT1, EVT VT2) const override |
| bool | isProfitableToHoist (Instruction *I) const override |
| Check if it is profitable to hoist instruction in then/else to if. | |
| bool | isZExtFree (Type *Ty1, Type *Ty2) const override |
| Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. | |
| bool | isZExtFree (EVT VT1, EVT VT2) const override |
| bool | isZExtFree (SDValue Val, EVT VT2) const override |
| Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). | |
| bool | shouldSinkOperands (Instruction *I, SmallVectorImpl< Use * > &Ops) const override |
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded into a target instruction, e.g. | |
| bool | optimizeExtendOrTruncateConversion (Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override |
| Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target. | |
| bool | hasPairedLoad (EVT LoadedType, Align &RequiredAligment) const override |
| Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. | |
| unsigned | getMaxSupportedInterleaveFactor () const override |
| Get the maximum supported factor for interleaved memory accesses. | |
| bool | lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override |
| Lower an interleaved load into a ldN intrinsic. | |
| bool | lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override |
| Lower an interleaved store into a stN intrinsic. | |
| bool | lowerDeinterleaveIntrinsicToLoad (IntrinsicInst *DI, LoadInst *LI, SmallVectorImpl< Instruction * > &DeadInsts) const override |
| Lower a deinterleave intrinsic to a target specific load intrinsic. | |
| bool | lowerInterleaveIntrinsicToStore (IntrinsicInst *II, StoreInst *SI, SmallVectorImpl< Instruction * > &DeadInsts) const override |
| Lower an interleave intrinsic to a target specific store intrinsic. | |
| bool | isLegalAddImmediate (int64_t) const override |
| Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. | |
| bool | isLegalAddScalableImmediate (int64_t) const override |
| Return true if adding the specified scalable immediate is legal, that is the target has add instructions which can add a register with the immediate (multiplied by vscale) without having to materialize the immediate into a register. | |
| bool | isLegalICmpImmediate (int64_t) const override |
| Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. | |
| bool | isMulAddWithConstProfitable (SDValue AddNode, SDValue ConstNode) const override |
| Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2). | |
| bool | shouldConsiderGEPOffsetSplit () const override |
| EVT | getOptimalMemOpType (const MemOp &Op, const AttributeList &FuncAttributes) const override |
| Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. | |
| LLT | getOptimalMemOpLLT (const MemOp &Op, const AttributeList &FuncAttributes) const override |
| LLT returning variant. | |
| bool | isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override |
| Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. | |
| int64_t | getPreferredLargeGEPBaseOffset (int64_t MinOffset, int64_t MaxOffset) const override |
| Return the prefered common base offset. | |
| bool | isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, EVT VT) const override |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. | |
| bool | isFMAFasterThanFMulAndFAdd (const Function &F, Type *Ty) const override |
| IR version. | |
| bool | generateFMAsInMachineCombiner (EVT VT, CodeGenOptLevel OptLevel) const override |
| bool | isTypeDesirableForOp (unsigned Opc, EVT VT) const override |
| Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. | |
| const MCPhysReg * | getScratchRegisters (CallingConv::ID CC) const override |
| Returns a 0 terminated array of registers that can be safely used as scratch registers. | |
| ArrayRef< MCPhysReg > | getRoundingControlRegisters () const override |
| Returns a 0 terminated array of rounding control registers that can be attached into strict FP call. | |
| bool | isDesirableToCommuteWithShift (const SDNode *N, CombineLevel Level) const override |
| Returns false if N is a bit extraction pattern of (X >> C) & Mask. | |
| bool | isDesirableToPullExtFromShl (const MachineInstr &MI) const override |
| GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x), y => zext (shl x, y) | |
| bool | isDesirableToCommuteXorWithShift (const SDNode *N) const override |
| Returns false if N is a bit extraction pattern of (X >> C) & Mask. | |
| bool | shouldFoldConstantShiftPairToMask (const SDNode *N, CombineLevel Level) const override |
| Return true if it is profitable to fold a pair of shifts into a mask. | |
| bool | shouldFoldSelectWithIdentityConstant (unsigned BinOpcode, EVT VT) const override |
| Return true if pulling a binary operation into a select with an identity constant is profitable. | |
| bool | shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override |
| Returns true if it is beneficial to convert a load of a constant to just the constant itself. | |
| bool | isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const override |
| Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index. | |
| bool | shouldFormOverflowOp (unsigned Opcode, EVT VT, bool MathUsed) const override |
| Try to convert math with an overflow comparison into the corresponding DAG node operation. | |
| Value * | emitLoadLinked (IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override |
| Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. | |
| Value * | emitStoreConditional (IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override |
| Perform a store-conditional operation to Addr. | |
| void | emitAtomicCmpXchgNoStoreLLBalance (IRBuilderBase &Builder) const override |
| bool | isOpSuitableForLDPSTP (const Instruction *I) const |
| bool | isOpSuitableForLSE128 (const Instruction *I) const |
| bool | isOpSuitableForRCPC3 (const Instruction *I) const |
| bool | shouldInsertFencesForAtomic (const Instruction *I) const override |
| Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. | |
| bool | shouldInsertTrailingFenceForAtomicStore (const Instruction *I) const override |
| Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering for this atomic. | |
| TargetLoweringBase::AtomicExpansionKind | shouldExpandAtomicLoadInIR (LoadInst *LI) const override |
| Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. | |
| TargetLoweringBase::AtomicExpansionKind | shouldExpandAtomicStoreInIR (StoreInst *SI) const override |
| Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into. | |
| TargetLoweringBase::AtomicExpansionKind | shouldExpandAtomicRMWInIR (AtomicRMWInst *AI) const override |
| Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. | |
| TargetLoweringBase::AtomicExpansionKind | shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const override |
| Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass. | |
| bool | useLoadStackGuardNode () const override |
| If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. | |
| TargetLoweringBase::LegalizeTypeAction | getPreferredVectorAction (MVT VT) const override |
| Return the preferred vector type legalization action. | |
| Value * | getIRStackGuard (IRBuilderBase &IRB) const override |
| If the target has a standard location for the stack protector cookie, returns the address of that location. | |
| void | insertSSPDeclarations (Module &M) const override |
| Inserts necessary declarations for SSP (stack protection) purpose. | |
| Value * | getSDagStackGuard (const Module &M) const override |
| Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. | |
| Function * | getSSPStackGuardCheck (const Module &M) const override |
| If the target has a standard stack protection check function that performs validation and error handling, returns the function. | |
| Value * | getSafeStackPointerLocation (IRBuilderBase &IRB) const override |
| If the target has a standard location for the unsafe stack pointer, returns the address of that location. | |
| Register | getExceptionPointerRegister (const Constant *PersonalityFn) const override |
| If a physical register, this returns the register that receives the exception address on entry to an EH pad. | |
| Register | getExceptionSelectorRegister (const Constant *PersonalityFn) const override |
| If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. | |
| bool | isIntDivCheap (EVT VT, AttributeList Attr) const override |
| Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. | |
| bool | canMergeStoresTo (unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override |
| Returns if it's reasonable to merge stores to MemVT size. | |
| bool | isCheapToSpeculateCttz (Type *) const override |
| Return true if it is cheap to speculate a call to intrinsic cttz. | |
| bool | isCheapToSpeculateCtlz (Type *) const override |
| Return true if it is cheap to speculate a call to intrinsic ctlz. | |
| bool | isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const override |
| Return if the target supports combining a chain like: | |
| bool | hasAndNotCompare (SDValue V) const override |
| Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. | |
| bool | hasAndNot (SDValue Y) const override |
| Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. | |
| bool | shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd (SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override |
| Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in. | |
| ShiftLegalizationStrategy | preferredShiftLegalizationStrategy (SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override |
| bool | shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const override |
| Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform. | |
| bool | preferIncOfAddToSubOfNot (EVT VT) const override |
| These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical. | |
| bool | shouldConvertFpToSat (unsigned Op, EVT FPVT, EVT VT) const override |
| Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns. | |
| bool | shouldExpandCmpUsingSelects () const override |
| Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean types. | |
| bool | isComplexDeinterleavingSupported () const override |
| Does this target support complex deinterleaving. | |
| bool | isComplexDeinterleavingOperationSupported (ComplexDeinterleavingOperation Operation, Type *Ty) const override |
| Does this target support complex deinterleaving with the given operation and type. | |
| Value * | createComplexDeinterleavingIR (IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override |
| Create the IR node for the given complex deinterleaving operation. | |
| bool | supportSplitCSR (MachineFunction *MF) const override |
| Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies. | |
| void | initializeSplitCSR (MachineBasicBlock *Entry) const override |
| Perform necessary initialization to handle a subset of CSRs explicitly via copies. | |
| void | insertCopiesSplitCSR (MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override |
| Insert explicit copies in entry and exit blocks. | |
| bool | supportSwiftError () const override |
| Return true if the target supports swifterror attribute. | |
| bool | supportPtrAuthBundles () const override |
| Return true if the target supports ptrauth operand bundles. | |
| bool | supportKCFIBundles () const override |
| Return true if the target supports kcfi operand bundles. | |
| MachineInstr * | EmitKCFICheck (MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override |
| bool | enableAggressiveFMAFusion (EVT VT) const override |
| Enable aggressive FMA fusion on targets that want it. | |
| unsigned | getVaListSizeInBits (const DataLayout &DL) const override |
| Returns the size of the platform's va_list object. | |
| bool | isLegalInterleavedAccessType (VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const |
Returns true if VecTy is a legal interleaved access type. | |
| unsigned | getNumInterleavedAccesses (VectorType *VecTy, const DataLayout &DL, bool UseScalable) const |
| Returns the number of interleaved accesses that will be generated when lowering accesses of the given type. | |
| MachineMemOperand::Flags | getTargetMMOFlags (const Instruction &I) const override |
| This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them. | |
| bool | functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override |
| For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers. | |
| bool | needsFixedCatchObjects () const override |
| Used for exception handling on Win64. | |
| bool | fallBackToDAGISel (const Instruction &Inst) const override |
| bool | mergeStoresAfterLegalization (EVT VT) const override |
| SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR. | |
| unsigned | getRedZoneSize (const Function &F) const |
| bool | isAllActivePredicate (SelectionDAG &DAG, SDValue N) const |
| EVT | getPromotedVTForPredicate (EVT VT) const |
| EVT | getAsmOperandValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override |
| bool | shouldExpandGetActiveLaneMask (EVT VT, EVT OpVT) const override |
| Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder. | |
| bool | shouldExpandCttzElements (EVT VT) const override |
| Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in SelectionDAGBuilder. | |
| SDValue | changeStreamingMode (SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InGlue, unsigned Condition, SDValue PStateSM=SDValue()) const |
| If a change in streaming mode is required on entry to/return from a function call it emits and returns the corresponding SMSTART or SMSTOP node. | |
| bool | isVScaleKnownToBeAPowerOfTwo () const override |
| Return true only if vscale must be a power of two. | |
| bool | useSVEForFixedLengthVectorVT (EVT VT, bool OverrideNEON=false) const |
| MVT | getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const override |
| Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. | |
| unsigned | getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const override |
| Certain targets require unusual breakdowns of certain types. | |
| unsigned | getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override |
| Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. | |
| bool | hasInlineStackProbe (const MachineFunction &MF) const override |
| True if stack clash protection is enabled for this functions. | |
| void | verifyTargetSDNode (const SDNode *N) const override |
| Check the given SDNode. Aborts if it is invalid. | |
 Public Member Functions inherited from llvm::TargetLowering | |
| TargetLowering (const TargetLowering &)=delete | |
| TargetLowering & | operator= (const TargetLowering &)=delete |
| TargetLowering (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. | |
| bool | isPositionIndependent () const |
| virtual bool | isSDNodeSourceOfDivergence (const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const |
| virtual bool | isReassocProfitable (SelectionDAG &DAG, SDValue N0, SDValue N1) const |
| virtual bool | isReassocProfitable (MachineRegisterInfo &MRI, Register N0, Register N1) const |
| virtual bool | isSDNodeAlwaysUniform (const SDNode *N) const |
| virtual bool | getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const |
| Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address. | |
| virtual bool | getPostIndexedAddressParts (SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const |
| Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store. | |
| virtual bool | isIndexingLegal (MachineInstr &MI, Register Base, Register Offset, bool IsPre, MachineRegisterInfo &MRI) const |
| Returns true if the specified base+offset is a legal indexed addressing mode for this target. | |
| virtual unsigned | getJumpTableEncoding () const |
| Return the entry encoding for a jump table in the current function. | |
| virtual MVT | getJumpTableRegTy (const DataLayout &DL) const |
| virtual const MCExpr * | LowerCustomJumpTableEntry (const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const |
| virtual SDValue | getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const |
| Returns relocation base for the given PIC jumptable. | |
| virtual const MCExpr * | getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const |
| This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr. | |
| virtual bool | isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const |
| Return true if folding a constant offset with the given GlobalAddress is legal. | |
| virtual bool | isInlineAsmTargetBranch (const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const |
| On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use either a memory constraint or an address constraint. | |
| bool | isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const |
| Check whether a given call node is in tail position within its function. | |
| void | softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) const |
| Soften the operands of a comparison. | |
| void | softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling=false) const |
| virtual SDValue | visitMaskedLoad (SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue &NewLoad, SDValue Ptr, SDValue PassThru, SDValue Mask) const |
| virtual SDValue | visitMaskedStore (SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue Ptr, SDValue Val, SDValue Mask) const |
| std::pair< SDValue, SDValue > | makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const |
| Returns a pair of (return value, chain). | |
| bool | parametersInCSRMatch (const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const |
| Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function. | |
| virtual bool | findOptimalMemOpLowering (std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const |
| Determines the optimal series of memory ops to replace the memset / memcpy. | |
| bool | ShrinkDemandedConstant (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const |
| Check to see if the specified operand of the specified instruction is a constant integer. | |
| bool | ShrinkDemandedConstant (SDValue Op, const APInt &DemandedBits, TargetLoweringOpt &TLO) const |
| Helper wrapper around ShrinkDemandedConstant, demanding all elements. | |
| virtual bool | targetShrinkDemandedConstant (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const |
| bool | ShrinkDemandedOp (SDValue Op, unsigned BitWidth, const APInt &DemandedBits, TargetLoweringOpt &TLO) const |
| Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const |
| Look at Op. | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const |
| Helper wrapper around SimplifyDemandedBits, demanding all elements. | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, DAGCombinerInfo &DCI) const |
| Helper wrapper around SimplifyDemandedBits. | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, DAGCombinerInfo &DCI) const |
| Helper wrapper around SimplifyDemandedBits. | |
| SDValue | SimplifyMultipleUseDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const |
| More limited version of SimplifyDemandedBits that can be used to "look
through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc. | |
| SDValue | SimplifyMultipleUseDemandedBits (SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, unsigned Depth=0) const |
| Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all elements. | |
| SDValue | SimplifyMultipleUseDemandedVectorElts (SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const |
| Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all bits from only some vector elements. | |
| bool | SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const |
| Look at Vector Op. | |
| bool | SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedElts, DAGCombinerInfo &DCI) const |
| Helper wrapper around SimplifyDemandedVectorElts. | |
| virtual bool | shouldSimplifyDemandedVectorElts (SDValue Op, const TargetLoweringOpt &TLO) const |
| Return true if the target supports simplifying demanded vector elements by converting them to undefs. | |
| virtual void | computeKnownBitsForTargetNode (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const |
| Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. | |
| virtual void | computeKnownBitsForTargetInstr (GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const |
| Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. | |
| virtual Align | computeKnownAlignForTargetInstr (GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const |
Determine the known alignment for the pointer value R. | |
| virtual void | computeKnownBitsForFrameIndex (int FIOp, KnownBits &Known, const MachineFunction &MF) const |
Determine which of the bits of FrameIndex FIOp are known to be 0. | |
| virtual unsigned | ComputeNumSignBitsForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const |
| This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner. | |
| virtual unsigned | computeNumSignBitsForTargetInstr (GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const |
| This method can be implemented by targets that want to expose additional information about sign bits to GlobalISel combiners. | |
| virtual bool | SimplifyDemandedVectorEltsForTargetNode (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const |
| Attempt to simplify any target nodes based on the demanded vector elements, returning true on success. | |
| virtual bool | SimplifyDemandedBitsForTargetNode (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) const |
| Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success. | |
| virtual SDValue | SimplifyMultipleUseDemandedBitsForTargetNode (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const |
| More limited version of SimplifyDemandedBits that can be used to "look
through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc. | |
| virtual bool | isGuaranteedNotToBeUndefOrPoisonForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const |
Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits. | |
| virtual bool | canCreateUndefOrPoisonForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const |
| Return true if Op can create undef or poison from non-undef & non-poison operands. | |
| SDValue | buildLegalVectorShuffle (EVT VT, const SDLoc &DL, SDValue N0, SDValue N1, MutableArrayRef< int > Mask, SelectionDAG &DAG) const |
| Tries to build a legal vector shuffle using the provided parameters or equivalent variations. | |
| virtual const Constant * | getTargetConstantFromLoad (LoadSDNode *LD) const |
| This method returns the constant pool value that will be loaded by LD. | |
| virtual bool | isKnownNeverNaNForTargetNode (SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const |
If SNaN is false,. | |
| virtual bool | isSplatValueForTargetNode (SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const |
Return true if vector Op has the same value across all DemandedElts, indicating any elements which may be undef in the output UndefElts. | |
| virtual bool | isTargetCanonicalConstantNode (SDValue Op) const |
| Returns true if the given Opc is considered a canonical constant for the target, which should not be transformed back into a BUILD_VECTOR. | |
| bool | isConstTrueVal (SDValue N) const |
| Return if the N is a constant or constant vector equal to the true value from getBooleanContents(). | |
| bool | isConstFalseVal (SDValue N) const |
| Return if the N is a constant or constant vector equal to the false value from getBooleanContents(). | |
| bool | isExtendedTrueVal (const ConstantSDNode *N, EVT VT, bool SExt) const |
Return if N is a True value when extended to VT. | |
| SDValue | SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const |
| Try to simplify a setcc built with the specified operands and cc. | |
| virtual SDValue | unwrapAddress (SDValue N) const |
| virtual bool | isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const |
| Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset. | |
| virtual SDValue | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. | |
| virtual bool | isDesirableToCommuteWithShift (const SDNode *N, CombineLevel Level) const |
| Return true if it is profitable to move this shift by a constant amount through its operand, adjusting any immediate operands as necessary to preserve semantics. | |
| virtual bool | isDesirableToCommuteWithShift (const MachineInstr &MI, bool IsAfterLegal) const |
| GlobalISel - return true if it is profitable to move this shift by a constant amount through its operand, adjusting any immediate operands as necessary to preserve semantics. | |
| virtual bool | isDesirableToPullExtFromShl (const MachineInstr &MI) const |
| GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x), y => zext (shl x, y) | |
| virtual AndOrSETCCFoldKind | isDesirableToCombineLogicOpOfSETCC (const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const |
| virtual bool | isDesirableToCommuteXorWithShift (const SDNode *N) const |
| Return true if it is profitable to combine an XOR of a logical shift to create a logical shift of NOT. | |
| virtual bool | isTypeDesirableForOp (unsigned, EVT VT) const |
| Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. | |
| virtual bool | isDesirableToTransformToIntegerOp (unsigned, EVT) const |
| Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. | |
| virtual bool | IsDesirableToPromoteOp (SDValue, EVT &) const |
| This method query the target whether it is beneficial for dag combiner to promote the specified node. | |
| virtual bool | supportSwiftError () const |
| Return true if the target supports swifterror attribute. | |
| virtual bool | supportSplitCSR (MachineFunction *MF) const |
| Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies. | |
| virtual bool | supportKCFIBundles () const |
| Return true if the target supports kcfi operand bundles. | |
| virtual bool | supportPtrAuthBundles () const |
| Return true if the target supports ptrauth operand bundles. | |
| virtual void | initializeSplitCSR (MachineBasicBlock *Entry) const |
| Perform necessary initialization to handle a subset of CSRs explicitly via copies. | |
| virtual void | insertCopiesSplitCSR (MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const |
| Insert explicit copies in entry and exit blocks. | |
| virtual SDValue | getNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const |
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation. | |
| SDValue | getCheaperOrNeutralNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, const NegatibleCost CostThreshold=NegatibleCost::Neutral, unsigned Depth=0) const |
| SDValue | getCheaperNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const |
| This is the helper function to return the newly negated expression only when the cost is cheaper. | |
| SDValue | getNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const |
| This is the helper function to return the newly negated expression if the cost is not expensive. | |
| virtual bool | splitValueIntoRegisterParts (SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const |
| Target-specific splitting of values into parts that fit a register storing a legal type. | |
| virtual bool | checkForPhysRegDependency (SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const |
| Allows the target to handle physreg-carried dependency in target-specific way. | |
| virtual SDValue | joinRegisterPartsIntoValue (SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const |
| Target-specific combining of register parts into its original value. | |
| virtual SDValue | LowerFormalArguments (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const |
| This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. | |
| std::pair< SDValue, SDValue > | LowerCallTo (CallLoweringInfo &CLI) const |
| This function lowers an abstract call to a function into an actual call. | |
| virtual SDValue | LowerCall (CallLoweringInfo &, SmallVectorImpl< SDValue > &) const |
| This hook must be implemented to lower calls into the specified DAG. | |
| virtual void | HandleByVal (CCState *, unsigned &, Align) const |
| Target-specific cleanup for formal ByVal parameters. | |
| virtual bool | CanLowerReturn (CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const |
| This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers. | |
| virtual SDValue | LowerReturn (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const |
| This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. | |
| virtual bool | isUsedByReturnOnly (SDNode *, SDValue &) const |
| Return true if result of the specified node is used by a return node only. | |
| virtual bool | mayBeEmittedAsTailCall (const CallInst *) const |
| Return true if the target may be able emit the call instruction as a tail call. | |
| virtual Register | getRegisterByName (const char *RegName, LLT Ty, const MachineFunction &MF) const |
| Return the register ID of the name passed in. | |
| virtual EVT | getTypeForExtReturn (LLVMContext &Context, EVT VT, ISD::NodeType) const |
| Return the type that should be used to zero or sign extend a zeroext/signext integer return value. | |
| virtual bool | functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const |
| For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers. | |
| virtual bool | shouldSplitFunctionArgumentsAsLittleEndian (const DataLayout &DL) const |
| For most targets, an LLVM type must be broken down into multiple smaller types. | |
| virtual const MCPhysReg * | getScratchRegisters (CallingConv::ID CC) const |
| Returns a 0 terminated array of registers that can be safely used as scratch registers. | |
| virtual ArrayRef< MCPhysReg > | getRoundingControlRegisters () const |
| Returns a 0 terminated array of rounding control registers that can be attached into strict FP call. | |
| virtual SDValue | prepareVolatileOrAtomicLoad (SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const |
| This callback is used to prepare for a volatile or atomic load. | |
| virtual void | LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const |
| This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. | |
| virtual SDValue | LowerOperation (SDValue Op, SelectionDAG &DAG) const |
| This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. | |
| virtual void | ReplaceNodeResults (SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const |
| This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type. | |
| virtual const char * | getTargetNodeName (unsigned Opcode) const |
| This method returns the name of a target specific DAG node. | |
| virtual FastISel * | createFastISel (FunctionLoweringInfo &, const TargetLibraryInfo *) const |
| This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. | |
| bool | verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const |
| virtual void | verifyTargetSDNode (const SDNode *N) const |
| Check the given SDNode. Aborts if it is invalid. | |
| virtual bool | ExpandInlineAsm (CallInst *) const |
| This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. | |
| virtual AsmOperandInfoVector | ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const |
| Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. | |
| virtual ConstraintWeight | getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const |
| Examine constraint type and operand type and determine a weight value. | |
| virtual ConstraintWeight | getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const |
| Examine constraint string and operand type and determine a weight value. | |
| virtual void | ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const |
| Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. | |
| virtual ConstraintType | getConstraintType (StringRef Constraint) const |
| Given a constraint, return the type of constraint it is for this target. | |
| ConstraintGroup | getConstraintPreferences (AsmOperandInfo &OpInfo) const |
| Given an OpInfo with list of constraints codes as strings, return a sorted Vector of pairs of constraint codes and their types in priority of what we'd prefer to lower them as. | |
| virtual std::pair< unsigned, const TargetRegisterClass * > | getRegForInlineAsmConstraint (const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const |
| Given a physical register constraint (e.g. | |
| virtual InlineAsm::ConstraintCode | getInlineAsmMemConstraint (StringRef ConstraintCode) const |
| virtual const char * | LowerXConstraint (EVT ConstraintVT) const |
| Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. | |
| virtual void | LowerAsmOperandForConstraint (SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const |
| Lower the specified operand into the Ops vector. | |
| virtual SDValue | LowerAsmOutputForConstraint (SDValue &Chain, SDValue &Glue, const SDLoc &DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const |
| virtual void | CollectTargetIntrinsicOperands (const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const |
| SDValue | BuildSDIV (SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) const |
| Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. | |
| SDValue | BuildUDIV (SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) const |
| Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. | |
| SDValue | buildSDIVPow2WithCMov (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const |
| Build sdiv by power-of-2 with conditional move instructions Ref: "Hacker's Delight" by Henry Warren 10-1 If conditional move/branch is preferred, we lower sdiv x, +/-2**k into: bgez x, label add x, x, 2**k-1 label: sra res, x, k neg res, res (when the divisor is negative) | |
| virtual SDValue | BuildSDIVPow2 (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const |
| Targets may override this function to provide custom SDIV lowering for power-of-2 denominators. | |
| virtual SDValue | BuildSREMPow2 (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const |
| Targets may override this function to provide custom SREM lowering for power-of-2 denominators. | |
| virtual unsigned | combineRepeatedFPDivisors () const |
| Indicate whether this target prefers to combine FDIVs with the same divisor. | |
| virtual SDValue | getSqrtEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const |
| Hooks for building estimates in place of slower divisions and square roots. | |
| SDValue | createSelectForFMINNUM_FMAXNUM (SDNode *Node, SelectionDAG &DAG) const |
| Try to convert the fminnum/fmaxnum to a compare/select sequence. | |
| virtual SDValue | getRecipEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const |
| Return a reciprocal estimate value for the input operand. | |
| virtual SDValue | getSqrtInputTest (SDValue Operand, SelectionDAG &DAG, const DenormalMode &Mode) const |
| Return a target-dependent comparison result if the input operand is suitable for use with a square root estimate calculation. | |
| virtual SDValue | getSqrtResultForDenormInput (SDValue Operand, SelectionDAG &DAG) const |
| Return a target-dependent result if the input operand is not suitable for use with a square root estimate calculation. | |
| bool | expandMUL_LOHI (unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const |
| Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result. | |
| bool | expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const |
| Expand a MUL into two nodes. | |
| bool | expandDIVREMByConstant (SDNode *N, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue()) const |
| Attempt to expand an n-bit div/rem/divrem by constant using a n/2-bit urem by constant and other arithmetic ops. | |
| SDValue | expandFunnelShift (SDNode *N, SelectionDAG &DAG) const |
| Expand funnel shift. | |
| SDValue | expandROT (SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) const |
| Expand rotations. | |
| void | expandShiftParts (SDNode *N, SDValue &Lo, SDValue &Hi, SelectionDAG &DAG) const |
| Expand shift-by-parts. | |
| bool | expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand float(f32) to SINT(i64) conversion. | |
| bool | expandFP_TO_UINT (SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const |
| Expand float to UINT conversion. | |
| bool | expandUINT_TO_FP (SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const |
| Expand UINT(i64) to double(f64) conversion. | |
| SDValue | expandFMINNUM_FMAXNUM (SDNode *N, SelectionDAG &DAG) const |
| Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs. | |
| SDValue | expandFMINIMUM_FMAXIMUM (SDNode *N, SelectionDAG &DAG) const |
| Expand fminimum/fmaximum into multiple comparison with selects. | |
| SDValue | expandFMINIMUMNUM_FMAXIMUMNUM (SDNode *N, SelectionDAG &DAG) const |
| Expand fminimumnum/fmaximumnum into multiple comparison with selects. | |
| SDValue | expandFP_TO_INT_SAT (SDNode *N, SelectionDAG &DAG) const |
| Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max. | |
| SDValue | expandRoundInexactToOdd (EVT ResultVT, SDValue Op, const SDLoc &DL, SelectionDAG &DAG) const |
| Truncate Op to ResultVT. | |
| SDValue | expandFP_ROUND (SDNode *Node, SelectionDAG &DAG) const |
| Expand round(fp) to fp conversion. | |
| SDValue | expandIS_FPCLASS (EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) const |
| Expand check for floating point class. | |
| SDValue | expandCTPOP (SDNode *N, SelectionDAG &DAG) const |
| Expand CTPOP nodes. | |
| SDValue | expandVPCTPOP (SDNode *N, SelectionDAG &DAG) const |
| Expand VP_CTPOP nodes. | |
| SDValue | expandCTLZ (SDNode *N, SelectionDAG &DAG) const |
| Expand CTLZ/CTLZ_ZERO_UNDEF nodes. | |
| SDValue | expandVPCTLZ (SDNode *N, SelectionDAG &DAG) const |
| Expand VP_CTLZ/VP_CTLZ_ZERO_UNDEF nodes. | |
| SDValue | CTTZTableLookup (SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned NumBitsPerElt) const |
| Expand CTTZ via Table Lookup. | |
| SDValue | expandCTTZ (SDNode *N, SelectionDAG &DAG) const |
| Expand CTTZ/CTTZ_ZERO_UNDEF nodes. | |
| SDValue | expandVPCTTZ (SDNode *N, SelectionDAG &DAG) const |
| Expand VP_CTTZ/VP_CTTZ_ZERO_UNDEF nodes. | |
| SDValue | expandVPCTTZElements (SDNode *N, SelectionDAG &DAG) const |
| Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_UNDEF nodes. | |
| SDValue | expandABS (SDNode *N, SelectionDAG &DAG, bool IsNegative=false) const |
| Expand ABS nodes. | |
| SDValue | expandABD (SDNode *N, SelectionDAG &DAG) const |
| Expand ABDS/ABDU nodes. | |
| SDValue | expandAVG (SDNode *N, SelectionDAG &DAG) const |
| Expand vector/scalar AVGCEILS/AVGCEILU/AVGFLOORS/AVGFLOORU nodes. | |
| SDValue | expandBSWAP (SDNode *N, SelectionDAG &DAG) const |
| Expand BSWAP nodes. | |
| SDValue | expandVPBSWAP (SDNode *N, SelectionDAG &DAG) const |
| Expand VP_BSWAP nodes. | |
| SDValue | expandBITREVERSE (SDNode *N, SelectionDAG &DAG) const |
| Expand BITREVERSE nodes. | |
| SDValue | expandVPBITREVERSE (SDNode *N, SelectionDAG &DAG) const |
| Expand VP_BITREVERSE nodes. | |
| std::pair< SDValue, SDValue > | scalarizeVectorLoad (LoadSDNode *LD, SelectionDAG &DAG) const |
| Turn load of vector type into a load of the individual elements. | |
| SDValue | scalarizeVectorStore (StoreSDNode *ST, SelectionDAG &DAG) const |
| std::pair< SDValue, SDValue > | expandUnalignedLoad (LoadSDNode *LD, SelectionDAG &DAG) const |
| Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors. | |
| SDValue | expandUnalignedStore (StoreSDNode *ST, SelectionDAG &DAG) const |
| Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors. | |
| SDValue | IncrementMemoryAddress (SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const |
Increments memory address Addr according to the type of the value DataVT that should be stored. | |
| SDValue | getVectorElementPointer (SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const |
Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base address of VecPtr. | |
| SDValue | getVectorSubVecPointer (SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, EVT SubVecVT, SDValue Index) const |
Get a pointer to a sub-vector of type SubVecVT at index Idx located in memory for a vector of type VecVT starting at a base address of VecPtr. | |
| SDValue | expandIntMINMAX (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::[US][MIN|MAX]. | |
| SDValue | expandAddSubSat (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. | |
| SDValue | expandCMP (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::[US]CMP. | |
| SDValue | expandShlSat (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::[US]SHLSAT. | |
| SDValue | expandFixedPointMul (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT]. | |
| SDValue | expandFixedPointDiv (unsigned Opcode, const SDLoc &dl, SDValue LHS, SDValue RHS, unsigned Scale, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::[US]DIVFIX[SAT]. | |
| void | expandUADDSUBO (SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::U(ADD|SUB)O. | |
| void | expandSADDSUBO (SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::S(ADD|SUB)O. | |
| bool | expandMULO (SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::[US]MULO. | |
| void | forceExpandWideMUL (SelectionDAG &DAG, const SDLoc &dl, bool Signed, EVT WideVT, const SDValue LL, const SDValue LH, const SDValue RL, const SDValue RH, SDValue &Lo, SDValue &Hi) const |
| forceExpandWideMUL - Unconditionally expand a MUL into either a libcall or brute force via a wide multiplication. | |
| void | forceExpandWideMUL (SelectionDAG &DAG, const SDLoc &dl, bool Signed, const SDValue LHS, const SDValue RHS, SDValue &Lo, SDValue &Hi) const |
| Same as above, but creates the upper halves of each operand by sign/zero-extending the operands. | |
| SDValue | expandVecReduce (SDNode *Node, SelectionDAG &DAG) const |
| Expand a VECREDUCE_* into an explicit calculation. | |
| SDValue | expandVecReduceSeq (SDNode *Node, SelectionDAG &DAG) const |
| Expand a VECREDUCE_SEQ_* into an explicit ordered calculation. | |
| bool | expandREM (SDNode *Node, SDValue &Result, SelectionDAG &DAG) const |
| Expand an SREM or UREM using SDIV/UDIV or SDIVREM/UDIVREM, if legal. | |
| SDValue | expandVectorSplice (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::VECTOR_SPLICE. | |
| SDValue | expandVECTOR_COMPRESS (SDNode *Node, SelectionDAG &DAG) const |
| Expand a vector VECTOR_COMPRESS into a sequence of extract element, store temporarily, advance store position, before re-loading the final vector. | |
| bool | LegalizeSetCCCondCode (SelectionDAG &DAG, EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, SDValue Mask, SDValue EVL, bool &NeedInvert, const SDLoc &dl, SDValue &Chain, bool IsSignaling=false) const |
| Legalize a SETCC or VP_SETCC with given LHS and RHS and condition code CC on the current target. | |
| virtual MachineBasicBlock * | EmitInstrWithCustomInserter (MachineInstr &MI, MachineBasicBlock *MBB) const |
| This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. | |
| virtual void | AdjustInstrPostInstrSelection (MachineInstr &MI, SDNode *Node) const |
| This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. | |
| virtual bool | useLoadStackGuardNode () const |
| If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. | |
| virtual SDValue | emitStackGuardXorFP (SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const |
| virtual SDValue | LowerToTLSEmulatedModel (const GlobalAddressSDNode *GA, SelectionDAG &DAG) const |
| Lower TLS global address SDNode for target independent emulated TLS model. | |
| virtual SDValue | expandIndirectJTBranch (const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) const |
| Expands target specific indirect branch for the case of JumpTable expansion. | |
| SDValue | lowerCmpEqZeroToCtlzSrl (SDValue Op, SelectionDAG &DAG) const |
| virtual bool | isXAndYEqZeroPreferableToXAndYEqY (ISD::CondCode, EVT) const |
| Public Member Functions inherited from llvm::TargetLoweringBase | |
| virtual void | markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const |
| TargetLoweringBase (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. | |
| TargetLoweringBase (const TargetLoweringBase &)=delete | |
| TargetLoweringBase & | operator= (const TargetLoweringBase &)=delete |
| virtual | ~TargetLoweringBase ()=default |
| bool | isStrictFPEnabled () const |
| Return true if the target support strict float operation. | |
| const TargetMachine & | getTargetMachine () const |
| virtual bool | useSoftFloat () const |
| virtual MVT | getPointerTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the pointer type for the given address space, defaults to the pointer type from the data layout. | |
| virtual MVT | getPointerMemTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout. | |
| MVT | getFrameIndexTy (const DataLayout &DL) const |
| Return the type for frame index, which is determined by the alloca address space specified through the data layout. | |
| MVT | getProgramPointerTy (const DataLayout &DL) const |
| Return the type for code pointers, which is determined by the program address space specified through the data layout. | |
| virtual MVT | getFenceOperandTy (const DataLayout &DL) const |
| Return the type for operands of fence. | |
| virtual MVT | getScalarShiftAmountTy (const DataLayout &, EVT) const |
| Return the type to use for a scalar shift opcode, given the shifted amount type. | |
| EVT | getShiftAmountTy (EVT LHSTy, const DataLayout &DL) const |
| Returns the type for the shift amount of a shift opcode. | |
| virtual LLVM_READONLY LLT | getPreferredShiftAmountTy (LLT ShiftValueTy) const |
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy. | |
| virtual MVT | getVectorIdxTy (const DataLayout &DL) const |
| Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. | |
| virtual MVT | getVPExplicitVectorLengthTy () const |
| Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc. | |
| virtual MachineMemOperand::Flags | getTargetMMOFlags (const Instruction &I) const |
| This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them. | |
| virtual MachineMemOperand::Flags | getTargetMMOFlags (const MemSDNode &Node) const |
| This callback is used to inspect load/store SDNode. | |
| MachineMemOperand::Flags | getLoadMemOperandFlags (const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const |
| MachineMemOperand::Flags | getStoreMemOperandFlags (const StoreInst &SI, const DataLayout &DL) const |
| MachineMemOperand::Flags | getAtomicMemOperandFlags (const Instruction &AI, const DataLayout &DL) const |
| virtual bool | isSelectSupported (SelectSupportKind) const |
| virtual bool | shouldExpandGetActiveLaneMask (EVT VT, EVT OpVT) const |
| Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder. | |
| virtual bool | shouldExpandGetVectorLength (EVT CountVT, unsigned VF, bool IsScalable) const |
| virtual bool | shouldExpandCttzElements (EVT VT) const |
| Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in SelectionDAGBuilder. | |
| unsigned | getBitWidthForCttzElements (Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const |
| Return the minimum number of bits required to hold the maximum possible number of trailing zero vector elements. | |
| virtual bool | shouldReassociateReduction (unsigned RedOpc, EVT VT) const |
| virtual bool | reduceSelectOfFPConstantLoads (EVT CmpOpVT) const |
| Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. | |
| bool | hasMultipleConditionRegisters () const |
| Return true if multiple condition registers are available. | |
| bool | hasExtractBitsInsn () const |
| Return true if the target has BitExtract instructions. | |
| virtual TargetLoweringBase::LegalizeTypeAction | getPreferredVectorAction (MVT VT) const |
| Return the preferred vector type legalization action. | |
| virtual bool | softPromoteHalfType () const |
| virtual bool | useFPRegsForHalfType () const |
| virtual bool | shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const |
| virtual bool | isIntDivCheap (EVT VT, AttributeList Attr) const |
| Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. | |
| virtual bool | hasStandaloneRem (EVT VT) const |
| Return true if the target can handle a standalone remainder operation. | |
| virtual bool | isFsqrtCheap (SDValue X, SelectionDAG &DAG) const |
| Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). | |
| int | getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. | |
| int | getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. | |
| int | getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a square root of the given type based on the function's attributes. | |
| int | getDivRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a division of the given type based on the function's attributes. | |
| bool | isSlowDivBypassed () const |
| Returns true if target has indicated at least one type should be bypassed. | |
| const DenseMap< unsigned int, unsigned int > & | getBypassSlowDivWidths () const |
| Returns map of slow types for division or remainder with corresponding fast types. | |
| virtual bool | isVScaleKnownToBeAPowerOfTwo () const |
| Return true only if vscale must be a power of two. | |
| bool | isJumpExpensive () const |
| Return true if Flow Control is an expensive operation that should be avoided. | |
| virtual CondMergingParams | getJumpConditionMergingParams (Instruction::BinaryOps, const Value *, const Value *) const |
| bool | isPredictableSelectExpensive () const |
| Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. | |
| virtual bool | fallBackToDAGISel (const Instruction &Inst) const |
| virtual bool | isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const |
| Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. | |
| virtual bool | isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const |
| Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*)) | |
| virtual bool | storeOfVectorConstantIsCheap (bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const |
| Return true if it is expected to be cheaper to do a store of vector constant with the given size and type for the address space than to store the individual scalar element constants. | |
| virtual bool | mergeStoresAfterLegalization (EVT MemVT) const |
| Allow store merging for the specified type after legalization in addition to before legalization. | |
| virtual bool | canMergeStoresTo (unsigned AS, EVT MemVT, const MachineFunction &MF) const |
| Returns if it's reasonable to merge stores to MemVT size. | |
| virtual bool | isCheapToSpeculateCttz (Type *Ty) const |
| Return true if it is cheap to speculate a call to intrinsic cttz. | |
| virtual bool | isCheapToSpeculateCtlz (Type *Ty) const |
| Return true if it is cheap to speculate a call to intrinsic ctlz. | |
| virtual bool | isCtlzFast () const |
| Return true if ctlz instruction is fast. | |
| virtual bool | isCtpopFast (EVT VT) const |
| Return true if ctpop instruction is fast. | |
| virtual unsigned | getCustomCtpopCost (EVT VT, ISD::CondCode Cond) const |
| Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP. | |
| virtual bool | isEqualityCmpFoldedWithSignedCmp () const |
| Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison. | |
| virtual bool | preferZeroCompareBranch () const |
| Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare. | |
| virtual bool | isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const |
| Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. | |
| virtual bool | isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const |
| Return if the target supports combining a chain like: | |
| virtual bool | areTwoSDNodeTargetMMOFlagsMergeable (const MemSDNode &NodeX, const MemSDNode &NodeY) const |
| Return true if it is valid to merge the TargetMMOFlags in two SDNodes. | |
| virtual bool | convertSetCCLogicToBitwiseLogic (EVT VT) const |
| Use bitwise logic to make pairs of compares more efficient. | |
| virtual MVT | hasFastEqualityCompare (unsigned NumBits) const |
| Return the preferred operand type if the target has a quick way to compare integer values of the given size. | |
| virtual bool | hasAndNotCompare (SDValue Y) const |
| Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. | |
| virtual bool | hasAndNot (SDValue X) const |
| Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. | |
| virtual bool | hasBitTest (SDValue X, SDValue Y) const |
| Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized. | |
| virtual bool | shouldFoldMaskToVariableShiftPair (SDValue X) const |
| There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred. | |
| virtual bool | shouldFoldConstantShiftPairToMask (const SDNode *N, CombineLevel Level) const |
| Return true if it is profitable to fold a pair of shifts into a mask. | |
| virtual bool | shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const |
| Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform. | |
| virtual bool | shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd (SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const |
| Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in. | |
| virtual bool | optimizeFMulOrFDivAsShiftAddBitcast (SDNode *N, SDValue FPConst, SDValue IntPow2) const |
| virtual unsigned | preferedOpcodeForCmpEqPiecesOfOperand (EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) const |
| virtual bool | preferIncOfAddToSubOfNot (EVT VT) const |
| These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical. | |
| virtual bool | preferABDSToABSWithNSW (EVT VT) const |
| virtual bool | preferScalarizeSplat (SDNode *N) const |
| virtual bool | preferSextInRegOfTruncate (EVT TruncVT, EVT VT, EVT ExtVT) const |
| bool | enableExtLdPromotion () const |
| Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). | |
| virtual bool | canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const |
| Return true if the target can combine store(extractelement VectorTy,
Idx). | |
| virtual bool | shallExtractConstSplatVectorElementToStore (Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const |
| Return true if the target shall perform extract vector element and store given that the vector is known to be splat of constant. | |
| virtual bool | shouldSplatInsEltVarIndex (EVT) const |
| Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead. | |
| virtual bool | enableAggressiveFMAFusion (EVT VT) const |
| Return true if target always benefits from combining into FMA for a given value type. | |
| virtual bool | enableAggressiveFMAFusion (LLT Ty) const |
| Return true if target always benefits from combining into FMA for a given value type. | |
| virtual EVT | getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const |
| Return the ValueType of the result of SETCC operations. | |
| virtual MVT::SimpleValueType | getCmpLibcallReturnType () const |
| Return the ValueType for comparison libcalls. | |
| BooleanContent | getBooleanContents (bool isVec, bool isFloat) const |
| For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. | |
| BooleanContent | getBooleanContents (EVT Type) const |
| SDValue | promoteTargetBoolean (SelectionDAG &DAG, SDValue Bool, EVT ValVT) const |
| Promote the given target boolean to a target boolean of the given type. | |
| Sched::Preference | getSchedulingPreference () const |
| Return target scheduling preference. | |
| virtual Sched::Preference | getSchedulingPreference (SDNode *) const |
| Some scheduler, e.g. | |
| virtual const TargetRegisterClass * | getRegClassFor (MVT VT, bool isDivergent=false) const |
| Return the register class that should be used for the specified value type. | |
| virtual bool | requiresUniformRegister (MachineFunction &MF, const Value *) const |
| Allows target to decide about the register class of the specific value that is live outside the defining block. | |
| virtual const TargetRegisterClass * | getRepRegClassFor (MVT VT) const |
| Return the 'representative' register class for the specified value type. | |
| virtual uint8_t | getRepRegClassCostFor (MVT VT) const |
| Return the cost of the 'representative' register class for the specified value type. | |
| virtual ShiftLegalizationStrategy | preferredShiftLegalizationStrategy (SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const |
| bool | isTypeLegal (EVT VT) const |
| Return true if the target has native support for the specified value type. | |
| const ValueTypeActionImpl & | getValueTypeActions () const |
| LegalizeKind | getTypeConversion (LLVMContext &Context, EVT VT) const |
| Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in order to type-legalize it. | |
| LegalizeTypeAction | getTypeAction (LLVMContext &Context, EVT VT) const |
| Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). | |
| LegalizeTypeAction | getTypeAction (MVT VT) const |
| virtual EVT | getTypeToTransformTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. | |
| EVT | getTypeToExpandTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. | |
| unsigned | getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Vector types are broken down into some number of legal first class types. | |
| virtual unsigned | getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. | |
| virtual bool | getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const |
| Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). | |
| virtual bool | isFPImmLegal (const APFloat &, EVT, bool ForCodeSize=false) const |
| Returns true if the target can instruction select the specified FP immediate natively. | |
| virtual bool | isShuffleMaskLegal (ArrayRef< int >, EVT) const |
| Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. | |
| virtual bool | canOpTrap (unsigned Op, EVT VT) const |
| Returns true if the operation can trap for the value type. | |
| virtual bool | isVectorClearMaskLegal (ArrayRef< int >, EVT) const |
| Similar to isShuffleMaskLegal. | |
| virtual LegalizeAction | getCustomOperationAction (SDNode &Op) const |
| How to legalize this custom operation? | |
| LegalizeAction | getOperationAction (unsigned Op, EVT VT) const |
| Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| virtual bool | isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const |
| Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. | |
| LegalizeAction | getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const |
| Some fixed point operations may be natively supported by the target but only for specific scales. | |
| LegalizeAction | getStrictFPOperationAction (unsigned Op, EVT VT) const |
| bool | isOperationLegalOrCustom (unsigned Op, EVT VT, bool LegalOnly=false) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering. | |
| bool | isOperationLegalOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const |
| Return true if the specified operation is legal on this target or can be made legal using promotion. | |
| bool | isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. | |
| bool | isOperationCustom (unsigned Op, EVT VT) const |
| Return true if the operation uses custom lowering, regardless of whether the type is legal or not. | |
| virtual bool | areJTsAllowed (const Function *Fn) const |
| Return true if lowering to a jump table is allowed. | |
| bool | rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const |
| Check whether the range [Low,High] fits in a machine word. | |
| virtual bool | isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const |
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values. | |
| virtual MVT | getPreferredSwitchConditionType (LLVMContext &Context, EVT ConditionVT) const |
| Returns preferred type for switch condition. | |
| bool | isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const |
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons. | |
| bool | isOperationExpand (unsigned Op, EVT VT) const |
| Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. | |
| bool | isOperationLegal (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target. | |
| LegalizeAction | getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal on this target. | |
| bool | isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal or custom on this target. | |
| LegalizeAction | getAtomicLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Same as getLoadExtAction, but for atomic loads. | |
| bool | isAtomicLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified atomic load with extension is legal on this target. | |
| LegalizeAction | getTruncStoreAction (EVT ValVT, EVT MemVT) const |
| Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isTruncStoreLegal (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation is legal on this target. | |
| bool | isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation has solution on this target. | |
| virtual bool | canCombineTruncStore (EVT ValVT, EVT MemVT, bool LegalOnly) const |
| LegalizeAction | getIndexedLoadAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isIndexedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. | |
| LegalizeAction | getIndexedStoreAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isIndexedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. | |
| LegalizeAction | getIndexedMaskedLoadAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isIndexedMaskedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. | |
| LegalizeAction | getIndexedMaskedStoreAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isIndexedMaskedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. | |
| virtual bool | shouldExtendGSIndex (EVT VT, EVT &EltTy) const |
| Returns true if the index type for a masked gather/scatter requires extending. | |
| virtual bool | shouldRemoveExtendFromGSIndex (SDValue Extend, EVT DataVT) const |
| virtual bool | isLegalScaleForGatherScatter (uint64_t Scale, uint64_t ElemSize) const |
| LegalizeAction | getCondCodeAction (ISD::CondCode CC, MVT VT) const |
| Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isCondCodeLegal (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal on this target. | |
| bool | isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal or custom on this target. | |
| MVT | getTypeToPromoteTo (unsigned Op, MVT VT) const |
| If the action for this operation is to promote, this method returns the ValueType to promote to. | |
| virtual EVT | getAsmOperandValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| EVT | getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the EVT corresponding to this LLVM type. | |
| EVT | getMemValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| MVT | getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the MVT corresponding to this LLVM type. See getValueType. | |
| virtual uint64_t | getByValTypeAlignment (Type *Ty, const DataLayout &DL) const |
| Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. | |
| MVT | getRegisterType (MVT VT) const |
| Return the type of registers that this ValueType will eventually require. | |
| MVT | getRegisterType (LLVMContext &Context, EVT VT) const |
| Return the type of registers that this ValueType will eventually require. | |
| virtual unsigned | getNumRegisters (LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const |
| Return the number of registers that this ValueType will eventually require. | |
| virtual MVT | getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const |
| Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. | |
| virtual unsigned | getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const |
| Certain targets require unusual breakdowns of certain types. | |
| virtual Align | getABIAlignmentForCallingConv (Type *ArgTy, const DataLayout &DL) const |
| Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type. | |
| virtual bool | ShouldShrinkFPConstant (EVT) const |
| If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. | |
| virtual bool | shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const |
| Return true if it is profitable to reduce a load to a smaller type. | |
| virtual bool | shouldRemoveRedundantExtend (SDValue Op) const |
| Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant, and use x directly. | |
| bool | isPaddedAtMostSignificantBitsWhenStored (EVT VT) const |
| Indicates if any padding is guaranteed to go at the most significant bits when storing the type to memory and the type size isn't equal to the store size. | |
| bool | hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const |
| When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. | |
| bool | hasTargetDAGCombine (ISD::NodeType NT) const |
| If true, the target has custom DAG combine transformations that it can perform for the specified node. | |
| unsigned | getGatherAllAliasesMaxDepth () const |
| virtual unsigned | getVaListSizeInBits (const DataLayout &DL) const |
| Returns the size of the platform's va_list object. | |
| unsigned | getMaxStoresPerMemset (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memset. | |
| unsigned | getMaxStoresPerMemcpy (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memcpy. | |
| virtual unsigned | getMaxGluedStoresPerMemcpy () const |
| Get maximum # of store operations to be glued together. | |
| unsigned | getMaxExpandSizeMemcmp (bool OptSize) const |
| Get maximum # of load operations permitted for memcmp. | |
| unsigned | getMaxStoresPerMemmove (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memmove. | |
| virtual bool | allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const |
| Determine if the target supports unaligned memory accesses. | |
| virtual bool | allowsMisalignedMemoryAccesses (LLT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const |
| LLT handling variant. | |
| bool | allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const |
| This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access. | |
| bool | allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const |
| Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand. | |
| virtual bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const |
| Return true if the target supports a memory access of this type for the given address space and alignment. | |
| bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const |
| Return true if the target supports a memory access of this type for the given MachineMemOperand. | |
| bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const |
| LLT handling variant. | |
| virtual EVT | getOptimalMemOpType (const MemOp &Op, const AttributeList &) const |
| Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. | |
| virtual LLT | getOptimalMemOpLLT (const MemOp &Op, const AttributeList &) const |
| LLT returning variant. | |
| virtual bool | isSafeMemOpType (MVT) const |
| Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. | |
| virtual unsigned | getMinimumJumpTableEntries () const |
| Return lower limit for number of blocks in a jump table. | |
| unsigned | getMinimumJumpTableDensity (bool OptForSize) const |
| Return lower limit of the density in a jump table. | |
| unsigned | getMaximumJumpTableSize () const |
| Return upper limit for number of entries in a jump table. | |
| virtual bool | isJumpTableRelative () const |
| Register | getStackPointerRegisterToSaveRestore () const |
| If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. | |
| virtual Register | getExceptionPointerRegister (const Constant *PersonalityFn) const |
| If a physical register, this returns the register that receives the exception address on entry to an EH pad. | |
| virtual Register | getExceptionSelectorRegister (const Constant *PersonalityFn) const |
| If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. | |
| virtual bool | needsFixedCatchObjects () const |
| Align | getMinStackArgumentAlignment () const |
| Return the minimum stack alignment of an argument. | |
| Align | getMinFunctionAlignment () const |
| Return the minimum function alignment. | |
| Align | getPrefFunctionAlignment () const |
| Return the preferred function alignment. | |
| virtual Align | getPrefLoopAlignment (MachineLoop *ML=nullptr) const |
| Return the preferred loop alignment. | |
| virtual unsigned | getMaxPermittedBytesForAlignment (MachineBasicBlock *MBB) const |
| Return the maximum amount of bytes allowed to be emitted when padding for alignment. | |
| virtual bool | alignLoopsWithOptSize () const |
| Should loops be aligned even when the function is marked OptSize (but not MinSize). | |
| virtual Value * | getIRStackGuard (IRBuilderBase &IRB) const |
| If the target has a standard location for the stack protector guard, returns the address of that location. | |
| virtual void | insertSSPDeclarations (Module &M) const |
| Inserts necessary declarations for SSP (stack protection) purpose. | |
| virtual Value * | getSDagStackGuard (const Module &M) const |
| Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. | |
| virtual bool | useStackGuardXorFP () const |
| If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. | |
| virtual Function * | getSSPStackGuardCheck (const Module &M) const |
| If the target has a standard stack protection check function that performs validation and error handling, returns the function. | |
| virtual Value * | getSafeStackPointerLocation (IRBuilderBase &IRB) const |
| Returns the target-specific address of the unsafe stack pointer. | |
| virtual bool | hasStackProbeSymbol (const MachineFunction &MF) const |
| Returns the name of the symbol used to emit stack probes or the empty string if not applicable. | |
| virtual bool | hasInlineStackProbe (const MachineFunction &MF) const |
| virtual StringRef | getStackProbeSymbolName (const MachineFunction &MF) const |
| virtual bool | isFreeAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const |
| Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. | |
| virtual bool | shouldAlignPointerArgs (CallInst *, unsigned &, Align &) const |
| Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. | |
| virtual void | emitAtomicCmpXchgNoStoreLLBalance (IRBuilderBase &Builder) const |
| virtual bool | shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const |
| Returns true if arguments should be sign-extended in lib calls. | |
| virtual bool | shouldExtendTypeInLibCall (EVT Type) const |
| Returns true if arguments should be extended in lib calls. | |
| virtual AtomicExpansionKind | shouldExpandAtomicLoadInIR (LoadInst *LI) const |
| Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. | |
| virtual AtomicExpansionKind | shouldCastAtomicLoadInIR (LoadInst *LI) const |
| Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass. | |
| virtual AtomicExpansionKind | shouldExpandAtomicStoreInIR (StoreInst *SI) const |
| Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into. | |
| virtual AtomicExpansionKind | shouldCastAtomicStoreInIR (StoreInst *SI) const |
| Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into. | |
| virtual AtomicExpansionKind | shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const |
| Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass. | |
| virtual AtomicExpansionKind | shouldExpandAtomicRMWInIR (AtomicRMWInst *RMW) const |
| Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. | |
| virtual AtomicExpansionKind | shouldCastAtomicRMWIInIR (AtomicRMWInst *RMWI) const |
| Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass. | |
| virtual LoadInst * | lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const |
| On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. | |
| virtual ISD::NodeType | getExtendForAtomicOps () const |
| Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). | |
| virtual ISD::NodeType | getExtendForAtomicCmpSwapArg () const |
| Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). | |
| virtual bool | shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const |
| Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. | |
| virtual bool | isProfitableToCombineMinNumMaxNum (EVT VT) const |
| virtual bool | convertSelectOfConstantsToMath (EVT VT) const |
| Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. | |
| virtual bool | decomposeMulByConstant (LLVMContext &Context, EVT VT, SDValue C) const |
| Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. | |
| virtual bool | isMulAddWithConstProfitable (SDValue AddNode, SDValue ConstNode) const |
| Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2). | |
| virtual bool | shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const |
| Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value. | |
| bool | isBeneficialToExpandPowI (int64_t Exponent, bool OptForSize) const |
| Return true if it is beneficial to expand an @llvm.powi. | |
| virtual bool | getAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const |
| CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. | |
| virtual bool | isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const |
| Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. | |
| virtual bool | addressingModeSupportsTLS (const GlobalValue &) const |
| Returns true if the targets addressing mode can target thread local storage (TLS). | |
| virtual int64_t | getPreferredLargeGEPBaseOffset (int64_t MinOffset, int64_t MaxOffset) const |
| Return the prefered common base offset. | |
| virtual bool | isLegalICmpImmediate (int64_t) const |
| Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. | |
| virtual bool | isLegalAddImmediate (int64_t) const |
| Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. | |
| virtual bool | isLegalAddScalableImmediate (int64_t) const |
| Return true if adding the specified scalable immediate is legal, that is the target has add instructions which can add a register with the immediate (multiplied by vscale) without having to materialize the immediate into a register. | |
| virtual bool | isLegalStoreImmediate (int64_t Value) const |
| Return true if the specified immediate is legal for the value input of a store instruction. | |
| virtual bool | isVectorShiftByScalarCheap (Type *Ty) const |
| Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. | |
| virtual Type * | shouldConvertSplatType (ShuffleVectorInst *SVI) const |
| Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI's scalar type if the new type is more profitable. | |
| virtual bool | shouldConvertPhiType (Type *From, Type *To) const |
| Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'. | |
| virtual bool | isCommutativeBinOp (unsigned Opcode) const |
| Returns true if the opcode is a commutative binary operation. | |
| virtual bool | isBinOp (unsigned Opcode) const |
| Return true if the node is a math/logic binary operator. | |
| virtual bool | isTruncateFree (Type *FromTy, Type *ToTy) const |
| Return true if it's free to truncate a value of type FromTy to type ToTy. | |
| virtual bool | allowTruncateForTailCall (Type *FromTy, Type *ToTy) const |
| Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. | |
| virtual bool | isTruncateFree (EVT FromVT, EVT ToVT) const |
| virtual bool | isTruncateFree (LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) const |
| virtual bool | isTruncateFree (SDValue Val, EVT VT2) const |
| Return true if truncating the specific node Val to type VT2 is free. | |
| virtual bool | isProfitableToHoist (Instruction *I) const |
| bool | isExtFree (const Instruction *I) const |
Return true if the extension represented by I is free. | |
| bool | isExtLoad (const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const |
Return true if Load and Ext can form an ExtLoad. | |
| virtual bool | isZExtFree (Type *FromTy, Type *ToTy) const |
| Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. | |
| virtual bool | isZExtFree (EVT FromTy, EVT ToTy) const |
| virtual bool | isZExtFree (LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) const |
| virtual bool | isZExtFree (SDValue Val, EVT VT2) const |
| Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). | |
| virtual bool | isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const |
| Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. | |
| virtual bool | signExtendConstant (const ConstantInt *C) const |
| Return true if this constant should be sign extended when promoting to a larger type. | |
| virtual bool | shouldSinkOperands (Instruction *I, SmallVectorImpl< Use * > &Ops) const |
| Return true if sinking I's operands to the same basic block as I is profitable, e.g. | |
| virtual bool | optimizeExtendOrTruncateConversion (Instruction *I, Loop *L, const TargetTransformInfo &TTI) const |
| Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target. | |
| virtual bool | hasPairedLoad (EVT, Align &) const |
| Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. | |
| virtual bool | hasVectorBlend () const |
| Return true if the target has a vector blend instruction. | |
| virtual unsigned | getMaxSupportedInterleaveFactor () const |
| Get the maximum supported factor for interleaved memory accesses. | |
| virtual bool | lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const |
| Lower an interleaved load to target specific intrinsics. | |
| virtual bool | lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const |
| Lower an interleaved store to target specific intrinsics. | |
| virtual bool | lowerDeinterleaveIntrinsicToLoad (IntrinsicInst *DI, LoadInst *LI, SmallVectorImpl< Instruction * > &DeadInsts) const |
| Lower a deinterleave intrinsic to a target specific load intrinsic. | |
| virtual bool | lowerInterleaveIntrinsicToStore (IntrinsicInst *II, StoreInst *SI, SmallVectorImpl< Instruction * > &DeadInsts) const |
| Lower an interleave intrinsic to a target specific store intrinsic. | |
| virtual bool | isFPExtFree (EVT DestVT, EVT SrcVT) const |
| Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). | |
| virtual bool | isFPExtFoldable (const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. | |
| virtual bool | isFPExtFoldable (const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. | |
| virtual bool | isVectorLoadExtDesirable (SDValue ExtVal) const |
| Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. | |
| virtual bool | isFNegFree (EVT VT) const |
| Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. | |
| virtual bool | isFAbsFree (EVT VT) const |
| Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. | |
| virtual bool | isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, EVT) const |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. | |
| virtual bool | isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, LLT) const |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. | |
| virtual bool | isFMAFasterThanFMulAndFAdd (const Function &F, Type *) const |
| IR version. | |
| virtual bool | isFMADLegal (const MachineInstr &MI, LLT Ty) const |
Returns true if MI can be combined with another instruction to form TargetOpcode::G_FMAD. | |
| virtual bool | isFMADLegal (const SelectionDAG &DAG, const SDNode *N) const |
| Returns true if be combined with to form an ISD::FMAD. | |
| virtual bool | generateFMAsInMachineCombiner (EVT VT, CodeGenOptLevel OptLevel) const |
| virtual bool | isNarrowingProfitable (EVT SrcVT, EVT DestVT) const |
| Return true if it's profitable to narrow operations of type SrcVT to DestVT. | |
| virtual bool | shouldFoldSelectWithIdentityConstant (unsigned BinOpcode, EVT VT) const |
| Return true if pulling a binary operation into a select with an identity constant is profitable. | |
| virtual bool | shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const |
| Return true if it is beneficial to convert a load of a constant to just the constant itself. | |
| virtual bool | isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const |
| Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index. | |
| virtual bool | shouldScalarizeBinop (SDValue VecOp) const |
| Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation. | |
| virtual bool | isExtractVecEltCheap (EVT VT, unsigned Index) const |
| Return true if extraction of a scalar element from the given vector type at the given index is cheap. | |
| virtual bool | shouldFormOverflowOp (unsigned Opcode, EVT VT, bool MathUsed) const |
| Try to convert math with an overflow comparison into the corresponding DAG node operation. | |
| virtual bool | aggressivelyPreferBuildVectorSources (EVT VecVT) const |
| virtual bool | shouldConsiderGEPOffsetSplit () const |
| virtual bool | shouldAvoidTransformToShift (EVT VT, unsigned Amount) const |
| Return true if creating a shift of the type by the given amount is not profitable. | |
| virtual bool | shouldFoldSelectWithSingleBitTest (EVT VT, const APInt &AndMask) const |
| virtual bool | shouldKeepZExtForFP16Conv () const |
| Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function. | |
| virtual bool | shouldConvertFpToSat (unsigned Op, EVT FPVT, EVT VT) const |
| Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns. | |
| virtual bool | shouldExpandCmpUsingSelects () const |
| Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean types. | |
| virtual bool | isComplexDeinterleavingSupported () const |
| Does this target support complex deinterleaving. | |
| virtual bool | isComplexDeinterleavingOperationSupported (ComplexDeinterleavingOperation Operation, Type *Ty) const |
| Does this target support complex deinterleaving with the given operation and type. | |
| virtual Value * | createComplexDeinterleavingIR (IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const |
| Create the IR node for the given complex deinterleaving operation. | |
| void | setLibcallName (RTLIB::Libcall Call, const char *Name) |
| Rename the default libcall routine name for the specified libcall. | |
| void | setLibcallName (ArrayRef< RTLIB::Libcall > Calls, const char *Name) |
| const char * | getLibcallName (RTLIB::Libcall Call) const |
| Get the libcall routine name for the specified libcall. | |
| void | setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC) |
| Override the default CondCode to be used to test the result of the comparison libcall against zero. | |
| ISD::CondCode | getCmpLibcallCC (RTLIB::Libcall Call) const |
| Get the CondCode that's to be used to test the result of the comparison libcall against zero. | |
| void | setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC) |
| Set the CallingConv that should be used for the specified libcall. | |
| CallingConv::ID | getLibcallCallingConv (RTLIB::Libcall Call) const |
| Get the CallingConv that should be used for the specified libcall. | |
| virtual void | finalizeLowering (MachineFunction &MF) const |
| Execute target specific actions to finalize target lowering. | |
| virtual bool | shouldLocalize (const MachineInstr &MI, const TargetTransformInfo *TTI) const |
Check whether or not MI needs to be moved close to its uses. | |
| int | InstructionOpcodeToISD (unsigned Opcode) const |
| Get the ISD node that corresponds to the Instruction class opcode. | |
| unsigned | getMaxAtomicSizeInBitsSupported () const |
| Returns the maximum atomic operation size (in bits) supported by the backend. | |
| unsigned | getMaxDivRemBitWidthSupported () const |
| Returns the size in bits of the maximum div/rem the backend supports. | |
| unsigned | getMaxLargeFPConvertBitWidthSupported () const |
| Returns the size in bits of the maximum larget fp convert the backend supports. | |
| unsigned | getMinCmpXchgSizeInBits () const |
| Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. | |
| bool | supportsUnalignedAtomics () const |
| Whether the target supports unaligned atomic operations. | |
| virtual Value * | emitMaskedAtomicRMWIntrinsic (IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const |
| Perform a masked atomicrmw using a target-specific intrinsic. | |
| virtual void | emitExpandAtomicRMW (AtomicRMWInst *AI) const |
| Perform a atomicrmw expansion using a target-specific way. | |
| virtual void | emitBitTestAtomicRMWIntrinsic (AtomicRMWInst *AI) const |
| Perform a bit test atomicrmw using a target-specific intrinsic. | |
| virtual void | emitCmpArithAtomicRMWIntrinsic (AtomicRMWInst *AI) const |
| Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic. | |
| virtual Value * | emitMaskedAtomicCmpXchgIntrinsic (IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const |
| Perform a masked cmpxchg using a target-specific intrinsic. | |
| virtual Instruction * | emitLeadingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const |
| Inserts in the IR a target-specific intrinsic specifying a fence. | |
| virtual Instruction * | emitTrailingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const |
Additional Inherited Members | |
| Public Types inherited from llvm::TargetLowering | |
| enum | ConstraintType { C_Register , C_RegisterClass , C_Memory , C_Address , C_Immediate , C_Other , C_Unknown } |
| enum | ConstraintWeight { CW_Invalid = -1 , CW_Okay = 0 , CW_Good = 1 , CW_Better = 2 , CW_Best = 3 , CW_SpecificReg = CW_Okay , CW_Register = CW_Good , CW_Memory = CW_Better , CW_Constant = CW_Best , CW_Default = CW_Okay } |
| using | AsmOperandInfoVector = std::vector< AsmOperandInfo > |
| using | ConstraintPair = std::pair< StringRef, TargetLowering::ConstraintType > |
| using | ConstraintGroup = SmallVector< ConstraintPair > |
| Public Types inherited from llvm::TargetLoweringBase | |
| enum | LegalizeAction : uint8_t { Legal , Promote , Expand , LibCall , Custom } |
| This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More... | |
| enum | LegalizeTypeAction : uint8_t { TypeLegal , TypePromoteInteger , TypeExpandInteger , TypeSoftenFloat , TypeExpandFloat , TypeScalarizeVector , TypeSplitVector , TypeWidenVector , TypePromoteFloat , TypeSoftPromoteHalf , TypeScalarizeScalableVector } |
| This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More... | |
| enum | BooleanContent { UndefinedBooleanContent , ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent } |
| Enum that describes how the target represents true/false values. More... | |
| enum | SelectSupportKind { ScalarValSelect , ScalarCondVectorVal , VectorMaskSelect } |
| Enum that describes what type of support for selects the target has. More... | |
| enum class | AtomicExpansionKind { None , CastToInteger , LLSC , LLOnly , CmpXChg , MaskedIntrinsic , BitTestIntrinsic , CmpArithIntrinsic , Expand , NotAtomic } |
| Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More... | |
| enum class | MulExpansionKind { Always , OnlyLegalOrCustom } |
| Enum that specifies when a multiplication should be expanded. More... | |
| enum class | NegatibleCost { Cheaper = 0 , Neutral = 1 , Expensive = 2 } |
| Enum that specifies when a float negation is beneficial. More... | |
| enum | AndOrSETCCFoldKind : uint8_t { None = 0 , AddAnd = 1 , NotAnd = 2 , ABS = 4 } |
| Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ...)). More... | |
| enum | ReciprocalEstimate : int { Unspecified = -1 , Disabled = 0 , Enabled = 1 } |
| Reciprocal estimate status values used by the functions below. More... | |
| enum class | ShiftLegalizationStrategy { ExpandToParts , ExpandThroughStack , LowerToLibcall } |
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recursion depth - how many expansion needed. More... | |
| using | LegalizeKind = std::pair< LegalizeTypeAction, EVT > |
| LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. | |
| using | ArgListTy = std::vector< ArgListEntry > |
| Static Public Member Functions inherited from llvm::TargetLoweringBase | |
| static ISD::NodeType | getExtendForContent (BooleanContent Content) |
| Protected Member Functions inherited from llvm::TargetLoweringBase | |
| void | initActions () |
| Initialize all of the actions to default values. | |
| Value * | getDefaultSafeStackPointerLocation (IRBuilderBase &IRB, bool UseTLS) const |
| void | setBooleanContents (BooleanContent Ty) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. | |
| void | setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. | |
| void | setBooleanVectorContents (BooleanContent Ty) |
| Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. | |
| void | setSchedulingPreference (Sched::Preference Pref) |
| Specify the target scheduling preference. | |
| void | setMinimumJumpTableEntries (unsigned Val) |
| Indicate the minimum number of blocks to generate jump tables. | |
| void | setMaximumJumpTableSize (unsigned) |
| Indicate the maximum number of entries in jump tables. | |
| void | setStackPointerRegisterToSaveRestore (Register R) |
| If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. | |
| void | setHasMultipleConditionRegisters (bool hasManyRegs=true) |
| Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. | |
| void | setHasExtractBitsInsn (bool hasExtractInsn=true) |
| Tells the code generator that the target has BitExtract instructions. | |
| void | setJumpIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. | |
| void | addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth) |
| Tells the code generator which bitwidths to bypass. | |
| void | addRegisterClass (MVT VT, const TargetRegisterClass *RC) |
| Add the specified register class as an available regclass for the specified value type. | |
| virtual std::pair< const TargetRegisterClass *, uint8_t > | findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const |
| Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". | |
| void | computeRegisterProperties (const TargetRegisterInfo *TRI) |
| Once all of the register classes are added, this allows us to compute derived properties we expose. | |
| void | setOperationAction (unsigned Op, MVT VT, LegalizeAction Action) |
| Indicate that the specified operation does not work with the specified type and indicate what to do about it. | |
| void | setOperationAction (ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action) |
| void | setOperationAction (ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action) |
| void | setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. | |
| void | setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| void | setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action) |
| void | setAtomicLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Let target indicate that an extending atomic load of the specified type is legal. | |
| void | setAtomicLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| void | setAtomicLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action) |
| void | setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. | |
| void | setIndexedLoadAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. | |
| void | setIndexedLoadAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action) |
| void | setIndexedStoreAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. | |
| void | setIndexedStoreAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action) |
| void | setIndexedMaskedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it. | |
| void | setIndexedMaskedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it. | |
| void | setCondCodeAction (ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action) |
| Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. | |
| void | setCondCodeAction (ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action) |
| void | AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. | |
| void | setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| Convenience method to set an operation to Promote and specify the type in a single call. | |
| void | setOperationPromotedToType (ArrayRef< unsigned > Ops, MVT OrigVT, MVT DestVT) |
| void | setTargetDAGCombine (ArrayRef< ISD::NodeType > NTs) |
| Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. | |
| void | setMinFunctionAlignment (Align Alignment) |
| Set the target's minimum function alignment. | |
| void | setPrefFunctionAlignment (Align Alignment) |
| Set the target's preferred function alignment. | |
| void | setPrefLoopAlignment (Align Alignment) |
| Set the target's preferred loop alignment. | |
| void | setMaxBytesForAlignment (unsigned MaxBytes) |
| void | setMinStackArgumentAlignment (Align Alignment) |
| Set the minimum stack alignment of an argument. | |
| void | setMaxAtomicSizeInBitsSupported (unsigned SizeInBits) |
| Set the maximum atomic operation size supported by the backend. | |
| void | setMaxDivRemBitWidthSupported (unsigned SizeInBits) |
| Set the size in bits of the maximum div/rem the backend supports. | |
| void | setMaxLargeFPConvertBitWidthSupported (unsigned SizeInBits) |
| Set the size in bits of the maximum fp convert the backend supports. | |
| void | setMinCmpXchgSizeInBits (unsigned SizeInBits) |
| Sets the minimum cmpxchg or ll/sc size supported by the backend. | |
| void | setSupportsUnalignedAtomics (bool UnalignedSupported) |
| Sets whether unaligned atomic operations are supported. | |
| virtual bool | isExtFreeImpl (const Instruction *I) const |
Return true if the extension represented by I is free. | |
| bool | isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const |
| Return true if the value types that can be represented by the specified register class are all legal. | |
| MachineBasicBlock * | emitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. | |
| Protected Attributes inherited from llvm::TargetLoweringBase | |
| unsigned | GatherAllAliasesMaxDepth |
| Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more preferable chain. | |
| unsigned | MaxStoresPerMemset |
| Specify maximum number of store instructions per memset call. | |
| unsigned | MaxStoresPerMemsetOptSize |
| Likewise for functions with the OptSize attribute. | |
| unsigned | MaxStoresPerMemcpy |
| Specify maximum number of store instructions per memcpy call. | |
| unsigned | MaxStoresPerMemcpyOptSize |
| Likewise for functions with the OptSize attribute. | |
| unsigned | MaxGluedStoresPerMemcpy = 0 |
| Specify max number of store instructions to glue in inlined memcpy. | |
| unsigned | MaxLoadsPerMemcmp |
| Specify maximum number of load instructions per memcmp call. | |
| unsigned | MaxLoadsPerMemcmpOptSize |
| Likewise for functions with the OptSize attribute. | |
| unsigned | MaxStoresPerMemmove |
| Specify maximum number of store instructions per memmove call. | |
| unsigned | MaxStoresPerMemmoveOptSize |
| Likewise for functions with the OptSize attribute. | |
| bool | PredictableSelectIsExpensive |
| Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. | |
| bool | EnableExtLdPromotion |
| bool | IsStrictFPEnabled |
Detailed Description
Definition at line 559 of file AArch64ISelLowering.h.
Constructor & Destructor Documentation
◆ AArch64TargetLowering()
|
explicit |
Definition at line 376 of file AArch64ISelLowering.cpp.
References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::ISD::ABS, llvm::ISD::ADD, llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BRIND, llvm::ISD::BSWAP, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::TargetLoweringBase::Custom, llvm::ISD::DEBUGTRAP, llvm::ISD::DYNAMIC_STACKALLOC, llvm::TargetLoweringBase::EnableExtLdPromotion, llvm::TargetLoweringBase::Expand, llvm::ISD::EXPERIMENTAL_VECTOR_HISTOGRAM, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FACOS, llvm::ISD::FADD, llvm::ISD::FASIN, llvm::ISD::FATAN, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FCOSH, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP10, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FFREXP, llvm::MVT::fixedlen_vector_valuetypes(), llvm::ISD::FLDEXP, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMA, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::MVT::fp_fixedlen_vector_valuetypes(), llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT, llvm::ISD::FP_TO_UINT_SAT, llvm::MVT::fp_valuetypes(), llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::ISD::FSIN, llvm::ISD::FSINCOS, llvm::ISD::FSINH, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTAN, llvm::ISD::FTANH, llvm::ISD::FTRUNC, llvm::ISD::GET_FPMODE, llvm::ISD::GET_ROUNDING, llvm::TargetLoweringBase::getLibcallName(), llvm::AArch64Subtarget::getMaxBytesForLoopAlignment(), llvm::TargetLoweringBase::getMaximumJumpTableSize(), llvm::AArch64Subtarget::getMaximumJumpTableSize(), llvm::AArch64Subtarget::getPrefFunctionAlignment(), llvm::AArch64Subtarget::getPrefLoopAlignment(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::MVT::getVectorVT(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::Sched::Hybrid, im, llvm::ISD::INIT_TRAMPOLINE, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::MVT::integer_fixedlen_vector_valuetypes(), llvm::MVT::integer_valuetypes(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::AArch64Subtarget::isLittleEndian(), llvm::AArch64Subtarget::isNeonAvailable(), llvm::TargetLoweringBase::isOperationExpand(), llvm::AArch64Subtarget::isStreaming(), llvm::TargetLoweringBase::IsStrictFPEnabled, llvm::AArch64Subtarget::isSVEAvailable(), llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), llvm::AArch64Subtarget::isTargetMachO(), llvm::AArch64Subtarget::isTargetWindows(), llvm::AArch64Subtarget::isWindowsArm64EC(), llvm::ISD::JumpTable, llvm::CodeModel::Large, llvm::ISD::LAST_INDEXED_MODE, LCALLNAME4, LCALLNAME5, llvm::IRSimilarity::Legal, llvm::TargetLoweringBase::LibCall, llvm::ISD::LLRINT, llvm::ISD::LLROUND, llvm::ISD::LOAD, llvm::ISD::LRINT, llvm::ISD::LROUND, llvm::TargetLoweringBase::MaxGluedStoresPerMemcpy, llvm::TargetLoweringBase::MaxLoadsPerMemcmp, llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize, llvm::TargetLoweringBase::MaxStoresPerMemcpy, llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize, llvm::TargetLoweringBase::MaxStoresPerMemmove, llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize, llvm::TargetLoweringBase::MaxStoresPerMemset, llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize, llvm::ISD::MGATHER, llvm::ISD::MLOAD, llvm::ISD::MSCATTER, llvm::ISD::MSTORE, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::OR, llvm::ISD::PARITY, llvm::ISD::PRE_INC, llvm::TargetLoweringBase::PredictableSelectIsExpensive, llvm::ISD::PREFETCH, llvm::TargetLoweringBase::Promote, llvm::ISD::PtrAuthGlobalAddress, llvm::ISD::READCYCLECOUNTER, llvm::ISD::RESET_FPMODE, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::ISD::SADDSAT, llvm::StringSaver::save(), llvm::MVT::scalable_vector_valuetypes(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SET_FPMODE, llvm::ISD::SET_ROUNDING, llvm::TargetLoweringBase::setBooleanContents(), llvm::TargetLoweringBase::setBooleanVectorContents(), llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setHasExtractBitsInsn(), llvm::TargetLoweringBase::setIndexedLoadAction(), llvm::TargetLoweringBase::setIndexedStoreAction(), llvm::ISD::SETLE, llvm::TargetLoweringBase::setLibcallName(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::ISD::SETLT, llvm::TargetLoweringBase::setMaxAtomicSizeInBitsSupported(), llvm::TargetLoweringBase::setMaxBytesForAlignment(), llvm::TargetLoweringBase::setMaxDivRemBitWidthSupported(), llvm::TargetLoweringBase::setMaximumJumpTableSize(), llvm::TargetLoweringBase::setMinFunctionAlignment(), llvm::ISD::SETO, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setOperationPromotedToType(), llvm::TargetLoweringBase::setPrefFunctionAlignment(), llvm::TargetLoweringBase::setPrefLoopAlignment(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::SSUBSAT, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STEP_VECTOR, llvm::ISD::STORE, llvm::ISD::STRICT_FACOS, llvm::ISD::STRICT_FADD, llvm::ISD::STRICT_FASIN, llvm::ISD::STRICT_FATAN, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FCOS, llvm::ISD::STRICT_FCOSH, llvm::ISD::STRICT_FDIV, llvm::ISD::STRICT_FEXP, llvm::ISD::STRICT_FEXP2, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FLDEXP, llvm::ISD::STRICT_FLOG, llvm::ISD::STRICT_FLOG10, llvm::ISD::STRICT_FLOG2, llvm::ISD::STRICT_FMA, llvm::ISD::STRICT_FMAXIMUM, llvm::ISD::STRICT_FMAXNUM, llvm::ISD::STRICT_FMINIMUM, llvm::ISD::STRICT_FMINNUM, llvm::ISD::STRICT_FMUL, llvm::ISD::STRICT_FNEARBYINT, llvm::ISD::STRICT_FP_EXTEND, llvm::ISD::STRICT_FP_ROUND, llvm::ISD::STRICT_FP_TO_SINT, llvm::ISD::STRICT_FP_TO_UINT, llvm::ISD::STRICT_FPOW, llvm::ISD::STRICT_FPOWI, llvm::ISD::STRICT_FREM, llvm::ISD::STRICT_FRINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::STRICT_FSIN, llvm::ISD::STRICT_FSINH, llvm::ISD::STRICT_FSQRT, llvm::ISD::STRICT_FSUB, llvm::ISD::STRICT_FTAN, llvm::ISD::STRICT_FTANH, llvm::ISD::STRICT_FTRUNC, llvm::ISD::STRICT_LLRINT, llvm::ISD::STRICT_LLROUND, llvm::ISD::STRICT_LRINT, llvm::ISD::STRICT_LROUND, llvm::ISD::STRICT_SINT_TO_FP, llvm::ISD::STRICT_UINT_TO_FP, llvm::ISD::SUB, llvm::ISD::TRAP, llvm::ISD::TRUNCATE, llvm::ISD::TRUNCATE_SSAT_S, llvm::ISD::TRUNCATE_SSAT_U, llvm::ISD::TRUNCATE_USAT_U, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UADDSAT, llvm::ISD::UBSANTRAP, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::UREM, llvm::AArch64Subtarget::useSVEForFixedLengthVectors(), useSVEForFixedLengthVectorVT(), llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::USUBSAT, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMAXIMUM, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMINIMUM, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SEQ_FADD, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, llvm::ISD::VECTOR_COMPRESS, llvm::ISD::VECTOR_DEINTERLEAVE, llvm::ISD::VECTOR_INTERLEAVE, llvm::ISD::VECTOR_SPLICE, llvm::ISD::VSCALE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, and llvm::ISD::ZEXTLOAD.
Member Function Documentation
◆ allowsMisalignedMemoryAccesses() [1/2]
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overridevirtual |
Returns true if the target allows unaligned memory accesses of the specified type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2493 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::Fast, and llvm::EVT::getStoreSize().
Referenced by getOptimalMemOpLLT(), and getOptimalMemOpType().
◆ allowsMisalignedMemoryAccesses() [2/2]
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overridevirtual |
LLT variant.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2518 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::Fast, llvm::LLT::fixed_vector(), and llvm::LLT::getSizeInBytes().
◆ canMergeStoresTo()
|
inlineoverridevirtual |
Returns if it's reasonable to merge stores to MemVT size.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 849 of file AArch64ISelLowering.h.
References llvm::MachineFunction::getFunction(), llvm::EVT::getSizeInBits(), and llvm::Function::hasFnAttribute().
◆ CCAssignFnForCall()
| CCAssignFn * AArch64TargetLowering::CCAssignFnForCall | ( | CallingConv::ID | CC, |
| bool | IsVarArg | ||
| ) | const |
Selects the correct CCAssignFn for a given CallingConvention value.
Definition at line 7324 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0, llvm::CallingConv::AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2, llvm::CallingConv::AArch64_SVE_VectorCall, llvm::CallingConv::AArch64_VectorCall, llvm::CallingConv::ARM64EC_Thunk_Native, llvm::CallingConv::ARM64EC_Thunk_X64, llvm::CallingConv::C, CC, llvm::CC_AArch64_AAPCS(), llvm::CC_AArch64_Arm64EC_CFGuard_Check(), llvm::CC_AArch64_Arm64EC_Thunk(), llvm::CC_AArch64_Arm64EC_Thunk_Native(), llvm::CC_AArch64_Arm64EC_VarArg(), llvm::CC_AArch64_DarwinPCS(), llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(), llvm::CC_AArch64_DarwinPCS_VarArg(), llvm::CC_AArch64_GHC(), llvm::CC_AArch64_Preserve_None(), llvm::CC_AArch64_Win64_CFGuard_Check(), llvm::CC_AArch64_Win64_VarArg(), llvm::CC_AArch64_Win64PCS(), llvm::CallingConv::CFGuard_Check, llvm::CallingConv::CXX_FAST_TLS, llvm::CallingConv::Fast, llvm::CallingConv::GHC, llvm::CallingConv::GRAAL, llvm::AArch64Subtarget::isTargetDarwin(), llvm::AArch64Subtarget::isTargetILP32(), llvm::AArch64Subtarget::isTargetWindows(), llvm::AArch64Subtarget::isWindowsArm64EC(), llvm::CallingConv::PreserveAll, llvm::CallingConv::PreserveMost, llvm::CallingConv::PreserveNone, llvm::report_fatal_error(), llvm::CallingConv::Swift, llvm::CallingConv::SwiftTail, llvm::CallingConv::Tail, and llvm::CallingConv::Win64.
Referenced by analyzeCallOperands(), finishStackBlock(), getAssignFnsForCC(), and llvm::AArch64CallLowering::lowerFormalArguments().
◆ CCAssignFnForReturn()
| CCAssignFn * AArch64TargetLowering::CCAssignFnForReturn | ( | CallingConv::ID | CC | ) | const |
Selects the correct CCAssignFn for a given CallingConvention value.
Definition at line 7386 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::ARM64EC_Thunk_X64, CC, llvm::CallingConv::CFGuard_Check, llvm::AArch64Subtarget::isWindowsArm64EC(), llvm::RetCC_AArch64_AAPCS(), llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(), and llvm::RetCC_AArch64_Arm64EC_Thunk().
Referenced by llvm::AArch64CallLowering::lowerCall(), and llvm::AArch64CallLowering::lowerReturn().
◆ changeStreamingMode()
| SDValue AArch64TargetLowering::changeStreamingMode | ( | SelectionDAG & | DAG, |
| SDLoc | DL, | ||
| bool | Enable, | ||
| SDValue | Chain, | ||
| SDValue | InGlue, | ||
| unsigned | Condition, | ||
| SDValue | PStateSM = SDValue() |
||
| ) | const |
If a change in streaming mode is required on entry to/return from a function call it emits and returns the corresponding SMSTART or SMSTOP node.
Condition should be one of the enum values from AArch64SME::ToggleCondition.
Definition at line 8350 of file AArch64ISelLowering.cpp.
References llvm::AArch64SME::Always, assert(), DL, llvm::Enable, llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AArch64FunctionInfo::setHasStreamingModeChanges(), llvm::AArch64ISD::SMSTART, llvm::AArch64ISD::SMSTOP, and TRI.
◆ computeKnownBitsForTargetNode()
|
overridevirtual |
Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them Known.
Reimplemented from llvm::TargetLowering.
Definition at line 2329 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADDlow, llvm::KnownBits::ashr(), assert(), llvm::AArch64ISD::ASSERT_ZEXT_BOOL, llvm::AArch64ISD::BICi, llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::AArch64ISD::CSEL, llvm::Depth, llvm::AArch64ISD::DUP, llvm::KnownBits::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::EVT::getScalarSizeInBits(), llvm::KnownBits::intersectWith(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::AArch64Subtarget::isTargetILP32(), llvm::AArch64ISD::LOADgot, llvm::KnownBits::lshr(), llvm::KnownBits::makeConstant(), llvm::AArch64ISD::MOVI, llvm::KnownBits::shl(), llvm::KnownBits::trunc(), llvm::AArch64ISD::VASHR, llvm::AArch64ISD::VLSHR, llvm::AArch64ISD::VSHL, and llvm::KnownBits::Zero.
◆ ComputeNumSignBitsForTargetNode()
|
overridevirtual |
This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.
The DemandedElts argument allows us to only collect the minimum sign bits that are shared by the requested vector elements.
Reimplemented from llvm::TargetLowering.
Definition at line 2456 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::CMEQ, llvm::AArch64ISD::CMEQz, llvm::AArch64ISD::CMGE, llvm::AArch64ISD::CMGEz, llvm::AArch64ISD::CMGT, llvm::AArch64ISD::CMGTz, llvm::AArch64ISD::CMHI, llvm::AArch64ISD::CMHS, llvm::AArch64ISD::CMLEz, llvm::AArch64ISD::CMLTz, llvm::AArch64ISD::FCMEQ, llvm::AArch64ISD::FCMEQz, llvm::AArch64ISD::FCMGE, llvm::AArch64ISD::FCMGEz, llvm::AArch64ISD::FCMGT, llvm::AArch64ISD::FCMGTz, llvm::AArch64ISD::FCMLEz, llvm::AArch64ISD::FCMLTz, and llvm::EVT::getScalarSizeInBits().
◆ createComplexDeinterleavingIR()
|
overridevirtual |
Create the IR node for the given complex deinterleaving operation.
If one cannot be created using all the given inputs, nullptr should be returned.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 29024 of file AArch64ISelLowering.cpp.
References Accumulator, assert(), B, llvm::CAdd, llvm::CMulPartial, createComplexDeinterleavingIR(), llvm::PoisonValue::get(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), llvm::VectorType::getHalfElementsVectorType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::Constant::getNullValue(), llvm::Type::getScalarSizeInBits(), llvm::Value::getType(), llvm::Type::isIntegerTy(), llvm::isPowerOf2_32(), llvm::Type::isScalableTy(), llvm::Intrinsic::not_intrinsic, llvm::Rotation_270, and llvm::Rotation_90.
Referenced by createComplexDeinterleavingIR().
◆ createFastISel()
|
overridevirtual |
This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.
Reimplemented from llvm::TargetLowering.
Definition at line 2544 of file AArch64ISelLowering.cpp.
References llvm::AArch64::createFastISel().
◆ EmitAllocateZABuffer()
| MachineBasicBlock * AArch64TargetLowering::EmitAllocateZABuffer | ( | MachineInstr & | MI, |
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 3100 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineFrameInfo::CreateVariableSizedObject(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::AArch64Subtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::AArch64FunctionInfo::getTPIDR2Obj(), llvm::AArch64Subtarget::isTargetWindows(), MI, MRI, llvm::MachineBasicBlock::remove_instr(), Size, TII, and llvm::TPIDR2Object::Uses.
Referenced by EmitInstrWithCustomInserter().
◆ emitAtomicCmpXchgNoStoreLLBalance()
|
overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27177 of file AArch64ISelLowering.cpp.
References llvm::IRBuilderBase::CreateCall(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::GlobalValue::getParent(), and llvm::BasicBlock::getParent().
◆ EmitDynamicProbedAlloc()
| MachineBasicBlock * AArch64TargetLowering::EmitDynamicProbedAlloc | ( | MachineInstr & | MI, |
| MachineBasicBlock * | MBB | ||
| ) | const |
Definition at line 2953 of file AArch64ISelLowering.cpp.
References DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), MBB, MBBI, MI, and TII.
Referenced by EmitInstrWithCustomInserter().
◆ EmitF128CSEL()
| MachineBasicBlock * AArch64TargetLowering::EmitF128CSEL | ( | MachineInstr & | MI, |
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 2885 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::AArch64Subtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::insert(), MBB, MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by EmitInstrWithCustomInserter().
◆ EmitFill()
| MachineBasicBlock * AArch64TargetLowering::EmitFill | ( | MachineInstr & | MI, |
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 2987 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::AArch64Subtarget::getInstrInfo(), MI, and TII.
Referenced by EmitInstrWithCustomInserter().
◆ EmitInitTPIDR2Object()
| MachineBasicBlock * AArch64TargetLowering::EmitInitTPIDR2Object | ( | MachineInstr & | MI, |
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 3070 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::AArch64Subtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::AArch64FunctionInfo::getTPIDR2Obj(), MI, llvm::MachineBasicBlock::remove_instr(), llvm::MachineFrameInfo::RemoveStackObject(), and TII.
Referenced by EmitInstrWithCustomInserter().
◆ EmitInstrWithCustomInserter()
|
overridevirtual |
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.
These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of MBB.
Reimplemented from llvm::TargetLowering.
Definition at line 3143 of file AArch64ISelLowering.cpp.
References llvm::MachineOperand::CreateReg(), llvm::Pass::dump(), EmitAllocateZABuffer(), EmitDynamicProbedAlloc(), EmitF128CSEL(), EmitFill(), EmitInitTPIDR2Object(), EmitLoweredCatchRet(), llvm::TargetLoweringBase::emitPatchPoint(), EmitTileLoad(), EmitZAInstr(), EmitZero(), EmitZTInstr(), llvm::AArch64Subtarget::getInstrInfo(), llvm::AArch64::getSMEPseudoMap(), llvm_unreachable, MI, llvm::AArch64::SMEMatrixArray, llvm::AArch64::SMEMatrixTileB, llvm::AArch64::SMEMatrixTileD, llvm::AArch64::SMEMatrixTileH, llvm::AArch64::SMEMatrixTileQ, llvm::AArch64::SMEMatrixTileS, llvm::AArch64::SMEMatrixTypeMask, and TII.
◆ EmitKCFICheck()
|
overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27428 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::getInstr(), llvm_unreachable, MBB, MBBI, and TII.
◆ emitLoadLinked()
|
overridevirtual |
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27138 of file AArch64ISelLowering.cpp.
References llvm::CallBase::addParamAttr(), Addr, llvm::IRBuilderBase::CreateBitCast(), llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateExtractValue(), llvm::IRBuilderBase::CreateOr(), llvm::IRBuilderBase::CreateShl(), llvm::IRBuilderBase::CreateTrunc(), llvm::IRBuilderBase::CreateZExt(), DL, llvm::Attribute::get(), llvm::IRBuilderBase::getContext(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::IRBuilderBase::getIntNTy(), llvm::GlobalValue::getParent(), llvm::BasicBlock::getParent(), llvm::Type::getPrimitiveSizeInBits(), llvm::Hi, Int, llvm::isAcquireOrStronger(), and llvm::Lo.
◆ EmitLoweredCatchRet()
| MachineBasicBlock * AArch64TargetLowering::EmitLoweredCatchRet | ( | MachineInstr & | MI, |
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 2944 of file AArch64ISelLowering.cpp.
References assert(), llvm::classifyEHPersonality(), llvm::MachineFunction::getFunction(), llvm::MachineBasicBlock::getParent(), llvm::Function::getPersonalityFn(), and llvm::isAsynchronousEHPersonality().
Referenced by EmitInstrWithCustomInserter().
◆ emitStoreConditional()
|
overridevirtual |
Perform a store-conditional operation to Addr.
Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27183 of file AArch64ISelLowering.cpp.
References llvm::CallBase::addParamAttr(), Addr, llvm::IRBuilderBase::CreateBitCast(), llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateLShr(), llvm::IRBuilderBase::CreateTrunc(), llvm::IRBuilderBase::CreateZExtOrBitCast(), DL, llvm::Attribute::get(), llvm::IRBuilderBase::getContext(), llvm::Intrinsic::getDeclaration(), llvm::Function::getFunctionType(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt64Ty(), llvm::IRBuilderBase::getIntNTy(), llvm::FunctionType::getParamType(), llvm::GlobalValue::getParent(), llvm::BasicBlock::getParent(), llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::Hi, Int, llvm::isReleaseOrStronger(), and llvm::Lo.
◆ EmitTileLoad()
| MachineBasicBlock * AArch64TargetLowering::EmitTileLoad | ( | unsigned | Opc, |
| unsigned | BaseReg, | ||
| MachineInstr & | MI, | ||
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 2969 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::AArch64Subtarget::getInstrInfo(), MI, and TII.
Referenced by EmitInstrWithCustomInserter().
◆ EmitZAInstr()
| MachineBasicBlock * AArch64TargetLowering::EmitZAInstr | ( | unsigned | Opc, |
| unsigned | BaseReg, | ||
| MachineInstr & | MI, | ||
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 3019 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::AArch64Subtarget::getInstrInfo(), I, MI, and TII.
Referenced by EmitInstrWithCustomInserter().
◆ EmitZero()
| MachineBasicBlock * AArch64TargetLowering::EmitZero | ( | MachineInstr & | MI, |
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 3053 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::BuildMI(), llvm::AArch64Subtarget::getInstrInfo(), I, llvm::RegState::ImplicitDefine, MI, and TII.
Referenced by EmitInstrWithCustomInserter().
◆ EmitZTInstr()
| MachineBasicBlock * AArch64TargetLowering::EmitZTInstr | ( | MachineInstr & | MI, |
| MachineBasicBlock * | BB, | ||
| unsigned | Opcode, | ||
| bool | Op0IsDef | ||
| ) | const |
Definition at line 3002 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::AArch64Subtarget::getInstrInfo(), I, MI, and TII.
Referenced by EmitInstrWithCustomInserter().
◆ enableAggressiveFMAFusion()
Enable aggressive FMA fusion on targets that want it.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27456 of file AArch64ISelLowering.cpp.
References llvm::EVT::isFloatingPoint().
◆ fallBackToDAGISel()
|
overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27575 of file AArch64ISelLowering.cpp.
References llvm::sampleprof::Base, EnableSVEGISel, llvm::Instruction::getFunction(), llvm::User::getNumOperands(), llvm::User::getOperand(), llvm::Value::getType(), and llvm::Type::isScalableTy().
◆ functionArgumentNeedsConsecutiveRegisters()
|
overridevirtual |
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
Reimplemented from llvm::TargetLowering.
Definition at line 27221 of file AArch64ISelLowering.cpp.
References llvm::all_equal(), llvm::ComputeValueVTs(), DL, llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isArrayTy(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
◆ generateFMAsInMachineCombiner()
|
overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17919 of file AArch64ISelLowering.cpp.
References llvm::Aggressive, llvm::EVT::isScalableVector(), and useSVEForFixedLengthVectorVT().
◆ getAsmOperandValueType()
|
overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 11922 of file AArch64ISelLowering.cpp.
References DL, llvm::TargetLoweringBase::getAsmOperandValueType(), and llvm::Type::isIntegerTy().
◆ getExceptionPointerRegister()
|
inlineoverridevirtual |
If a physical register, this returns the register that receives the exception address on entry to an EH pad.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 834 of file AArch64ISelLowering.h.
◆ getExceptionSelectorRegister()
|
inlineoverridevirtual |
If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 842 of file AArch64ISelLowering.h.
◆ getIRStackGuard()
|
overridevirtual |
If the target has a standard location for the stack protector cookie, returns the address of that location.
Otherwise, returns nullptr.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27250 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::getIRStackGuard(), llvm::AArch64Subtarget::isTargetAndroid(), llvm::AArch64Subtarget::isTargetFuchsia(), and UseTlsOffset().
◆ getMaxSupportedInterleaveFactor()
|
inlineoverridevirtual |
Get the maximum supported factor for interleaved memory accesses.
Default to be the minimum interleave factor: 2.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 697 of file AArch64ISelLowering.h.
Referenced by lowerInterleavedLoad(), and lowerInterleavedStore().
◆ getNumInterleavedAccesses()
| unsigned AArch64TargetLowering::getNumInterleavedAccesses | ( | VectorType * | VecTy, |
| const DataLayout & | DL, | ||
| bool | UseScalable | ||
| ) | const |
Returns the number of interleaved accesses that will be generated when lowering accesses of the given type.
A helper function for determining the number of interleaved accesses we will generate when lowering accesses of the given type.
Definition at line 16866 of file AArch64ISelLowering.cpp.
References DL, llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), and llvm::AArch64Subtarget::getMinSVEVectorSizeInBits().
Referenced by llvm::AArch64TTIImpl::getInterleavedMemoryOpCost(), lowerDeinterleaveIntrinsicToLoad(), lowerInterleavedLoad(), lowerInterleavedStore(), and lowerInterleaveIntrinsicToStore().
◆ getNumRegistersForCallingConv()
|
overridevirtual |
Certain targets require unusual breakdowns of certain types.
For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 29152 of file AArch64ISelLowering.cpp.
References CC, llvm::TargetLoweringBase::getNumRegistersForCallingConv(), llvm::EVT::getVectorElementCount(), getVectorTypeBreakdownForCallingConv(), llvm::EVT::isFixedLengthVector(), llvm::ElementCount::isScalar(), and llvm::AArch64Subtarget::useSVEForFixedLengthVectors().
Referenced by llvm::AArch64CallLowering::lowerReturn().
◆ getOptimalMemOpLLT()
|
overridevirtual |
LLT returning variant.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17678 of file AArch64ISelLowering.cpp.
References allowsMisalignedMemoryAccesses(), llvm::CallingConv::Fast, llvm::LLT::fixed_vector(), llvm::AttributeList::hasFnAttr(), llvm::MachineMemOperand::MONone, and llvm::LLT::scalar().
◆ getOptimalMemOpType()
|
overridevirtual |
Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.
It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17648 of file AArch64ISelLowering.cpp.
References allowsMisalignedMemoryAccesses(), llvm::CallingConv::Fast, llvm::AttributeList::hasFnAttr(), and llvm::MachineMemOperand::MONone.
◆ getPointerTy()
|
inlineoverridevirtual |
Return the pointer type for the given address space, defaults to the pointer type from the data layout.
FIXME: The default needs to be removed once all the code is updated.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 587 of file AArch64ISelLowering.h.
References llvm::MVT::getIntegerVT().
Referenced by getVaListSizeInBits().
◆ getPreferredLargeGEPBaseOffset()
|
overridevirtual |
Return the prefered common base offset.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17872 of file AArch64ISelLowering.cpp.
References isLegalAddImmediate().
◆ getPreferredVectorAction()
|
overridevirtual |
Return the preferred vector type legalization action.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 26912 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::getPreferredVectorAction(), and llvm::TargetLoweringBase::TypeWidenVector.
◆ getPromotedVTForPredicate()
Definition at line 28895 of file AArch64ISelLowering.cpp.
Referenced by llvm::AArch64TTIImpl::getSpliceCost().
◆ getRedZoneSize()
Definition at line 987 of file AArch64ISelLowering.h.
References F.
Referenced by llvm::AArch64FrameLowering::canUseRedZone().
◆ getRegisterTypeForCallingConv()
|
overridevirtual |
Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.
For MIPS all vector types must be passed through the integer register set.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 29136 of file AArch64ISelLowering.cpp.
References CC, llvm::TargetLoweringBase::getRegisterTypeForCallingConv(), llvm::EVT::getVectorElementCount(), getVectorTypeBreakdownForCallingConv(), llvm::EVT::isFixedLengthVector(), llvm::ElementCount::isScalar(), and llvm::AArch64Subtarget::useSVEForFixedLengthVectors().
Referenced by llvm::AArch64CallLowering::lowerReturn().
◆ getRoundingControlRegisters()
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
Reimplemented from llvm::TargetLowering.
Definition at line 17936 of file AArch64ISelLowering.cpp.
◆ getSafeStackPointerLocation()
|
overridevirtual |
If the target has a standard location for the unsafe stack pointer, returns the address of that location.
Otherwise, returns nullptr.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27301 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::getSafeStackPointerLocation(), llvm::AArch64Subtarget::isTargetAndroid(), llvm::AArch64Subtarget::isTargetFuchsia(), and UseTlsOffset().
◆ getScalarShiftAmountTy()
|
overridevirtual |
Return the type to use for a scalar shift opcode, given the shifted amount type.
Targets should return a legal type if the input type is legal. Targets can return a type that is too small if the input type is illegal.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2488 of file AArch64ISelLowering.cpp.
◆ getScratchRegisters()
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overridevirtual |
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Reimplemented from llvm::TargetLowering.
Definition at line 17926 of file AArch64ISelLowering.cpp.
◆ getSDagStackGuard()
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27286 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::getSDagStackGuard(), llvm::AArch64Subtarget::getTargetTriple(), and llvm::Triple::isWindowsMSVCEnvironment().
◆ getSetCCResultType()
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overridevirtual |
Return the ISD::SETCC ValueType.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2161 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::C, llvm::EVT::changeVectorElementTypeToInteger(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::EVT::isScalableVector(), and llvm::EVT::isVector().
◆ getSSPStackGuardCheck()
If the target has a standard stack protection check function that performs validation and error handling, returns the function.
Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27293 of file AArch64ISelLowering.cpp.
References llvm::AArch64Subtarget::getSecurityCheckCookieName(), llvm::TargetLoweringBase::getSSPStackGuardCheck(), llvm::AArch64Subtarget::getTargetTriple(), and llvm::Triple::isWindowsMSVCEnvironment().
◆ getTargetMMOFlags()
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overridevirtual |
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them.
The default implementation does nothing.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16877 of file AArch64ISelLowering.cpp.
References FALKOR_STRIDED_ACCESS_MD, llvm::AArch64Subtarget::getProcFamily(), I, llvm::MachineMemOperand::MONone, and llvm::MOStridedAccess.
◆ getTargetNodeName()
This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 2549 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ABDS_PRED, llvm::AArch64ISD::ABDU_PRED, llvm::AArch64ISD::ABS_MERGE_PASSTHRU, llvm::AArch64ISD::ADC, llvm::AArch64ISD::ADCS, llvm::AArch64ISD::ADDlow, llvm::AArch64ISD::ADDP, llvm::AArch64ISD::ADDS, llvm::AArch64ISD::ADR, llvm::AArch64ISD::ADRP, llvm::AArch64ISD::ALLOCATE_ZA_BUFFER, llvm::AArch64ISD::ANDS, llvm::AArch64ISD::ANDV_PRED, llvm::AArch64ISD::ASSERT_ZEXT_BOOL, llvm::AArch64ISD::AUTH_CALL, llvm::AArch64ISD::AUTH_CALL_RVMARKER, llvm::AArch64ISD::AUTH_TC_RETURN, llvm::AArch64ISD::BIC, llvm::AArch64ISD::BICi, llvm::AArch64ISD::BITREVERSE_MERGE_PASSTHRU, llvm::AArch64ISD::BRCOND, llvm::AArch64ISD::BSP, llvm::AArch64ISD::BSWAP_MERGE_PASSTHRU, llvm::AArch64ISD::CALL, llvm::AArch64ISD::CALL_ARM64EC_TO_X64, llvm::AArch64ISD::CALL_BTI, llvm::AArch64ISD::CALL_RVMARKER, llvm::AArch64ISD::CBNZ, llvm::AArch64ISD::CBZ, llvm::AArch64ISD::CCMN, llvm::AArch64ISD::CCMP, llvm::AArch64ISD::CLASTA_N, llvm::AArch64ISD::CLASTB_N, llvm::AArch64ISD::CMEQ, llvm::AArch64ISD::CMEQz, llvm::AArch64ISD::CMGE, llvm::AArch64ISD::CMGEz, llvm::AArch64ISD::CMGT, llvm::AArch64ISD::CMGTz, llvm::AArch64ISD::CMHI, llvm::AArch64ISD::CMHS, llvm::AArch64ISD::CMLEz, llvm::AArch64ISD::CMLTz, llvm::AArch64ISD::COALESCER_BARRIER, llvm::AArch64ISD::CSEL, llvm::AArch64ISD::CSINC, llvm::AArch64ISD::CSINV, llvm::AArch64ISD::CSNEG, llvm::AArch64ISD::CTLZ_MERGE_PASSTHRU, llvm::AArch64ISD::CTPOP_MERGE_PASSTHRU, llvm::AArch64ISD::CTTZ_ELTS, llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUP_MERGE_PASSTHRU, llvm::AArch64ISD::DUPLANE128, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::AArch64ISD::EORV_PRED, llvm::AArch64ISD::EXT, llvm::AArch64ISD::FABS_MERGE_PASSTHRU, llvm::AArch64ISD::FADD_PRED, llvm::AArch64ISD::FADDA_PRED, llvm::AArch64ISD::FADDV_PRED, llvm::AArch64ISD::FCCMP, llvm::AArch64ISD::FCEIL_MERGE_PASSTHRU, llvm::AArch64ISD::FCMEQ, llvm::AArch64ISD::FCMEQz, llvm::AArch64ISD::FCMGE, llvm::AArch64ISD::FCMGEz, llvm::AArch64ISD::FCMGT, llvm::AArch64ISD::FCMGTz, llvm::AArch64ISD::FCMLEz, llvm::AArch64ISD::FCMLTz, llvm::AArch64ISD::FCMP, llvm::AArch64ISD::FCVTXN, llvm::AArch64ISD::FCVTZS_MERGE_PASSTHRU, llvm::AArch64ISD::FCVTZU_MERGE_PASSTHRU, llvm::AArch64ISD::FDIV_PRED, llvm::AArch64ISD::FFLOOR_MERGE_PASSTHRU, llvm::AArch64ISD::FIRST_NUMBER, llvm::AArch64ISD::FMA_PRED, llvm::AArch64ISD::FMAX_PRED, llvm::AArch64ISD::FMAXNM_PRED, llvm::AArch64ISD::FMAXNMV_PRED, llvm::AArch64ISD::FMAXV_PRED, llvm::AArch64ISD::FMIN_PRED, llvm::AArch64ISD::FMINNM_PRED, llvm::AArch64ISD::FMINNMV_PRED, llvm::AArch64ISD::FMINV_PRED, llvm::AArch64ISD::FMOV, llvm::AArch64ISD::FMUL_PRED, llvm::AArch64ISD::FNEARBYINT_MERGE_PASSTHRU, llvm::AArch64ISD::FNEG_MERGE_PASSTHRU, llvm::AArch64ISD::FP_EXTEND_MERGE_PASSTHRU, llvm::AArch64ISD::FP_ROUND_MERGE_PASSTHRU, llvm::AArch64ISD::FRECPE, llvm::AArch64ISD::FRECPS, llvm::AArch64ISD::FRECPX_MERGE_PASSTHRU, llvm::AArch64ISD::FRINT_MERGE_PASSTHRU, llvm::AArch64ISD::FROUND_MERGE_PASSTHRU, llvm::AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU, llvm::AArch64ISD::FRSQRTE, llvm::AArch64ISD::FRSQRTS, llvm::AArch64ISD::FSQRT_MERGE_PASSTHRU, llvm::AArch64ISD::FSUB_PRED, llvm::AArch64ISD::FTRUNC_MERGE_PASSTHRU, llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1Q_INDEX_MERGE_ZERO, llvm::AArch64ISD::GLD1Q_MERGE_ZERO, llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1S_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_INDEX_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::AArch64ISD::GLDNT1S_MERGE_ZERO, llvm::AArch64ISD::HADDS_PRED, llvm::AArch64ISD::HADDU_PRED, llvm::AArch64ISD::INDEX_VECTOR, llvm::AArch64ISD::INIT_TPIDR2OBJ, llvm::AArch64ISD::INSR, llvm::AArch64ISD::LASTA, llvm::AArch64ISD::LASTB, llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LD1DUPpost, llvm::AArch64ISD::LD1LANEpost, llvm::AArch64ISD::LD1RO_MERGE_ZERO, llvm::AArch64ISD::LD1RQ_MERGE_ZERO, llvm::AArch64ISD::LD1S_MERGE_ZERO, llvm::AArch64ISD::LD1x2post, llvm::AArch64ISD::LD1x3post, llvm::AArch64ISD::LD1x4post, llvm::AArch64ISD::LD2DUPpost, llvm::AArch64ISD::LD2LANEpost, llvm::AArch64ISD::LD2post, llvm::AArch64ISD::LD3DUPpost, llvm::AArch64ISD::LD3LANEpost, llvm::AArch64ISD::LD3post, llvm::AArch64ISD::LD4DUPpost, llvm::AArch64ISD::LD4LANEpost, llvm::AArch64ISD::LD4post, llvm::AArch64ISD::LDFF1_MERGE_ZERO, llvm::AArch64ISD::LDFF1S_MERGE_ZERO, llvm::AArch64ISD::LDIAPP, llvm::AArch64ISD::LDNF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1S_MERGE_ZERO, llvm::AArch64ISD::LDNP, llvm::AArch64ISD::LDP, llvm::AArch64ISD::LOADgot, llvm::AArch64ISD::LS64_BUILD, llvm::AArch64ISD::LS64_EXTRACT, MAKE_CASE, llvm::AArch64ISD::MOPS_MEMCOPY, llvm::AArch64ISD::MOPS_MEMMOVE, llvm::AArch64ISD::MOPS_MEMSET, llvm::AArch64ISD::MOPS_MEMSET_TAGGING, llvm::AArch64ISD::MOVI, llvm::AArch64ISD::MOVIedit, llvm::AArch64ISD::MOVImsl, llvm::AArch64ISD::MOVIshift, llvm::AArch64ISD::MRRS, llvm::AArch64ISD::MRS, llvm::AArch64ISD::MSRR, llvm::AArch64ISD::MUL_PRED, llvm::AArch64ISD::MULHS_PRED, llvm::AArch64ISD::MULHU_PRED, llvm::AArch64ISD::MVNImsl, llvm::AArch64ISD::MVNIshift, llvm::AArch64ISD::NEG_MERGE_PASSTHRU, llvm::AArch64ISD::NVCAST, llvm::AArch64ISD::ORRi, llvm::AArch64ISD::ORV_PRED, llvm::AArch64ISD::PMULL, llvm::AArch64ISD::PREFETCH, llvm::AArch64ISD::PROBED_ALLOCA, llvm::AArch64ISD::PTEST, llvm::AArch64ISD::PTEST_ANY, llvm::AArch64ISD::PTRUE, llvm::AArch64ISD::RDSVL, llvm::AArch64ISD::REINTERPRET_CAST, llvm::AArch64ISD::RESTORE_ZA, llvm::AArch64ISD::RESTORE_ZT, llvm::AArch64ISD::RET_GLUE, llvm::AArch64ISD::REV16, llvm::AArch64ISD::REV32, llvm::AArch64ISD::REV64, llvm::AArch64ISD::REVD_MERGE_PASSTHRU, llvm::AArch64ISD::REVH_MERGE_PASSTHRU, llvm::AArch64ISD::REVW_MERGE_PASSTHRU, llvm::AArch64ISD::RHADDS_PRED, llvm::AArch64ISD::RHADDU_PRED, llvm::AArch64ISD::RSHRNB_I, llvm::AArch64ISD::SADDLP, llvm::AArch64ISD::SADDLV, llvm::AArch64ISD::SADDV, llvm::AArch64ISD::SADDV_PRED, llvm::AArch64ISD::SAVE_ZT, llvm::AArch64ISD::SBC, llvm::AArch64ISD::SBCS, llvm::AArch64ISD::SDIV_PRED, llvm::AArch64ISD::SDOT, llvm::AArch64ISD::SETCC_MERGE_ZERO, llvm::AArch64ISD::SHL_PRED, llvm::AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, llvm::AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU, llvm::AArch64ISD::SITOF, llvm::AArch64ISD::SMAX_PRED, llvm::AArch64ISD::SMAXV, llvm::AArch64ISD::SMAXV_PRED, llvm::AArch64ISD::SME_ZA_LDR, llvm::AArch64ISD::SME_ZA_STR, llvm::AArch64ISD::SMIN_PRED, llvm::AArch64ISD::SMINV, llvm::AArch64ISD::SMINV_PRED, llvm::AArch64ISD::SMSTART, llvm::AArch64ISD::SMSTOP, llvm::AArch64ISD::SMULL, llvm::AArch64ISD::SPLICE, llvm::AArch64ISD::SQSHL_I, llvm::AArch64ISD::SQSHLU_I, llvm::AArch64ISD::SRA_PRED, llvm::AArch64ISD::SRAD_MERGE_OP1, llvm::AArch64ISD::SRL_PRED, llvm::AArch64ISD::SRSHR_I, llvm::AArch64ISD::SST1_IMM_PRED, llvm::AArch64ISD::SST1_PRED, llvm::AArch64ISD::SST1_SCALED_PRED, llvm::AArch64ISD::SST1_SXTW_PRED, llvm::AArch64ISD::SST1_SXTW_SCALED_PRED, llvm::AArch64ISD::SST1_UXTW_PRED, llvm::AArch64ISD::SST1_UXTW_SCALED_PRED, llvm::AArch64ISD::SST1Q_INDEX_PRED, llvm::AArch64ISD::SST1Q_PRED, llvm::AArch64ISD::SSTNT1_INDEX_PRED, llvm::AArch64ISD::SSTNT1_PRED, llvm::AArch64ISD::ST1_PRED, llvm::AArch64ISD::ST1x2post, llvm::AArch64ISD::ST1x3post, llvm::AArch64ISD::ST1x4post, llvm::AArch64ISD::ST2G, llvm::AArch64ISD::ST2LANEpost, llvm::AArch64ISD::ST2post, llvm::AArch64ISD::ST3LANEpost, llvm::AArch64ISD::ST3post, llvm::AArch64ISD::ST4LANEpost, llvm::AArch64ISD::ST4post, llvm::AArch64ISD::STG, llvm::AArch64ISD::STILP, llvm::AArch64ISD::STNP, llvm::AArch64ISD::STP, llvm::AArch64ISD::STRICT_FCMP, llvm::AArch64ISD::STRICT_FCMPE, llvm::AArch64ISD::STZ2G, llvm::AArch64ISD::STZG, llvm::AArch64ISD::SUBS, llvm::AArch64ISD::SUNPKHI, llvm::AArch64ISD::SUNPKLO, llvm::AArch64ISD::SVE_LD2_MERGE_ZERO, llvm::AArch64ISD::SVE_LD3_MERGE_ZERO, llvm::AArch64ISD::SVE_LD4_MERGE_ZERO, llvm::AArch64ISD::TBL, llvm::AArch64ISD::TBNZ, llvm::AArch64ISD::TBZ, llvm::AArch64ISD::TC_RETURN, llvm::AArch64ISD::THREAD_POINTER, llvm::AArch64ISD::TLSDESC_CALLSEQ, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, llvm::AArch64ISD::UADDLP, llvm::AArch64ISD::UADDLV, llvm::AArch64ISD::UADDV, llvm::AArch64ISD::UADDV_PRED, llvm::AArch64ISD::UDIV_PRED, llvm::AArch64ISD::UDOT, llvm::AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU, llvm::AArch64ISD::UITOF, llvm::AArch64ISD::UMAX_PRED, llvm::AArch64ISD::UMAXV, llvm::AArch64ISD::UMAXV_PRED, llvm::AArch64ISD::UMIN_PRED, llvm::AArch64ISD::UMINV, llvm::AArch64ISD::UMINV_PRED, llvm::AArch64ISD::UMULL, llvm::AArch64ISD::UQSHL_I, llvm::AArch64ISD::URSHR_I, llvm::AArch64ISD::URSHR_I_PRED, llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, llvm::AArch64ISD::VASHR, llvm::AArch64ISD::VG_RESTORE, llvm::AArch64ISD::VG_SAVE, llvm::AArch64ISD::VLSHR, llvm::AArch64ISD::VSHL, llvm::AArch64ISD::VSLI, llvm::AArch64ISD::VSRI, llvm::AArch64ISD::WrapperLarge, llvm::AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU, llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.
◆ getTgtMemIntrinsic()
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overridevirtual |
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
The associated MachineMemOperands record the alignment specified in the intrinsic calls.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 15784 of file AArch64ISelLowering.cpp.
References DL, llvm::Value::getType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::MVT::getVT(), I, Info, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::Type::isVectorTy(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MONonTemporal, llvm::MachineMemOperand::MOStore, llvm::MachineMemOperand::MOVolatile, RetTy, and llvm::MemoryLocation::UnknownSize.
◆ getVaListSizeInBits()
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overridevirtual |
Returns the size of the platform's va_list object.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27461 of file AArch64ISelLowering.cpp.
References DL, getPointerTy(), llvm::MVT::getSizeInBits(), llvm::AArch64Subtarget::isTargetDarwin(), and llvm::AArch64Subtarget::isTargetWindows().
◆ getVectorTypeBreakdownForCallingConv()
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overridevirtual |
Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.
This occurs even if the vector type is legal.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 29166 of file AArch64ISelLowering.cpp.
References assert(), CC, llvm::ElementCount::getFixed(), llvm::MVT::getFixedSizeInBits(), llvm::TargetLoweringBase::getRegisterType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::TargetLoweringBase::getVectorTypeBreakdownForCallingConv(), llvm::EVT::getVectorVT(), llvm::MVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::MVT::SimpleTy, and llvm::AArch64Subtarget::useSVEForFixedLengthVectors().
Referenced by getNumRegistersForCallingConv(), and getRegisterTypeForCallingConv().
◆ hasAndNot()
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 876 of file AArch64ISelLowering.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::EVT::getSizeInBits(), hasAndNotCompare(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::EVT::isVector(), and Y.
◆ hasAndNotCompare()
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.
This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant.
Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 —> (X & 8) != 0
Reimplemented from llvm::TargetLoweringBase.
Definition at line 871 of file AArch64ISelLowering.h.
Referenced by hasAndNot().
◆ hasInlineStackProbe()
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overridevirtual |
True if stack clash protection is enabled for this functions.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 29232 of file AArch64ISelLowering.cpp.
References llvm::MachineFunction::getInfo(), and llvm::AArch64Subtarget::isTargetWindows().
Referenced by llvm::AArch64FrameLowering::canUseAsPrologue(), and llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr().
◆ hasPairedLoad()
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.
RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.
This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).
In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16853 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), and llvm::EVT::isSimple().
◆ initializeSplitCSR()
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overridevirtual |
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
This function is called at the beginning of instruction selection.
Reimplemented from llvm::TargetLowering.
Definition at line 27352 of file AArch64ISelLowering.cpp.
References llvm::AArch64FunctionInfo::setIsSplitCSR().
◆ insertCopiesSplitCSR()
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overridevirtual |
Insert explicit copies in entry and exit blocks.
We copy a subset of CSRs to virtual registers in the entry block, and copy them back to physical registers in the exit blocks. This function is called at the end of instruction selection.
Reimplemented from llvm::TargetLowering.
Definition at line 27358 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), llvm::AArch64Subtarget::getInstrInfo(), llvm::AArch64Subtarget::getRegisterInfo(), I, llvm_unreachable, MBBI, MRI, TII, and TRI.
◆ insertSSPDeclarations()
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overridevirtual |
Inserts necessary declarations for SSP (stack protection) purpose.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27265 of file AArch64ISelLowering.cpp.
References F, llvm::FunctionCallee::getCallee(), llvm::AArch64Subtarget::getSecurityCheckCookieName(), llvm::AArch64Subtarget::getTargetTriple(), llvm::PointerType::getUnqual(), llvm::Type::getVoidTy(), llvm::TargetLoweringBase::insertSSPDeclarations(), llvm::Triple::isWindowsMSVCEnvironment(), and llvm::CallingConv::Win64.
◆ isAllActivePredicate()
| bool AArch64TargetLowering::isAllActivePredicate | ( | SelectionDAG & | DAG, |
| SDValue | N | ||
| ) | const |
Definition at line 28890 of file AArch64ISelLowering.cpp.
References N.
◆ isCheapToSpeculateCtlz()
Return true if it is cheap to speculate a call to intrinsic ctlz.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 865 of file AArch64ISelLowering.h.
◆ isCheapToSpeculateCttz()
Return true if it is cheap to speculate a call to intrinsic cttz.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 861 of file AArch64ISelLowering.h.
◆ isComplexDeinterleavingOperationSupported()
|
overridevirtual |
Does this target support complex deinterleaving with the given operation and type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 28992 of file AArch64ISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), and llvm::isPowerOf2_32().
◆ isComplexDeinterleavingSupported()
|
overridevirtual |
Does this target support complex deinterleaving.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 28987 of file AArch64ISelLowering.cpp.
◆ isDesirableToCommuteWithShift()
|
overridevirtual |
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
Reimplemented from llvm::TargetLowering.
Definition at line 17942 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isMask_64(), N, llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.
◆ isDesirableToCommuteXorWithShift()
|
overridevirtual |
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
Reimplemented from llvm::TargetLowering.
Definition at line 17972 of file AArch64ISelLowering.cpp.
References assert(), llvm::BitWidth, N, llvm::ISD::SHL, llvm::ISD::SRL, and llvm::ISD::XOR.
◆ isDesirableToPullExtFromShl()
|
inlineoverridevirtual |
GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x), y => zext (shl x, y)
Reimplemented from llvm::TargetLowering.
Definition at line 760 of file AArch64ISelLowering.h.
◆ isExtractSubvectorCheap()
|
overridevirtual |
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 18045 of file AArch64ISelLowering.cpp.
References llvm::ISD::EXTRACT_SUBVECTOR, llvm::EVT::getVectorMinNumElements(), and llvm::TargetLoweringBase::isOperationLegalOrCustom().
◆ isFMAFasterThanFMulAndFAdd() [1/2]
|
overridevirtual |
IR version.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17908 of file AArch64ISelLowering.cpp.
References llvm::Type::DoubleTyID, llvm::Type::FloatTyID, llvm::Type::getScalarType(), and llvm::Type::getTypeID().
◆ isFMAFasterThanFMulAndFAdd() [2/2]
|
overridevirtual |
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17888 of file AArch64ISelLowering.cpp.
References llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.
Referenced by isProfitableToHoist().
◆ isFPImmLegal()
|
overridevirtual |
Returns true if the target can instruction select the specified FP immediate natively.
If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 11417 of file AArch64ISelLowering.cpp.
References llvm::dbgs(), llvm::AArch64_IMM::expandMOVImm(), llvm::AArch64_AM::getFP16Imm(), llvm::AArch64_AM::getFP32Imm(), llvm::AArch64_AM::getFP64Imm(), llvm::EVT::getSizeInBits(), llvm::APInt::getZExtValue(), Insn, and LLVM_DEBUG.
◆ isIntDivCheap()
|
overridevirtual |
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
The definition of "cheaper" may depend on whether we're optimizing for speed or for size.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27399 of file AArch64ISelLowering.cpp.
References llvm::AttributeList::hasFnAttr(), and llvm::EVT::isVector().
◆ isLegalAddImmediate()
|
overridevirtual |
Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17709 of file AArch64ISelLowering.cpp.
References llvm::dbgs(), and LLVM_DEBUG.
Referenced by getPreferredLargeGEPBaseOffset(), isLegalICmpImmediate(), and isMulAddWithConstProfitable().
◆ isLegalAddressingMode()
|
overridevirtual |
Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17793 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, DL, llvm::AArch64Subtarget::getInstrInfo(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::AArch64InstrInfo::isLegalAddressingMode(), llvm::isPowerOf2_64(), llvm::Type::isScalableTy(), llvm::Type::isSized(), llvm::TargetLoweringBase::AddrMode::ScalableOffset, and llvm::TargetLoweringBase::AddrMode::Scale.
◆ isLegalAddScalableImmediate()
|
overridevirtual |
Return true if adding the specified scalable immediate is legal, that is the target has add instructions which can add a register with the immediate (multiplied by vscale) without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17724 of file AArch64ISelLowering.cpp.
◆ isLegalICmpImmediate()
|
overridevirtual |
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17787 of file AArch64ISelLowering.cpp.
References isLegalAddImmediate().
◆ isLegalInterleavedAccessType()
| bool AArch64TargetLowering::isLegalInterleavedAccessType | ( | VectorType * | VecTy, |
| const DataLayout & | DL, | ||
| bool & | UseScalable | ||
| ) | const |
Returns true if VecTy is a legal interleaved access type.
This function checks the vector element type and the overall width of the vector.
Definition at line 16884 of file AArch64ISelLowering.cpp.
References DL, llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), llvm::getSVEPredPatternFromNumElements(), llvm::AArch64Subtarget::isNeonAvailable(), llvm::isPowerOf2_32(), llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), and llvm::AArch64Subtarget::useSVEForFixedLengthVectors().
Referenced by llvm::AArch64TTIImpl::getInterleavedMemoryOpCost(), lowerDeinterleaveIntrinsicToLoad(), lowerInterleavedLoad(), lowerInterleavedStore(), and lowerInterleaveIntrinsicToStore().
◆ isMaskAndCmp0FoldingBeneficial()
|
overridevirtual |
Return if the target supports combining a chain like:
into a single machine instruction of a form like:
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27316 of file AArch64ISelLowering.cpp.
References llvm::User::getOperand().
◆ isMulAddWithConstProfitable()
|
overridevirtual |
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
This may not be true if c1 and c2 can be represented as immediates but c1*c2 cannot, for example. The target should check if c1, c2 and c1*c2 can be represented as immediates, or have to be materialized into registers. If it is not sure about some cases, a default true can be returned to let the DAGCombiner decide. AddNode is (add x, c1), and ConstNode is c2.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17759 of file AArch64ISelLowering.cpp.
References llvm::AArch64_IMM::expandMOVImm(), llvm::ConstantSDNode::getAPIntValue(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::APInt::getSExtValue(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), Insn, isLegalAddImmediate(), and llvm::EVT::isVector().
◆ isOffsetFoldingLegal()
|
overridevirtual |
Return true if folding a constant offset with the given GlobalAddress is legal.
It is frequently not legal in PIC relocation models.
Reimplemented from llvm::TargetLowering.
Definition at line 11410 of file AArch64ISelLowering.cpp.
◆ isOpSuitableForLDPSTP()
| bool AArch64TargetLowering::isOpSuitableForLDPSTP | ( | const Instruction * | I | ) | const |
Definition at line 26924 of file AArch64ISelLowering.cpp.
References I.
Referenced by shouldExpandAtomicLoadInIR(), shouldExpandAtomicStoreInIR(), and shouldInsertFencesForAtomic().
◆ isOpSuitableForLSE128()
| bool AArch64TargetLowering::isOpSuitableForLSE128 | ( | const Instruction * | I | ) | const |
Definition at line 26939 of file AArch64ISelLowering.cpp.
References llvm::AtomicRMWInst::And, I, llvm::AtomicRMWInst::Or, llvm::Release, llvm::SequentiallyConsistent, and llvm::AtomicRMWInst::Xchg.
Referenced by shouldExpandAtomicStoreInIR(), and shouldInsertFencesForAtomic().
◆ isOpSuitableForRCPC3()
| bool AArch64TargetLowering::isOpSuitableForRCPC3 | ( | const Instruction * | I | ) | const |
Definition at line 26961 of file AArch64ISelLowering.cpp.
References llvm::Acquire, I, and llvm::Release.
Referenced by shouldExpandAtomicLoadInIR(), shouldExpandAtomicStoreInIR(), and shouldInsertFencesForAtomic().
◆ isProfitableToHoist()
|
overridevirtual |
Check if it is profitable to hoist instruction in then/else to if.
Not profitable if I and it's user can form a FMA instruction because we prefer FMSUB/FMADD.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16029 of file AArch64ISelLowering.cpp.
References DL, F, llvm::FPOpFusion::Fast, llvm::ISD::FMA, llvm::User::getOperand(), llvm::TargetLoweringBase::getTargetMachine(), llvm::Value::getType(), llvm::TargetLoweringBase::getValueType(), I, isFMAFasterThanFMulAndFAdd(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetMachine::Options, and Options.
◆ isReassocProfitable()
|
overridevirtual |
Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y), c1) where N0 is (op x, c1) and N1 is y.
Reimplemented from llvm::TargetLowering.
Definition at line 7307 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, getIntrinsicID(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::hasOneUse(), llvm::AArch64ISD::SMULL, and llvm::AArch64ISD::UMULL.
◆ isShuffleMaskLegal()
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 15007 of file AArch64ISelLowering.cpp.
References llvm::getPerfectShuffleCost(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isConcatMask(), isEXTMask(), isINSMask(), llvm::AArch64Subtarget::isNeonAvailable(), llvm::isREVMask(), llvm::ShuffleVectorSDNode::isSplatMask(), isTRN_v_undef_Mask(), llvm::isTRNMask(), isUZP_v_undef_Mask(), llvm::isUZPMask(), isZIP_v_undef_Mask(), llvm::isZIPMask(), and useSVEForFixedLengthVectorVT().
Referenced by isVectorClearMaskLegal(), and ReconstructShuffle().
◆ isTruncateFree() [1/2]
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16018 of file AArch64ISelLowering.cpp.
References llvm::EVT::getFixedSizeInBits(), llvm::EVT::isInteger(), and llvm::EVT::isVector().
◆ isTruncateFree() [2/2]
Return true if it's free to truncate a value of type FromTy to type ToTy.
e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX. Targets must return false when FromTy <= ToTy.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16011 of file AArch64ISelLowering.cpp.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().
◆ isTypeDesirableForOp()
Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type.
Reimplemented from llvm::TargetLowering.
Definition at line 29238 of file AArch64ISelLowering.cpp.
References llvm::TargetLowering::isTypeDesirableForOp(), llvm::ISD::TRUNCATE_SSAT_S, llvm::ISD::TRUNCATE_SSAT_U, and llvm::ISD::TRUNCATE_USAT_U.
◆ isVectorClearMaskLegal()
|
overridevirtual |
Similar to isShuffleMaskLegal.
Return true is the given 'select with zero' shuffle mask can be codegen'd directly.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 15040 of file AArch64ISelLowering.cpp.
References isShuffleMaskLegal().
◆ isVScaleKnownToBeAPowerOfTwo()
|
inlineoverridevirtual |
Return true only if vscale must be a power of two.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1011 of file AArch64ISelLowering.h.
◆ isZExtFree() [1/3]
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16062 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::EVT::isInteger(), and llvm::EVT::isVector().
◆ isZExtFree() [2/3]
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16070 of file AArch64ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), isZExtFree(), and llvm::ISD::LOAD.
◆ isZExtFree() [3/3]
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.
The function should return true when it is likely that the truncate can be freely folded with an instruction defining a value of FromTy. If the defining instruction is unknown (because you're looking at a function argument, PHI, etc.) then the target may require an explicit truncate, which is not necessarily free, but this function does not deal with those cases. Targets must return false when FromTy >= ToTy.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16055 of file AArch64ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().
Referenced by isZExtFree().
◆ lowerDeinterleaveIntrinsicToLoad()
|
overridevirtual |
Lower a deinterleave intrinsic to a target specific load intrinsic.
Return true on success. Currently only supports llvm.vector.deinterleave2
DI is the deinterleave intrinsic. LI is the accompanying load instruction DeadInsts is a reference to a vector that keeps track of dead instruction during transformations.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17448 of file AArch64ISelLowering.cpp.
References llvm::Address, assert(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateExtractValue(), llvm::IRBuilderBase::CreateGEP(), llvm::IRBuilderBase::CreateInsertVector(), llvm::IRBuilderBase::CreateVectorSplat(), llvm::dbgs(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), DL, llvm::Value::dump(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::VectorType::get(), llvm::PoisonValue::get(), llvm::Module::getDataLayout(), getDeinterleavedValues(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), llvm::IRBuilderBase::getInt64(), llvm::IntrinsicInst::getIntrinsicID(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::Instruction::getModule(), getNumInterleavedAccesses(), llvm::LoadInst::getPointerOperand(), llvm::LoadInst::getPointerOperandType(), getStructuredLoadFunction(), llvm::IRBuilderBase::getTrue(), getType(), I, Idx, llvm::SmallVectorImpl< T >::insert(), isLegalInterleavedAccessType(), llvm::Type::isScalableTy(), LLVM_DEBUG, llvm::Offset, replaceAllUsesWith(), and llvm::SmallVectorBase< Size_T >::size().
◆ lowerInterleavedLoad()
|
overridevirtual |
Lower an interleaved load into a ldN intrinsic.
E.g. Lower an interleaved load (Factor = 2): wide.vec = load <8 x i32>, <8 x i32>* ptr v0 = shuffle wide.vec, undef, <0, 2, 4, 6> ; Extract even elements v1 = shuffle wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
Into: ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(ptr) vec0 = extractelement { <4 x i32>, <4 x i32> } ld2, i32 0 vec1 = extractelement { <4 x i32>, <4 x i32> } ld2, i32 1
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17002 of file AArch64ISelLowering.cpp.
References assert(), llvm::concatenateVectors(), llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::IRBuilderBase::CreateExtractValue(), llvm::IRBuilderBase::CreateExtractVector(), llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreateIntToPtr(), DL, llvm::ArrayRef< T >::empty(), llvm::VectorType::get(), llvm::FixedVectorType::get(), llvm::Type::getContext(), llvm::Instruction::getDataLayout(), llvm::VectorType::getElementType(), llvm::Type::getInt1Ty(), llvm::Type::getInt32Ty(), llvm::Type::getInt64Ty(), getMaxSupportedInterleaveFactor(), llvm::AArch64Subtarget::getMaxSVEVectorSizeInBits(), llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), llvm::Instruction::getModule(), getNumInterleavedAccesses(), llvm::LoadInst::getPointerOperand(), llvm::LoadInst::getPointerOperandType(), getStructuredLoadFunction(), getSVEContainerIRType(), llvm::getSVEPredPatternFromNumElements(), llvm::ShuffleVectorInst::getType(), isLegalInterleavedAccessType(), llvm::Type::isPointerTy(), and llvm::ArrayRef< T >::size().
◆ lowerInterleavedStore()
|
overridevirtual |
Lower an interleaved store into a stN intrinsic.
E.g. Lower an interleaved store (Factor = 3): i.vec = shuffle <8 x i32> v0, <8 x i32> v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> i.vec, <12 x i32>* ptr
Into: sub.v0 = shuffle <8 x i32> v0, <8 x i32> v1, <0, 1, 2, 3> sub.v1 = shuffle <8 x i32> v0, <8 x i32> v1, <4, 5, 6, 7> sub.v2 = shuffle <8 x i32> v0, <8 x i32> v1, <8, 9, 10, 11> call void llvm.aarch64.neon.st3(sub.v0, sub.v1, sub.v2, ptr)
Note that the new shufflevectors will be removed and we'll only generate one st3 instruction in CodeGen.
Example for a more general valid mask (Factor 3). Lower: i.vec = shuffle <32 x i32> v0, <32 x i32> v1, <4, 32, 16, 5, 33, 17, 6, 34, 18, 7, 35, 19> store <12 x i32> i.vec, <12 x i32>* ptr
Into: sub.v0 = shuffle <32 x i32> v0, <32 x i32> v1, <4, 5, 6, 7> sub.v1 = shuffle <32 x i32> v0, <32 x i32> v1, <32, 33, 34, 35> sub.v2 = shuffle <32 x i32> v0, <32 x i32> v1, <16, 17, 18, 19> call void llvm.aarch64.neon.st3(sub.v0, sub.v1, sub.v2, ptr)
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17176 of file AArch64ISelLowering.cpp.
References llvm::all_of(), assert(), llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::IRBuilderBase::CreateInsertVector(), llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreatePtrToInt(), llvm::createSequentialMask(), llvm::IRBuilderBase::CreateShuffleVector(), DL, llvm::VectorType::get(), llvm::FixedVectorType::get(), llvm::UndefValue::get(), llvm::Type::getInt1Ty(), llvm::Type::getInt32Ty(), llvm::Type::getInt64Ty(), getMaxSupportedInterleaveFactor(), llvm::AArch64Subtarget::getMaxSVEVectorSizeInBits(), llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), getNumInterleavedAccesses(), llvm::User::getOperand(), llvm::ShuffleVectorInst::getShuffleMask(), getStructuredStoreFunction(), getSVEContainerIRType(), llvm::getSVEPredPatternFromNumElements(), llvm::ShuffleVectorInst::getType(), llvm::Value::getType(), hasNearbyPairedStore(), Idx, isLegalInterleavedAccessType(), llvm::Type::isPointerTy(), llvm::PoisonMaskElem, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ lowerInterleaveIntrinsicToStore()
|
overridevirtual |
Lower an interleave intrinsic to a target specific store intrinsic.
Return true on success. Currently only supports llvm.vector.interleave2
II is the interleave intrinsic. SI is the accompanying store instruction DeadInsts is a reference to a vector that keeps track of dead instruction during transformations.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17576 of file AArch64ISelLowering.cpp.
References llvm::Address, assert(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateExtractVector(), llvm::IRBuilderBase::CreateGEP(), llvm::IRBuilderBase::CreateVectorSplat(), llvm::dbgs(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), DL, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::VectorType::get(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), llvm::IRBuilderBase::getInt64(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getNumInterleavedAccesses(), getStructuredStoreFunction(), llvm::IRBuilderBase::getTrue(), getType(), getValuesToInterleave(), I, Idx, II, llvm::SmallVectorImpl< T >::insert(), isLegalInterleavedAccessType(), llvm::Type::isScalableTy(), LLVM_DEBUG, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorBase< Size_T >::size().
◆ LowerOperation()
|
overridevirtual |
Provide custom lowering hooks for some operations.
Reimplemented from llvm::TargetLowering.
Definition at line 6891 of file AArch64ISelLowering.cpp.
References llvm::ISD::ABDS, llvm::AArch64ISD::ABDS_PRED, llvm::ISD::ABDU, llvm::AArch64ISD::ABDU_PRED, llvm::ISD::ABS, llvm::AArch64ISD::ADCS, llvm::ISD::ADD, llvm::ISD::ADDROFRETURNADDR, llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_STORE, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BRIND, llvm::ISD::BSWAP, llvm::AArch64ISD::BSWAP_MERGE_PASSTHRU, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::AArch64ISD::CTLZ_MERGE_PASSTHRU, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::dbgs(), DL, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EXPERIMENTAL_VECTOR_HISTOGRAM, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::AArch64ISD::FABS_MERGE_PASSTHRU, llvm::ISD::FADD, llvm::AArch64ISD::FADD_PRED, llvm::ISD::FCEIL, llvm::AArch64ISD::FCEIL_MERGE_PASSTHRU, llvm::ISD::FCOPYSIGN, llvm::ISD::FDIV, llvm::AArch64ISD::FDIV_PRED, llvm::ISD::FFLOOR, llvm::AArch64ISD::FFLOOR_MERGE_PASSTHRU, llvm::ISD::FLDEXP, llvm::ISD::FMA, llvm::AArch64ISD::FMA_PRED, llvm::AArch64ISD::FMAX_PRED, llvm::ISD::FMAXIMUM, llvm::AArch64ISD::FMAXNM_PRED, llvm::ISD::FMAXNUM, llvm::AArch64ISD::FMIN_PRED, llvm::ISD::FMINIMUM, llvm::AArch64ISD::FMINNM_PRED, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::AArch64ISD::FMUL_PRED, llvm::ISD::FNEARBYINT, llvm::AArch64ISD::FNEARBYINT_MERGE_PASSTHRU, llvm::ISD::FNEG, llvm::AArch64ISD::FNEG_MERGE_PASSTHRU, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT, llvm::ISD::FP_TO_UINT_SAT, llvm::ISD::FRAMEADDR, llvm::ISD::FRINT, llvm::AArch64ISD::FRINT_MERGE_PASSTHRU, llvm::ISD::FROUND, llvm::AArch64ISD::FROUND_MERGE_PASSTHRU, llvm::ISD::FROUNDEVEN, llvm::AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::ISD::FSINCOS, llvm::ISD::FSQRT, llvm::AArch64ISD::FSQRT_MERGE_PASSTHRU, llvm::ISD::FSUB, llvm::AArch64ISD::FSUB_PRED, llvm::ISD::FTRUNC, llvm::AArch64ISD::FTRUNC_MERGE_PASSTHRU, llvm::ISD::GET_FPMODE, llvm::ISD::GET_ROUNDING, llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::AArch64ISD::HADDS_PRED, llvm::AArch64ISD::HADDU_PRED, llvm::ISD::INIT_TRAMPOLINE, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::AArch64Subtarget::isNeonAvailable(), llvm::ISD::JumpTable, llvm::ISD::LLRINT, llvm::ISD::LLROUND, LLVM_DEBUG, llvm_unreachable, llvm::ISD::LOAD, lowerADDSUBO_CARRY(), LowerBRCOND(), LowerFLDEXP(), LowerFunnelShift(), LowerPREFETCH(), LowerXALUO(), llvm::ISD::LRINT, llvm::ISD::LROUND, llvm::ISD::MGATHER, llvm::ISD::MLOAD, llvm::ISD::MSCATTER, llvm::AArch64ISD::MSRR, llvm::ISD::MSTORE, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::AArch64ISD::MULHS_PRED, llvm::ISD::MULHU, llvm::AArch64ISD::MULHU_PRED, llvm::ISD::OR, llvm::ISD::PARITY, llvm::ISD::PREFETCH, llvm::ISD::PtrAuthGlobalAddress, llvm::ISD::RESET_FPMODE, llvm::ISD::RETURNADDR, llvm::AArch64ISD::RHADDS_PRED, llvm::AArch64ISD::RHADDU_PRED, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::AArch64ISD::SBCS, llvm::ISD::SDIV, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SET_FPMODE, llvm::ISD::SET_ROUNDING, llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, llvm::ISD::SINT_TO_FP, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SPLAT_VECTOR, llvm::SelectionDAG::SplitScalar(), llvm::ISD::SPONENTRY, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::STORE, llvm::ISD::STRICT_FP_EXTEND, llvm::ISD::STRICT_FP_ROUND, llvm::ISD::STRICT_FP_TO_SINT, llvm::ISD::STRICT_FP_TO_UINT, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::STRICT_LLRINT, llvm::ISD::STRICT_LLROUND, llvm::ISD::STRICT_LRINT, llvm::ISD::STRICT_LROUND, llvm::ISD::STRICT_SINT_TO_FP, llvm::ISD::STRICT_UINT_TO_FP, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, useSVEForFixedLengthVectorVT(), llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VASTART, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMAXIMUM, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMINIMUM, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SEQ_FADD, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, llvm::ISD::VECTOR_COMPRESS, llvm::ISD::VECTOR_DEINTERLEAVE, llvm::ISD::VECTOR_INTERLEAVE, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VECTOR_SPLICE, llvm::ISD::VSCALE, llvm::ISD::VSELECT, llvm::ISD::WRITE_REGISTER, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.
◆ mergeStoresAfterLegalization()
SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.
This makes BUILD_VECTOR legalisation a source of stores to merge. However, merging them creates a BUILD_VECTOR that is just as illegal as the original, thus leading to an infinite legalisation loop. NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal vector types this override can be removed.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 7239 of file AArch64ISelLowering.cpp.
References llvm::AArch64Subtarget::useSVEForFixedLengthVectors().
◆ needsFixedCatchObjects()
|
overridevirtual |
Used for exception handling on Win64.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27492 of file AArch64ISelLowering.cpp.
◆ optimizeExtendOrTruncateConversion()
|
overridevirtual |
Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16736 of file AArch64ISelLowering.cpp.
References assert(), llvm::IRBuilderBase::CreateAShr(), llvm::IRBuilderBase::CreateBitCast(), llvm::IRBuilderBase::CreateFPToUI(), llvm::IRBuilderBase::CreateSIToFP(), createTblForTrunc(), createTblShuffleForSExt(), createTblShuffleForZExt(), llvm::IRBuilderBase::CreateTrunc(), llvm::IRBuilderBase::CreateUIToFP(), EnableExtToTBL, F, llvm::TargetTransformInfo::getCastContextHint(), llvm::TargetTransformInfo::getCastInstrCost(), llvm::FixedVectorType::getInteger(), llvm::VectorType::getInteger(), llvm::VectorType::getTruncatedElementVectorType(), I, llvm::AArch64Subtarget::isLittleEndian(), llvm::TargetTransformInfo::TCC_Free, llvm::TargetTransformInfo::TCK_SizeAndLatency, and llvm::AArch64Subtarget::useSVEForFixedLengthVectors().
◆ PerformDAGCombine()
|
overridevirtual |
This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::TargetLowering.
Definition at line 25742 of file AArch64ISelLowering.cpp.
References A, llvm::AArch64ISD::ADC, llvm::AArch64ISD::ADCS, llvm::ISD::ADD, llvm::ISD::AND, llvm::AArch64ISD::ANDS, llvm::ISD::ANY_EXTEND, B, llvm::AArch64ISD::BICi, llvm::AArch64ISD::BRCOND, llvm::AArch64ISD::BSP, llvm::ISD::BUILD_VECTOR, combineSVEPrefetchVecBaseImmOff(), llvm::ISD::CONCAT_VECTORS, llvm::AArch64ISD::CSEL, llvm::AArch64ISD::CSINC, llvm::ISD::CTLZ, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dbgs(), DL, llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUPLANE128, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, foldADCToCINC(), foldOverflowCheck(), llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT, llvm::ISD::FP_TO_UINT_SAT, llvm::APInt::getAllOnes(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1_MERGE_ZERO, llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1Q_INDEX_MERGE_ZERO, llvm::AArch64ISD::GLD1Q_MERGE_ZERO, llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO, llvm::AArch64ISD::GLD1S_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO, llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_INDEX_MERGE_ZERO, llvm::AArch64ISD::GLDNT1_MERGE_ZERO, llvm::ISD::GlobalAddress, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LDFF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1_MERGE_ZERO, legalizeSVEGatherPrefetchOffsVec(), LLVM_DEBUG, llvm::ISD::LOAD, llvm::ISD::MGATHER, llvm::AArch64ISD::MRS, llvm::ISD::MSCATTER, llvm::ISD::MSTORE, llvm::ISD::MUL, N, llvm::AArch64CC::NE, llvm::AArch64ISD::NVCAST, llvm::ISD::OR, performAddSubCombine(), performANDCombine(), performBRCONDCombine(), performBSPExpandForSVE(), performBuildVectorCombine(), performConcatVectorsCombine(), performCSELCombine(), performCTLZCombine(), performDUPCombine(), performDupLane128Combine(), performExtendCombine(), performExtractSubvectorCombine(), performExtractVectorEltCombine(), performFADDCombine(), performFlagSettingCombine(), performFPExtendCombine(), performFpToIntCombine(), performGatherLoadCombine(), performGLD1Combine(), performGlobalAddressCombine(), performInsertSubvectorCombine(), performInsertVectorEltCombine(), performIntrinsicCombine(), performIntToFpCombine(), performLD1Combine(), performLDNT1Combine(), performLOADCombine(), performMaskedGatherScatterCombine(), performMSTORECombine(), performMulCombine(), performMULLCombine(), performNEONPostLDSTCombine(), performNVCASTCombine(), performORCombine(), performReinterpretCastCombine(), performScalarToVectorCombine(), performScatterStoreCombine(), performSelectCombine(), performSETCCCombine(), performSetccMergeZeroCombine(), performSignExtendInRegCombine(), performSpliceCombine(), performST1Combine(), performSTNT1Combine(), performSTORECombine(), performSunpkloCombine(), performTBZCombine(), performTruncateCombine(), performUADDVCombine(), performUnpackCombine(), performUzpCombine(), performVecReduceAddCombine(), performVecReduceBitwiseCombine(), performVectorShiftCombine(), performVSelectCombine(), performXorCombine(), llvm::AArch64ISD::PMULL, llvm::AArch64ISD::REINTERPRET_CAST, llvm::AArch64ISD::RESTORE_ZT, llvm::AArch64ISD::SAVE_ZT, llvm::AArch64ISD::SBC, llvm::AArch64ISD::SBCS, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::AArch64ISD::SETCC_MERGE_ZERO, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::TargetLowering::SimplifyDemandedBits(), llvm::ISD::SINT_TO_FP, llvm::AArch64ISD::SMULL, llvm::AArch64ISD::SPLICE, llvm::AArch64ISD::SST1_IMM_PRED, llvm::AArch64ISD::SST1_PRED, llvm::AArch64ISD::SST1_SCALED_PRED, llvm::AArch64ISD::SST1_SXTW_PRED, llvm::AArch64ISD::SST1_SXTW_SCALED_PRED, llvm::AArch64ISD::SST1_UXTW_PRED, llvm::AArch64ISD::SST1_UXTW_SCALED_PRED, llvm::AArch64ISD::SST1Q_INDEX_PRED, llvm::AArch64ISD::SST1Q_PRED, llvm::AArch64ISD::SSTNT1_INDEX_PRED, llvm::AArch64ISD::SSTNT1_PRED, llvm::ISD::STORE, llvm::ISD::SUB, llvm::AArch64ISD::SUNPKLO, llvm::AArch64ISD::TBNZ, llvm::AArch64ISD::TBZ, llvm::ISD::TRUNCATE, llvm::AArch64ISD::UADDV, llvm::ISD::UINT_TO_FP, llvm::AArch64ISD::UMULL, llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, llvm::AArch64ISD::VASHR, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_XOR, llvm::AArch64ISD::VLSHR, llvm::ISD::VSELECT, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
◆ preferIncOfAddToSubOfNot()
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical.
Some targets may prefer one to the other.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27411 of file AArch64ISelLowering.cpp.
References llvm::EVT::isScalarInteger().
◆ preferredShiftLegalizationStrategy()
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overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27343 of file AArch64ISelLowering.cpp.
References llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::Function::hasMinSize(), llvm::AArch64Subtarget::isTargetDarwin(), llvm::AArch64Subtarget::isTargetWindows(), llvm::TargetLoweringBase::LowerToLibcall, N, and llvm::TargetLoweringBase::preferredShiftLegalizationStrategy().
◆ ReconstructShuffle()
| SDValue AArch64TargetLowering::ReconstructShuffle | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 12192 of file AArch64ISelLowering.cpp.
References assert(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::ISD::BITCAST, llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::dbgs(), llvm::SDValue::dump(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::AArch64ISD::EXT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::find(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), getExtFactor(), llvm::TypeSize::getFixed(), llvm::EVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), I, llvm::SmallVectorImpl< T >::insert(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::DataLayout::isBigEndian(), llvm::EVT::isScalableVector(), isShuffleMaskLegal(), LLVM_DEBUG, llvm::AArch64ISD::NVCAST, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorBase< Size_T >::size().
◆ shouldConsiderGEPOffsetSplit()
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overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17883 of file AArch64ISelLowering.cpp.
◆ shouldConvertConstantLoadToIntImm()
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overridevirtual |
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 18023 of file AArch64ISelLowering.cpp.
References assert(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isIntegerTy(), llvm::AArch64_AM::isLogicalImmediate(), and llvm::Log2_64().
◆ shouldConvertFpToSat()
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overridevirtual |
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27416 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::shouldConvertFpToSat().
◆ shouldExpandAtomicCmpXchgInIR()
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overridevirtual |
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27116 of file AArch64ISelLowering.cpp.
References llvm::AtomicCmpXchgInst::getCompareOperand(), llvm::Type::getPrimitiveSizeInBits(), llvm::TargetLoweringBase::getTargetMachine(), llvm::Value::getType(), llvm::TargetLoweringBase::LLSC, llvm::TargetLoweringBase::None, llvm::None, and Size.
◆ shouldExpandAtomicLoadInIR()
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overridevirtual |
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27034 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::CmpXChg, llvm::Type::getPrimitiveSizeInBits(), llvm::TargetLoweringBase::getTargetMachine(), llvm::Value::getType(), isOpSuitableForLDPSTP(), isOpSuitableForRCPC3(), llvm::TargetLoweringBase::LLSC, llvm::TargetLoweringBase::None, llvm::None, and Size.
◆ shouldExpandAtomicRMWInIR()
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overridevirtual |
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Default is to never expand.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27067 of file AArch64ISelLowering.cpp.
References llvm::AtomicRMWInst::And, assert(), llvm::TargetLoweringBase::CmpXChg, llvm::AtomicRMWInst::getOperation(), llvm::TargetMachine::getOptLevel(), llvm::Type::getPrimitiveSizeInBits(), llvm::TargetLoweringBase::getTargetMachine(), llvm::Value::getType(), llvm::AtomicRMWInst::isFloatingPointOperation(), llvm::TargetLoweringBase::LLSC, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::TargetLoweringBase::None, llvm::None, llvm::AtomicRMWInst::Or, Size, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.
◆ shouldExpandAtomicStoreInIR()
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overridevirtual |
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
For instance AtomicExpansionKind::Expand will try to use an atomicrmw xchg.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27017 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::Expand, isOpSuitableForLDPSTP(), isOpSuitableForLSE128(), isOpSuitableForRCPC3(), llvm::TargetLoweringBase::None, and Size.
◆ shouldExpandCmpUsingSelects()
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inlineoverridevirtual |
Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean types.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 917 of file AArch64ISelLowering.h.
◆ shouldExpandCttzElements()
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in SelectionDAGBuilder.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1996 of file AArch64ISelLowering.cpp.
References llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable().
◆ shouldExpandGetActiveLaneMask()
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overridevirtual |
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1976 of file AArch64ISelLowering.cpp.
◆ shouldFoldConstantShiftPairToMask()
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overridevirtual |
Return true if it is profitable to fold a pair of shifts into a mask.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 17996 of file AArch64ISelLowering.cpp.
References assert(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
◆ shouldFoldSelectWithIdentityConstant()
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overridevirtual |
Return true if pulling a binary operation into a select with an identity constant is profitable.
This is the inverse of an IR transform. Example: X + (Cond ? Y : 0) --> Cond ? (X + Y) : X
Reimplemented from llvm::TargetLoweringBase.
Definition at line 18018 of file AArch64ISelLowering.cpp.
References llvm::EVT::isScalableVector(), and llvm::TargetLoweringBase::isTypeLegal().
◆ shouldFormOverflowOp()
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inlineoverridevirtual |
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Targets may want to override this independently of whether the operation is legal/custom for the given type because it may obscure matching of other patterns.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 784 of file AArch64ISelLowering.h.
References llvm::TargetLoweringBase::shouldFormOverflowOp().
◆ shouldInsertFencesForAtomic()
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overridevirtual |
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
This should be true for most architectures with weak memory ordering. Defaults to false.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 26978 of file AArch64ISelLowering.cpp.
References I, isOpSuitableForLDPSTP(), isOpSuitableForLSE128(), and isOpSuitableForRCPC3().
◆ shouldInsertTrailingFenceForAtomicStore()
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overridevirtual |
Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering for this atomic.
Defaults to false.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 26989 of file AArch64ISelLowering.cpp.
References llvm::AArch64Subtarget::getTargetTriple(), I, llvm::Triple::isWindowsMSVCEnvironment(), and llvm::SequentiallyConsistent.
◆ shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()
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overridevirtual |
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27329 of file AArch64ISelLowering.cpp.
References CC, llvm::ISD::SHL, llvm::TargetLoweringBase::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), X, and Y.
◆ shouldReduceLoadWidth()
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overridevirtual |
Return true if it is profitable to reduce a load to a smaller type.
Example: (i16 (trunc (i32 (load x))) -> i16 load x
Reimplemented from llvm::TargetLoweringBase.
Definition at line 15960 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::ISD::Constant, llvm::MemSDNode::getBasePtr(), llvm::MemSDNode::getMemoryVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isScalableVector(), llvm::Log2_32(), llvm::ISD::NON_EXTLOAD, llvm::ISD::SHL, and llvm::TargetLoweringBase::shouldReduceLoadWidth().
◆ shouldRemoveRedundantExtend()
Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant, and use x directly.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 15995 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), and llvm::SDNode::use_size().
◆ shouldSinkOperands()
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overridevirtual |
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded into a target instruction, e.g.
shufflevectors extracts and/or sext/zext can be folded into (u,s)subl(2).
Reimplemented from llvm::TargetLoweringBase.
Definition at line 16286 of file AArch64ISelLowering.cpp.
References llvm::any_of(), areExtractExts(), areExtractShuffleVectors(), areOperandsOfVmullHighP64(), DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::APInt::getHighBitsSet(), llvm::Instruction::getOpcode(), llvm::User::getOperand(), llvm::User::getOperandUse(), llvm::ilist_detail::node_parent_access< NodeTy, ParentTy >::getParent(), I, Idx, II, isSplatShuffle(), llvm::ConstantInt::isZero(), llvm::PatternMatch::m_c_And(), llvm::PatternMatch::m_c_Or(), llvm::PatternMatch::m_Instruction(), llvm::PatternMatch::m_Not(), llvm::PatternMatch::m_OneUse(), llvm::PatternMatch::m_SExt(), llvm::PatternMatch::m_Specific(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExt(), llvm::PatternMatch::m_ZExtOrSExt(), llvm::MaskedValueIsZero(), llvm::PatternMatch::match(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), shouldSinkVectorOfPtrs(), and shouldSinkVScale().
◆ shouldTransformSignedTruncationCheck()
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inlineoverridevirtual |
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform.
Return false if there is no preference.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 896 of file AArch64ISelLowering.h.
References llvm::MVT::getIntegerVT(), and llvm::EVT::isVector().
◆ supportKCFIBundles()
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inlineoverridevirtual |
Return true if the target supports kcfi operand bundles.
Reimplemented from llvm::TargetLowering.
Definition at line 943 of file AArch64ISelLowering.h.
◆ supportPtrAuthBundles()
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inlineoverridevirtual |
Return true if the target supports ptrauth operand bundles.
Reimplemented from llvm::TargetLowering.
Definition at line 941 of file AArch64ISelLowering.h.
◆ supportSplitCSR()
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inlineoverridevirtual |
Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies.
Reimplemented from llvm::TargetLowering.
Definition at line 928 of file AArch64ISelLowering.h.
References llvm::CallingConv::CXX_FAST_TLS, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::Function::hasFnAttribute().
◆ supportSwiftError()
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inlineoverridevirtual |
Return true if the target supports swifterror attribute.
It optimizes loads and stores to reading and writing a specific register.
Reimplemented from llvm::TargetLowering.
Definition at line 937 of file AArch64ISelLowering.h.
Referenced by llvm::AArch64RegisterInfo::getCalleeSavedRegs(), llvm::AArch64RegisterInfo::getCallPreservedMask(), llvm::AArch64RegisterInfo::getDarwinCalleeSavedRegs(), llvm::AArch64RegisterInfo::getDarwinCallPreservedMask(), and produceCompactUnwindFrame().
◆ targetShrinkDemandedConstant()
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overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 2284 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::CallingConv::C, EnableOptimizeLogicalImm, llvm::EVT::getSizeInBits(), llvm::EVT::isVector(), llvm::TargetLowering::TargetLoweringOpt::LegalOps, optimizeLogicalImm(), llvm::ISD::OR, Size, and llvm::ISD::XOR.
◆ useLoadStackGuardNode()
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overridevirtual |
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
Reimplemented from llvm::TargetLowering.
Definition at line 26899 of file AArch64ISelLowering.cpp.
References llvm::AArch64Subtarget::isTargetAndroid(), llvm::AArch64Subtarget::isTargetFuchsia(), and llvm::TargetLowering::useLoadStackGuardNode().
◆ useSVEForFixedLengthVectorVT()
| bool AArch64TargetLowering::useSVEForFixedLengthVectorVT | ( | EVT | VT, |
| bool | OverrideNEON = false |
||
| ) | const |
Definition at line 7243 of file AArch64ISelLowering.cpp.
References llvm::EVT::getFixedSizeInBits(), llvm::AArch64Subtarget::getMinSVEVectorSizeInBits(), llvm::EVT::getSimpleVT(), llvm::EVT::getVectorElementType(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isPow2VectorType(), llvm::EVT::isSimple(), llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), llvm::MVT::SimpleTy, and llvm::AArch64Subtarget::useSVEForFixedLengthVectors().
Referenced by AArch64TargetLowering(), generateFMAsInMachineCombiner(), isShuffleMaskLegal(), LowerOperation(), and tryCombineToBSL().
◆ verifyTargetSDNode()
Check the given SDNode. Aborts if it is invalid.
Reimplemented from llvm::TargetLowering.
Definition at line 29251 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getSizeInBits(), llvm::EVT::isInteger(), llvm::EVT::isVector(), N, llvm::AArch64ISD::SUNPKHI, llvm::AArch64ISD::SUNPKLO, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, llvm::AArch64ISD::UUNPKHI, llvm::AArch64ISD::UUNPKLO, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.
The documentation for this class was generated from the following files:
- lib/Target/AArch64/AArch64ISelLowering.h
- lib/Target/AArch64/AArch64ISelLowering.cpp
