LLVM 24.0.0git
TargetTransformInfo.cpp
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1//===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "llvm/Analysis/CFG.h"
15#include "llvm/IR/CFG.h"
16#include "llvm/IR/Dominators.h"
17#include "llvm/IR/Instruction.h"
20#include "llvm/IR/Module.h"
21#include "llvm/IR/Operator.h"
24#include <optional>
25#include <utility>
26
27using namespace llvm;
28using namespace PatternMatch;
29
30#define DEBUG_TYPE "tti"
31
32static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
34 cl::desc("Recognize reduction patterns."));
35
37 "cache-line-size", cl::init(0), cl::Hidden,
38 cl::desc("Use this to override the target cache line size when "
39 "specified by the user."));
40
42 "min-page-size", cl::init(0), cl::Hidden,
43 cl::desc("Use this to override the target's minimum page size."));
44
46 "predictable-branch-threshold", cl::init(99), cl::Hidden,
48 "Use this to override the target's predictable branch threshold (%)."));
49
50namespace {
51/// No-op implementation of the TTI interface using the utility base
52/// classes.
53///
54/// This is used when no target specific information is available.
55struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
56 explicit NoTTIImpl(const DataLayout &DL)
57 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
58};
59} // namespace
60
62 std::unique_ptr<const TargetTransformInfoImplBase> Impl)
63 : TTIImpl(std::move(Impl)) {}
64
66 // If the loop has irreducible control flow, it can not be converted to
67 // Hardware loop.
68 LoopBlocksRPO RPOT(L);
69 RPOT.perform(&LI);
71 return false;
72 return true;
73}
74
76 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
77 bool TypeBasedOnly)
78 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
79 ScalarizationCost(ScalarizationCost) {
80
81 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
82 FMF = FPMO->getFastMathFlags();
83
84 if (!TypeBasedOnly)
85 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
86 for (const Value *Arg : CI.args())
87 ParamTys.push_back(Arg->getType());
88}
89
92 FastMathFlags Flags,
93 const IntrinsicInst *I,
94 InstructionCost ScalarCost)
95 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
96 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
97}
98
101 : RetTy(Ty), IID(Id) {
102
103 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
104 ParamTys.reserve(Arguments.size());
105 for (const Value *Argument : Arguments)
106 ParamTys.push_back(Argument->getType());
107}
108
112 InstructionCost ScalarCost, VectorInstrContext VIC)
113 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost),
114 VIC(VIC) {
115 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
116 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
117}
118
120 // Match default options:
121 // - hardware-loop-counter-bitwidth = 32
122 // - hardware-loop-decrement = 1
123 CountType = Type::getInt32Ty(L->getHeader()->getContext());
124 LoopDecrement = ConstantInt::get(CountType, 1);
125}
126
128 LoopInfo &LI, DominatorTree &DT,
129 bool ForceNestedLoop,
131 SmallVector<BasicBlock *, 4> ExitingBlocks;
132 L->getExitingBlocks(ExitingBlocks);
133
134 for (BasicBlock *BB : ExitingBlocks) {
135 // If we pass the updated counter back through a phi, we need to know
136 // which latch the updated value will be coming from.
137 if (!L->isLoopLatch(BB)) {
139 continue;
140 }
141
142 const SCEV *EC = SE.getExitCount(L, BB);
144 continue;
145 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
146 if (ConstEC->getValue()->isZero())
147 continue;
148 } else if (!SE.isLoopInvariant(EC, L))
149 continue;
150
151 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
152 continue;
153
154 // If this exiting block is contained in a nested loop, it is not eligible
155 // for insertion of the branch-and-decrement since the inner loop would
156 // end up messing up the value in the CTR.
157 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
158 continue;
159
160 // We now have a loop-invariant count of loop iterations (which is not the
161 // constant zero) for which we know that this loop will not exit via this
162 // existing block.
163
164 // We need to make sure that this block will run on every loop iteration.
165 // For this to be true, we must dominate all blocks with backedges. Such
166 // blocks are in-loop predecessors to the header block.
167 bool NotAlways = false;
168 for (BasicBlock *Pred : predecessors(L->getHeader())) {
169 if (!L->contains(Pred))
170 continue;
171
172 if (!DT.dominates(BB, Pred)) {
173 NotAlways = true;
174 break;
175 }
176 }
177
178 if (NotAlways)
179 continue;
180
181 // Make sure this blocks ends with a conditional branch.
182 Instruction *TI = BB->getTerminator();
183 if (!TI)
184 continue;
185
186 if (CondBrInst *BI = dyn_cast<CondBrInst>(TI))
187 ExitBranch = BI;
188 else
189 continue;
190
191 // Note that this block may not be the loop latch block, even if the loop
192 // has a latch block.
193 ExitBlock = BB;
194 ExitCount = EC;
195 break;
196 }
197
198 if (!ExitBlock)
199 return false;
200 return true;
201}
202
204 : TTIImpl(std::make_unique<NoTTIImpl>(DL)) {}
205
207
210
212 TTIImpl = std::move(RHS.TTIImpl);
213 return *this;
214}
215
217 return TTIImpl->getInliningThresholdMultiplier();
218}
219
220unsigned
222 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
223}
224
225unsigned
227 const {
228 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
229}
230
232 return TTIImpl->getInliningLastCallToStaticBonus();
233}
234
235unsigned
237 return TTIImpl->adjustInliningThreshold(CB);
238}
239
241 const AllocaInst *AI) const {
242 return TTIImpl->getCallerAllocaCost(CB, AI);
243}
244
246 return TTIImpl->getInlinerVectorBonusPercent();
247}
248
250 Type *PointeeType, const Value *Ptr, ArrayRef<const Value *> Operands,
251 TTI::TargetCostKind CostKind, Type *AccessType) const {
252 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind, AccessType);
253}
254
257 const TTI::PointersChainInfo &Info, Type *AccessTy,
259 assert((Base || !Info.isSameBase()) &&
260 "If pointers have same base address it has to be provided.");
261 return TTIImpl->getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
262}
263
265 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
266 BlockFrequencyInfo *BFI) const {
267 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
268}
269
273 enum TargetCostKind CostKind) const {
274 InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
276 "TTI should not produce negative costs!");
277 return Cost;
278}
279
281 return PredictableBranchThreshold.getNumOccurrences() > 0
283 : TTIImpl->getPredictableBranchThreshold();
284}
285
287 return TTIImpl->getBranchMispredictPenalty();
288}
289
291 return TTIImpl->hasBranchDivergence(F);
292}
293
296 ValueUniformity VU = TTIImpl->getValueUniformity(V);
297 if (const auto *Call = dyn_cast<CallBase>(V)) {
299 Call->hasFnAttr(Attribute::NoDivergenceSource))
301 }
302 return VU;
303}
304
306 unsigned ToAS) const {
307 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
308}
309
311 unsigned ToAS) const {
312 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
313}
314
316 return TTIImpl->getFlatAddressSpace();
317}
318
320 unsigned AS2) const {
321 assert(AS1 != AS2 && "Expected distinct address spaces");
322 return TTIImpl->getAddressSpaceJoin(AS1, AS2);
323}
324
326 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
327 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
328}
329
331 unsigned ToAS) const {
332 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
333}
334
335std::pair<KnownBits, KnownBits>
337 const Value &PtrOp) const {
338 return TTIImpl->computeKnownBitsAddrSpaceCast(ToAS, PtrOp);
339}
340
342 unsigned FromAS, unsigned ToAS, const KnownBits &FromPtrBits) const {
343 return TTIImpl->computeKnownBitsAddrSpaceCast(FromAS, ToAS, FromPtrBits);
344}
345
347 unsigned SrcAS, unsigned DstAS) const {
348 return TTIImpl->getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
349}
350
352 unsigned AS) const {
353 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
354}
355
357 return TTIImpl->getAssumedAddrSpace(V);
358}
359
360std::pair<const Value *, unsigned>
362 return TTIImpl->getPredicatedAddrSpace(V);
363}
364
366 IntrinsicInst *II, Value *OldV, Value *NewV) const {
367 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
368}
369
371 return TTIImpl->isLoweredToCall(F);
372}
373
376 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
377 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
378}
379
381 return TTIImpl->getEpilogueVectorizationMinVF();
382}
383
385 TailFoldingInfo *TFI) const {
386 return TTIImpl->preferTailFoldingOverEpilogue(TFI);
387}
388
390 return TTIImpl->getPreferredTailFoldingStyle();
391}
392
393std::optional<Instruction *>
395 IntrinsicInst &II) const {
396 return TTIImpl->instCombineIntrinsic(IC, II);
397}
398
400 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
401 bool &KnownBitsComputed) const {
402 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
403 KnownBitsComputed);
404}
405
407 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
408 APInt &UndefElts2, APInt &UndefElts3,
409 std::function<void(Instruction *, unsigned, APInt, APInt &)>
410 SimplifyAndSetOp) const {
411 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
412 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
413 SimplifyAndSetOp);
414}
415
418 OptimizationRemarkEmitter *ORE) const {
419 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
420}
421
423 PeelingPreferences &PP) const {
424 return TTIImpl->getPeelingPreferences(L, SE, PP);
425}
426
428 return TTIImpl->isLegalAddImmediate(Imm);
429}
430
432 return TTIImpl->isLegalAddScalableImmediate(Imm);
433}
434
436 return TTIImpl->isLegalICmpImmediate(Imm);
437}
438
440 int64_t BaseOffset,
441 bool HasBaseReg, int64_t Scale,
442 unsigned AddrSpace,
443 Instruction *I,
444 int64_t ScalableOffset) const {
445 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
446 Scale, AddrSpace, I, ScalableOffset);
447}
448
450 const LSRCost &C2) const {
451 return TTIImpl->isLSRCostLess(C1, C2);
452}
453
455 return TTIImpl->isNumRegsMajorCostOfLSR();
456}
457
459 return TTIImpl->shouldDropLSRSolutionIfLessProfitable();
460}
461
463 return TTIImpl->isProfitableLSRChainElement(I);
464}
465
467 return TTIImpl->canMacroFuseCmp();
468}
469
471 ScalarEvolution *SE, LoopInfo *LI,
473 TargetLibraryInfo *LibInfo) const {
474 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
475}
476
479 ScalarEvolution *SE) const {
480 return TTIImpl->getPreferredAddressingMode(L, SE);
481}
482
484 unsigned AddressSpace,
485 TTI::MaskKind MaskKind) const {
486 return TTIImpl->isLegalMaskedStore(DataType, Alignment, AddressSpace,
487 MaskKind);
488}
489
491 unsigned AddressSpace,
492 TTI::MaskKind MaskKind) const {
493 return TTIImpl->isLegalMaskedLoad(DataType, Alignment, AddressSpace,
494 MaskKind);
495}
496
498 Align Alignment) const {
499 return TTIImpl->isLegalNTStore(DataType, Alignment);
500}
501
502bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
503 return TTIImpl->isLegalNTLoad(DataType, Alignment);
504}
505
507 ElementCount NumElements) const {
508 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
509}
510
512 Align Alignment) const {
513 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
514}
515
517 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
518 const SmallBitVector &OpcodeMask) const {
519 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
520}
521
523 Align Alignment) const {
524 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
525}
526
528 Align Alignment) const {
529 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
530}
531
533 Align Alignment) const {
534 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
535}
536
538 Align Alignment) const {
539 return TTIImpl->isLegalMaskedCompressStore(DataType, Alignment);
540}
541
543 Align Alignment) const {
544 return TTIImpl->isLegalMaskedExpandLoad(DataType, Alignment);
545}
546
548 Align Alignment) const {
549 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
550}
551
553 VectorType *VTy, unsigned Factor, Align Alignment,
554 unsigned AddrSpace) const {
555 return TTIImpl->isLegalInterleavedAccessType(VTy, Factor, Alignment,
556 AddrSpace);
557}
558
560 Type *DataType) const {
561 return TTIImpl->isLegalMaskedVectorHistogram(AddrType, DataType);
562}
563
565 return TTIImpl->enableOrderedReductions();
566}
567
568bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
569 return TTIImpl->hasDivRemOp(DataType, IsSigned);
570}
571
573 unsigned AddrSpace) const {
574 return TTIImpl->hasVolatileVariant(I, AddrSpace);
575}
576
578 return TTIImpl->prefersVectorizedAddressing();
579}
580
582 Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg,
583 int64_t Scale, unsigned AddrSpace) const {
584 InstructionCost Cost = TTIImpl->getScalingFactorCost(
585 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
586 assert(Cost >= 0 && "TTI should not produce negative costs!");
587 return Cost;
588}
589
591 return TTIImpl->LSRWithInstrQueries();
592}
593
595 return TTIImpl->isTruncateFree(Ty1, Ty2);
596}
597
599 return TTIImpl->isProfitableToHoist(I);
600}
601
602bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
603
605 return TTIImpl->isTypeLegal(Ty);
606}
607
609 return TTIImpl->getRegUsageForType(Ty);
610}
611
613 return TTIImpl->shouldBuildLookupTables();
614}
615
617 Constant *C) const {
618 return TTIImpl->shouldBuildLookupTablesForConstant(C);
619}
620
622 return TTIImpl->getMinimumLookupTableEntryBitWidth();
623}
624
626 return TTIImpl->shouldBuildRelLookupTables();
627}
628
630 return TTIImpl->useColdCCForColdCall(F);
631}
632
634 return TTIImpl->useFastCCForInternalCall(F);
635}
636
638 Intrinsic::ID ID, unsigned ScalarOpdIdx) const {
639 return TTIImpl->isTargetIntrinsicWithScalarOpAtArg(ID, ScalarOpdIdx);
640}
641
643 Intrinsic::ID ID, int OpdIdx) const {
644 return TTIImpl->isTargetIntrinsicWithOverloadTypeAtArg(ID, OpdIdx);
645}
646
648 Intrinsic::ID ID, int RetIdx) const {
649 return TTIImpl->isTargetIntrinsicWithStructReturnOverloadAtField(ID, RetIdx);
650}
651
656 return Ctx1 == Ctx2 ? Ctx1 : TargetTransformInfo::VectorInstrContext::None;
657}
658
661 if (!I)
663
664 // For inserts, check if the value being inserted comes from a single-use
665 // load.
666 if (isa<InsertElementInst>(I) && isa<LoadInst>(I->getOperand(1)) &&
667 I->getOperand(1)->hasOneUse())
669
670 // For extracts, check if it has a single use that is a store.
671 if (isa<ExtractElementInst>(I) && I->hasOneUse() &&
672 isa<StoreInst>(*I->user_begin()))
674
676}
677
680 ArrayRef<int> Mask, ArrayRef<Value *> Scalars,
682 const {
683 return TTIImpl->getBuildVectorContextHint(Mask, Scalars, GatherUseOps);
684}
685
687 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
688 TTI::TargetCostKind CostKind, bool ForPoisonSrc, ArrayRef<Value *> VL,
689 TTI::VectorInstrContext VIC) const {
690 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
691 CostKind, ForPoisonSrc, VL, VIC);
692}
693
696 TTI::VectorInstrContext VIC) const {
697 return TTIImpl->getOperandsScalarizationOverhead(Tys, CostKind, VIC);
698}
699
701 return TTIImpl->supportsEfficientVectorElementLoadStore();
702}
703
705 return TTIImpl->supportsTailCalls();
706}
707
709 return TTIImpl->supportsTailCallFor(CB);
710}
711
713 bool LoopHasReductions) const {
714 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
715}
716
718TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
719 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
720}
721
723 return TTIImpl->enableSelectOptimize();
724}
725
727 const Instruction *I) const {
728 return TTIImpl->shouldTreatInstructionLikeSelect(I);
729}
730
732 return TTIImpl->enableInterleavedAccessVectorization();
733}
734
736 return TTIImpl->enableMaskedInterleavedAccessVectorization();
737}
738
740 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
741}
742
743bool
745 unsigned BitWidth,
746 unsigned AddressSpace,
747 Align Alignment,
748 unsigned *Fast) const {
749 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
750 AddressSpace, Alignment, Fast);
751}
752
754TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
755 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
756}
757
759 return TTIImpl->haveFastSqrt(Ty);
760}
761
763 return TTIImpl->haveFastClmul(Ty);
764}
765
767 const Instruction *I) const {
768 return TTIImpl->isExpensiveToSpeculativelyExecute(I);
769}
770
772 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
773}
774
776 InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
777 assert(Cost >= 0 && "TTI should not produce negative costs!");
778 return Cost;
779}
780
782 unsigned Idx,
783 const APInt &Imm,
784 Type *Ty) const {
785 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
786 assert(Cost >= 0 && "TTI should not produce negative costs!");
787 return Cost;
788}
789
793 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
794 assert(Cost >= 0 && "TTI should not produce negative costs!");
795 return Cost;
796}
797
799 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
802 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
803 assert(Cost >= 0 && "TTI should not produce negative costs!");
804 return Cost;
805}
806
809 const APInt &Imm, Type *Ty,
812 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
813 assert(Cost >= 0 && "TTI should not produce negative costs!");
814 return Cost;
815}
816
818 const Instruction &Inst, const Function &Fn) const {
819 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
820}
821
822unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
823 return TTIImpl->getNumberOfRegisters(ClassID);
824}
825
827 bool IsStore) const {
828 return TTIImpl->hasConditionalLoadStoreForType(Ty, IsStore);
829}
830
832 Type *Ty) const {
833 return TTIImpl->getRegisterClassForType(Vector, Ty);
834}
835
836const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
837 return TTIImpl->getRegisterClassName(ClassID);
838}
839
841 unsigned ClassID, TTI::TargetCostKind CostKind) const {
842 return TTIImpl->getRegisterClassSpillCost(ClassID, CostKind);
843}
844
846 unsigned ClassID, TTI::TargetCostKind CostKind) const {
847 return TTIImpl->getRegisterClassReloadCost(ClassID, CostKind);
848}
849
852 return TTIImpl->getRegisterBitWidth(K);
853}
854
856 return TTIImpl->getMinVectorRegisterBitWidth();
857}
858
859std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
860 return TTIImpl->getVScaleForTuning();
861}
862
865 return TTIImpl->shouldMaximizeVectorBandwidth(K);
866}
867
869 bool IsScalable) const {
870 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
871}
872
873unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
874 unsigned Opcode) const {
875 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
876}
877
878unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
879 Type *ScalarValTy,
880 Align Alignment,
881 unsigned AddrSpace) const {
882 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy, Alignment,
883 AddrSpace);
884}
885
887 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
888 return TTIImpl->shouldConsiderAddressTypePromotion(
889 I, AllowPromotionWithoutCommonHeader);
890}
891
893 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
894 : TTIImpl->getCacheLineSize();
895}
896
897std::optional<unsigned>
899 return TTIImpl->getCacheSize(Level);
900}
901
902std::optional<unsigned>
904 return TTIImpl->getCacheAssociativity(Level);
905}
906
907std::optional<unsigned> TargetTransformInfo::getMinPageSize() const {
908 return MinPageSize.getNumOccurrences() > 0 ? MinPageSize
909 : TTIImpl->getMinPageSize();
910}
911
913 return TTIImpl->getPrefetchDistance();
914}
915
917 unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
918 unsigned NumPrefetches, bool HasCall) const {
919 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
920 NumPrefetches, HasCall);
921}
922
924 return TTIImpl->getMaxPrefetchIterationsAhead();
925}
926
928 return TTIImpl->enableWritePrefetching();
929}
930
932 return TTIImpl->shouldPrefetchAddressSpace(AS);
933}
934
936 unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
938 PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
939 TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
940 return TTIImpl->getPartialReductionCost(Opcode, InputTypeA, InputTypeB,
941 AccumType, VF, OpAExtend, OpBExtend,
942 BinOp, CostKind, FMF);
943}
944
945unsigned
947 bool HasUnorderedReductions) const {
948 return TTIImpl->getMaxInterleaveFactor(VF, HasUnorderedReductions);
949}
950
955
956 // undef/poison don't materialize constants.
957 if (isa<UndefValue>(V))
958 return {OK_AnyValue, OP_None};
959
960 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
961 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
962 if (CI->getValue().isPowerOf2())
963 OpProps = OP_PowerOf2;
964 else if (CI->getValue().isNegatedPowerOf2())
965 OpProps = OP_NegatedPowerOf2;
966 }
967 return {OK_UniformConstantValue, OpProps};
968 }
969
970 // A broadcast shuffle creates a uniform value.
971 // TODO: Add support for non-zero index broadcasts.
972 // TODO: Add support for different source vector width.
973 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
974 if (ShuffleInst->isZeroEltSplat())
975 OpInfo = OK_UniformValue;
976
977 const Value *Splat = getSplatValue(V);
978
979 // Check for a splat of a constant or for a non uniform vector of constants
980 // and check if the constant(s) are all powers of two.
981 if (Splat) {
982 // Check for a splat of a uniform value. This is not loop aware, so return
983 // true only for the obviously uniform cases (argument, globalvalue)
985 OpInfo = OK_UniformValue;
986 } else if (isa<Constant>(Splat)) {
988 if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
989 if (CI->getValue().isPowerOf2())
990 OpProps = OP_PowerOf2;
991 else if (CI->getValue().isNegatedPowerOf2())
992 OpProps = OP_NegatedPowerOf2;
993 }
994 }
995 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
997 bool AllPow2 = true, AllNegPow2 = true;
998 for (uint64_t I = 0, E = CDS->getNumElements(); I != E; ++I) {
999 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
1000 AllPow2 &= CI->getValue().isPowerOf2();
1001 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
1002 if (AllPow2 || AllNegPow2)
1003 continue;
1004 }
1005 AllPow2 = AllNegPow2 = false;
1006 break;
1007 }
1008 OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
1009 OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
1010 } else if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
1012 }
1013
1014 return {OpInfo, OpProps};
1015}
1016
1020 if (X == Y)
1021 return OpInfoX;
1022 return OpInfoX.mergeWith(getOperandInfo(Y));
1023}
1024
1026 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
1027 OperandValueInfo Op1Info, OperandValueInfo Op2Info,
1028 ArrayRef<const Value *> Args, const Instruction *CxtI,
1029 const TargetLibraryInfo *TLibInfo) const {
1030
1031 // Use call cost for frem intructions that have platform specific vector math
1032 // functions, as those will be replaced with calls later by SelectionDAG or
1033 // ReplaceWithVecLib pass.
1034 if (TLibInfo && Opcode == Instruction::FRem) {
1035 VectorType *VecTy = dyn_cast<VectorType>(Ty);
1036 LibFunc Func = TLibInfo->getLibFunc(Instruction::FRem, Ty->getScalarType());
1037 if (VecTy && Func != NotLibFunc &&
1038 TLibInfo->isFunctionVectorizable(TLibInfo->getName(Func),
1039 VecTy->getElementCount()))
1040 return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
1041 }
1042
1043 InstructionCost Cost = TTIImpl->getArithmeticInstrCost(
1044 Opcode, Ty, CostKind, Op1Info, Op2Info, Args, CxtI);
1045 assert(Cost >= 0 && "TTI should not produce negative costs!");
1046 return Cost;
1047}
1048
1050 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1051 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const {
1053 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
1054 assert(Cost >= 0 && "TTI should not produce negative costs!");
1055 return Cost;
1056}
1057
1059 ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
1061 VectorType *SubTp, ArrayRef<const Value *> Args, const Instruction *CxtI,
1062 TTI::VectorInstrContext VIC) const {
1063 assert((Mask.empty() || DstTy->isScalableTy() ||
1064 Mask.size() == DstTy->getElementCount().getKnownMinValue()) &&
1065 "Expected the Mask to match the return size if given");
1066 assert(SrcTy->getScalarType() == DstTy->getScalarType() &&
1067 "Expected the same scalar types");
1068 InstructionCost Cost = TTIImpl->getShuffleCost(
1069 Kind, DstTy, SrcTy, CostKind, Mask, Index, SubTp, Args, CxtI, VIC);
1070 assert(Cost >= 0 && "TTI should not produce negative costs!");
1071 return Cost;
1072}
1073
1076 if (auto *Cast = dyn_cast<CastInst>(I))
1077 return getPartialReductionExtendKind(Cast->getOpcode());
1078 return PR_None;
1079}
1080
1084 switch (Kind) {
1086 return Instruction::CastOps::ZExt;
1088 return Instruction::CastOps::SExt;
1090 return Instruction::CastOps::FPExt;
1091 default:
1092 break;
1093 }
1094 llvm_unreachable("Unhandled partial reduction extend kind");
1095}
1096
1099 Instruction::CastOps CastOpc) {
1100 switch (CastOpc) {
1101 case Instruction::CastOps::ZExt:
1102 return PR_ZeroExtend;
1103 case Instruction::CastOps::SExt:
1104 return PR_SignExtend;
1105 case Instruction::CastOps::FPExt:
1106 return PR_FPExtend;
1107 default:
1108 return PR_None;
1109 }
1110 llvm_unreachable("Unhandled cast opcode");
1111}
1112
1115 if (!I)
1116 return CastContextHint::None;
1117
1118 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
1119 unsigned GatScatOp) {
1121 if (!I)
1122 return CastContextHint::None;
1123
1124 if (I->getOpcode() == LdStOp)
1126
1127 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1128 if (II->getIntrinsicID() == MaskedOp)
1130 if (II->getIntrinsicID() == GatScatOp)
1132 }
1133
1135 };
1136
1137 switch (I->getOpcode()) {
1138 case Instruction::ZExt:
1139 case Instruction::SExt:
1140 case Instruction::FPExt:
1141 return getLoadStoreKind(I->getOperand(0), Instruction::Load,
1142 Intrinsic::masked_load, Intrinsic::masked_gather);
1143 case Instruction::Trunc:
1144 case Instruction::FPTrunc:
1145 if (I->hasOneUse())
1146 return getLoadStoreKind(*I->user_begin(), Instruction::Store,
1147 Intrinsic::masked_store,
1148 Intrinsic::masked_scatter);
1149 break;
1150 default:
1151 return CastContextHint::None;
1152 }
1153
1155}
1156
1158 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
1159 TTI::TargetCostKind CostKind, const Instruction *I) const {
1160 assert((I == nullptr || I->getOpcode() == Opcode) &&
1161 "Opcode should reflect passed instruction.");
1163 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
1164 assert(Cost >= 0 && "TTI should not produce negative costs!");
1165 return Cost;
1166}
1167
1169 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index,
1172 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index, CostKind);
1173 assert(Cost >= 0 && "TTI should not produce negative costs!");
1174 return Cost;
1175}
1176
1178 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
1179 assert((I == nullptr || I->getOpcode() == Opcode) &&
1180 "Opcode should reflect passed instruction.");
1181 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
1182 assert(Cost >= 0 && "TTI should not produce negative costs!");
1183 return Cost;
1184}
1185
1187 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
1189 OperandValueInfo Op2Info, const Instruction *I) const {
1190 assert((I == nullptr || I->getOpcode() == Opcode) &&
1191 "Opcode should reflect passed instruction.");
1192 InstructionCost Cost = TTIImpl->getCmpSelInstrCost(
1193 Opcode, ValTy, CondTy, VecPred, CostKind, Op1Info, Op2Info, I);
1194 assert(Cost >= 0 && "TTI should not produce negative costs!");
1195 return Cost;
1196}
1197
1199 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1200 const Value *Op0, const Value *Op1, TTI::VectorInstrContext VIC) const {
1201 assert((Opcode == Instruction::InsertElement ||
1202 Opcode == Instruction::ExtractElement) &&
1203 "Expecting Opcode to be insertelement/extractelement.");
1205 TTIImpl->getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1, VIC);
1206 assert(Cost >= 0 && "TTI should not produce negative costs!");
1207 return Cost;
1208}
1209
1211 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1212 Value *Scalar, ArrayRef<std::tuple<Value *, User *, int>> ScalarUserAndIdx,
1213 TTI::VectorInstrContext VIC) const {
1214 assert((Opcode == Instruction::InsertElement ||
1215 Opcode == Instruction::ExtractElement) &&
1216 "Expecting Opcode to be insertelement/extractelement.");
1217 InstructionCost Cost = TTIImpl->getVectorInstrCost(
1218 Opcode, Val, CostKind, Index, Scalar, ScalarUserAndIdx, VIC);
1219 assert(Cost >= 0 && "TTI should not produce negative costs!");
1220 return Cost;
1221}
1222
1225 unsigned Index, TTI::VectorInstrContext VIC) const {
1226 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1227 // This is mentioned in the interface description and respected by all
1228 // callers, but never asserted upon.
1230 TTIImpl->getVectorInstrCost(I, Val, CostKind, Index, VIC);
1231 assert(Cost >= 0 && "TTI should not produce negative costs!");
1232 return Cost;
1233}
1234
1236 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind,
1237 unsigned Index) const {
1239 TTIImpl->getIndexedVectorInstrCostFromEnd(Opcode, Val, CostKind, Index);
1240 assert(Cost >= 0 && "TTI should not produce negative costs!");
1241 return Cost;
1242}
1243
1245 unsigned Opcode, TTI::TargetCostKind CostKind) const {
1246 assert((Opcode == Instruction::InsertValue ||
1247 Opcode == Instruction::ExtractValue) &&
1248 "Expecting Opcode to be insertvalue/extractvalue.");
1249 InstructionCost Cost = TTIImpl->getInsertExtractValueCost(Opcode, CostKind);
1250 assert(Cost >= 0 && "TTI should not produce negative costs!");
1251 return Cost;
1252}
1253
1255 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1257 InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
1258 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
1259 assert(Cost >= 0 && "TTI should not produce negative costs!");
1260 return Cost;
1261}
1262
1264 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1266 const Instruction *I) const {
1267 assert((I == nullptr || I->getOpcode() == Opcode) &&
1268 "Opcode should reflect passed instruction.");
1269 InstructionCost Cost = TTIImpl->getMemoryOpCost(
1270 Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
1271 assert(Cost >= 0 && "TTI should not produce negative costs!");
1272 return Cost;
1273}
1274
1276 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1277 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1278 bool UseMaskForCond, bool UseMaskForGaps) const {
1279 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
1280 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
1281 UseMaskForCond, UseMaskForGaps);
1282 assert(Cost >= 0 && "TTI should not produce negative costs!");
1283 return Cost;
1284}
1285
1289 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
1290 assert(Cost >= 0 && "TTI should not produce negative costs!");
1291 return Cost;
1292}
1293
1295 const MemIntrinsicCostAttributes &MICA,
1297 InstructionCost Cost = TTIImpl->getMemIntrinsicInstrCost(MICA, CostKind);
1298 assert(Cost >= 0 && "TTI should not produce negative costs!");
1299 return Cost;
1300}
1301
1304 ArrayRef<Type *> Tys,
1306 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
1307 assert(Cost >= 0 && "TTI should not produce negative costs!");
1308 return Cost;
1309}
1310
1312 return TTIImpl->getNumberOfParts(Tp);
1313}
1314
1316 Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr,
1319 TTIImpl->getAddressComputationCost(PtrTy, SE, Ptr, CostKind);
1320 assert(Cost >= 0 && "TTI should not produce negative costs!");
1321 return Cost;
1322}
1323
1325 InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1326 assert(Cost >= 0 && "TTI should not produce negative costs!");
1327 return Cost;
1328}
1329
1331 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1332}
1333
1335 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1338 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1339 assert(Cost >= 0 && "TTI should not produce negative costs!");
1340 return Cost;
1341}
1342
1347 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF, CostKind);
1348 assert(Cost >= 0 && "TTI should not produce negative costs!");
1349 return Cost;
1350}
1351
1353 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1354 std::optional<FastMathFlags> FMF, TTI::TargetCostKind CostKind) const {
1355 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1356 CostKind);
1357}
1358
1360 bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty,
1362 return TTIImpl->getMulAccReductionCost(IsUnsigned, RedOpcode, ResTy, Ty,
1363 CostKind);
1364}
1365
1368 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1369}
1370
1372 MemIntrinsicInfo &Info) const {
1373 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1374}
1375
1377 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1378}
1379
1381 IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate) const {
1382 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType,
1383 CanCreate);
1384}
1385
1387 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1388 unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
1389 std::optional<uint32_t> AtomicElementSize) const {
1390 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1391 DestAddrSpace, SrcAlign, DestAlign,
1392 AtomicElementSize);
1393}
1394
1396 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1397 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1398 Align SrcAlign, Align DestAlign,
1399 std::optional<uint32_t> AtomicCpySize) const {
1400 TTIImpl->getMemcpyLoopResidualLoweringType(
1401 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1402 DestAlign, AtomicCpySize);
1403}
1404
1406 const Function *Callee) const {
1407 return TTIImpl->areInlineCompatible(Caller, Callee);
1408}
1409
1410unsigned
1412 const CallBase &Call,
1413 unsigned DefaultCallPenalty) const {
1414 return TTIImpl->getInlineCallPenalty(F, Call, DefaultCallPenalty);
1415}
1416
1418 const Function *Caller, const Attribute &Attr) const {
1419 return TTIImpl->shouldCopyAttributeWhenOutliningFrom(Caller, Attr);
1420}
1422 const Function *Callee,
1423 ArrayRef<Type *> Types) const {
1424 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1425}
1426
1428 Type *Ty) const {
1429 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1430}
1431
1433 Type *Ty) const {
1434 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1435}
1436
1438 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1439}
1440
1442 return TTIImpl->isLegalToVectorizeLoad(LI);
1443}
1444
1446 return TTIImpl->isLegalToVectorizeStore(SI);
1447}
1448
1450 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1451 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1452 AddrSpace);
1453}
1454
1456 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1457 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1458 AddrSpace);
1459}
1460
1462 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1463 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1464}
1465
1467 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1468}
1469
1471 unsigned LoadSize,
1472 unsigned ChainSizeInBytes,
1473 VectorType *VecTy) const {
1474 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1475}
1476
1478 unsigned StoreSize,
1479 unsigned ChainSizeInBytes,
1480 VectorType *VecTy) const {
1481 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1482}
1483
1485 return TTIImpl->preferFixedOverScalableIfEqualCost();
1486}
1487
1489 Type *Ty) const {
1490 return TTIImpl->preferInLoopReduction(Kind, Ty);
1491}
1492
1494 return TTIImpl->preferAlternateOpcodeVectorization();
1495}
1496
1498 return TTIImpl->preferSLPInstCountCheck();
1499}
1500
1502 return TTIImpl->preferPredicatedReductionSelect();
1503}
1504
1506 ElementCount Iters) const {
1507 return TTIImpl->preferEpilogueVectorization(Iters);
1508}
1509
1511 return TTIImpl->shouldConsiderVectorizationRegPressure();
1512}
1513
1516 return TTIImpl->getVPLegalizationStrategy(VPI);
1517}
1518
1520 return TTIImpl->hasArmWideBranch(Thumb);
1521}
1522
1524 return TTIImpl->getFeatureMask(F);
1525}
1526
1528 return TTIImpl->getPriorityMask(F);
1529}
1530
1532 return TTIImpl->isMultiversionedFunction(F);
1533}
1534
1536 return TTIImpl->getMaxNumArgs();
1537}
1538
1540 return TTIImpl->shouldExpandReduction(II);
1541}
1542
1545 const IntrinsicInst *II) const {
1546 return TTIImpl->getPreferredExpandedReductionShuffle(II);
1547}
1548
1550 return TTIImpl->getGISelRematGlobalCost();
1551}
1552
1554 return TTIImpl->getMinTripCountTailFoldingThreshold();
1555}
1556
1558 return TTIImpl->supportsScalableVectors();
1559}
1560
1562 return TTIImpl->enableScalableVectorization();
1563}
1564
1566 return TTIImpl->hasActiveVectorLength();
1567}
1568
1570 Instruction *I, SmallVectorImpl<Use *> &OpsToSink) const {
1571 return TTIImpl->isProfitableToSinkOperands(I, OpsToSink);
1572}
1573
1575 return TTIImpl->isVectorShiftByScalarCheap(Ty);
1576}
1577
1578unsigned
1580 Type *ArrayType) const {
1581 return TTIImpl->getNumBytesToPadGlobalArray(Size, ArrayType);
1582}
1583
1585 const Function &F,
1586 SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const {
1587 return TTIImpl->collectKernelLaunchBounds(F, LB);
1588}
1589
1591 return TTIImpl->allowVectorElementIndexingUsingGEP();
1592}
1593
1595 const SmallBitVector &UniformArgs) const {
1596 return TTIImpl->isUniform(I, UniformArgs);
1597}
1598
1600
1601TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1602
1604 std::function<Result(const Function &)> TTICallback)
1605 : TTICallback(std::move(TTICallback)) {}
1606
1609 assert(!F.isIntrinsic() && "Should not request TTI for intrinsics");
1610 return TTICallback(F);
1611}
1612
1613AnalysisKey TargetIRAnalysis::Key;
1614
1615TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1616 return Result(F.getDataLayout());
1617}
1618
1619// Register the basic pass.
1621 "Target Transform Information", false, true)
1623
1624void TargetTransformInfoWrapperPass::anchor() {}
1625
1628
1632
1634 FunctionAnalysisManager DummyFAM;
1635 TTI = TIRA.run(F, DummyFAM);
1636 return *TTI;
1637}
1638
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
unsigned Imm
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define X(NUM, ENUM, NAME)
Definition ELF.h:857
static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")
static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
Module.h This file contains the declarations for the Module class.
#define F(x, y, z)
Definition MD5.cpp:54
#define I(x, y, z)
Definition MD5.cpp:57
uint64_t IntrinsicInst * II
if(PassOpts->AAPipeline)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
SI Fold Operands
This file defines the SmallVector class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static SymbolRef::Type getType(const Symbol *Sym)
Definition TapiFile.cpp:39
This file provides helpers for the implementation of a TargetTransformInfo-conforming class.
static cl::opt< unsigned > PredictableBranchThreshold("predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc("Use this to override the target's predictable branch threshold (%)."))
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
static cl::opt< unsigned > MinPageSize("min-page-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target's minimum page size."))
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition APInt.h:78
an instruction to allocate memory on the stack
This class represents an incoming formal argument to a Function.
Definition Argument.h:32
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
iterator end() const
Definition ArrayRef.h:130
iterator begin() const
Definition ArrayRef.h:129
Class to represent array types.
A cache of @llvm.assume calls within a function.
Functions, function parameters, and return types can have attributes to indicate how they should be t...
Definition Attributes.h:106
LLVM Basic Block Representation.
Definition BasicBlock.h:62
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:740
Conditional Branch instruction.
This is an important base class in LLVM.
Definition Constant.h:43
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:64
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition Dominators.h:122
LLVM_ABI bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Convenience struct for specifying and reasoning about fast-math flags.
Definition FMF.h:23
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition Pass.h:285
ImmutablePass(char &pid)
Definition Pass.h:287
The core instruction combiner logic.
Class to represent integer types.
LLVM_ABI IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:68
An instruction for reading from memory.
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Definition LoopInfo.h:40
Information for memory intrinsic cost model.
The optimization diagnostic interface.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
LLVM_ABI uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
LLVM_ABI bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
LLVM_ABI const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:30
An instruction for storing to memory.
Multiway switch.
Analysis pass providing the TargetTransformInfo.
LLVM_ABI Result run(const Function &F, FunctionAnalysisManager &)
LLVM_ABI TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
StringRef getName(LibFunc F) const
bool isFunctionVectorizable(StringRef F, const ElementCount &VF) const
LibFunc getLibFunc(StringRef funcName) const
Searches for a particular function name.
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
LLVM_ABI bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
LLVM_ABI Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate=true) const
LLVM_ABI bool isLegalToVectorizeLoad(LoadInst *LI) const
LLVM_ABI std::optional< unsigned > getVScaleForTuning() const
static LLVM_ABI CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
LLVM_ABI unsigned getMaxNumArgs() const
LLVM_ABI bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
LLVM_ABI bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
LLVM_ABI bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
LLVM_ABI VectorInstrContext getBuildVectorContextHint(ArrayRef< int > Mask, ArrayRef< Value * > Scalars, function_ref< bool(SmallVectorImpl< BuildVectorUseOp > &)> GatherUseOps) const
Calculates a VectorInstrContext for buildvector-like gather sequences.
LLVM_ABI bool isLegalToVectorizeStore(StoreInst *SI) const
LLVM_ABI bool areTypesABICompatible(const Function *Caller, const Function *Callee, ArrayRef< Type * > Types) const
LLVM_ABI bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
LLVM_ABI bool isMultiversionedFunction(const Function &F) const
Returns true if this is an instance of a function with multiple versions.
LLVM_ABI unsigned getMaxInterleaveFactor(ElementCount VF, bool HasUnorderedReductions) const
LLVM_ABI bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
LLVM_ABI bool isLegalMaskedStore(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked store.
LLVM_ABI unsigned getMinimumLookupTableEntryBitWidth() const
Return the minimum bit width to use for integer switch lookup table elements on this target.
LLVM_ABI bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
LLVM_ABI unsigned getAssumedAddrSpace(const Value *V) const
LLVM_ABI bool preferAlternateOpcodeVectorization() const
LLVM_ABI bool shouldDropLSRSolutionIfLessProfitable() const
Return true if LSR should drop a found solution if it's calculated to be less profitable than the bas...
LLVM_ABI bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
LLVM_ABI unsigned getPrefetchDistance() const
LLVM_ABI Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
LLVM_ABI bool haveFastClmul(IntegerType *Ty) const
Return true if the hardware has a fast carry-less multiplication instruction.
LLVM_ABI bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked expand load.
LLVM_ABI bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
LLVM_ABI InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
LLVM_ABI bool preferEpilogueVectorization(ElementCount Iters) const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop if t...
LLVM_ABI MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
LLVM_ABI void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
LLVM_ABI bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
LLVM_ABI InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind, Type *AccessType=nullptr) const
Estimate the cost of a GEP operation when lowered.
LLVM_ABI TailFoldingStyle getPreferredTailFoldingStyle() const
Query the target what the preferred style of tail folding is.
LLVM_ABI bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
LLVM_ABI std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
LLVM_ABI bool isProfitableLSRChainElement(Instruction *I) const
LLVM_ABI TypeSize getRegisterBitWidth(RegisterKind K) const
MaskKind
Some targets only support masked load/store with a constant mask.
LLVM_ABI unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
LLVM_ABI InstructionCost getOperandsScalarizationOverhead(ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing operands with the given types.
LLVM_ABI bool hasActiveVectorLength() const
LLVM_ABI bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
LLVM_ABI InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
LLVM_ABI ValueUniformity getValueUniformity(const Value *V) const
Get target-specific uniformity information for a value.
static LLVM_ABI OperandValueInfo commonOperandInfo(const Value *X, const Value *Y)
Collect common data between two OperandValueInfo inputs.
LLVM_ABI InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind) const
LLVM_ABI bool allowVectorElementIndexingUsingGEP() const
Returns true if GEP should not be used to index into vectors for this target.
LLVM_ABI bool preferTailFoldingOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be preferred to create a tail-folded vector loop,...
LLVM_ABI std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
LLVM_ABI unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
LLVM_ABI InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getAtomicMemIntrinsicMaxElementSize() const
LLVM_ABI InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, const Value *Op0=nullptr, const Value *Op1=nullptr, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
LLVM_ABI std::pair< KnownBits, KnownBits > computeKnownBitsAddrSpaceCast(unsigned ToAS, const Value &PtrOp) const
LLVM_ABI bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
LLVM_ABI unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
static LLVM_ABI PartialReductionExtendKind getPartialReductionExtendKind(Instruction *I)
Get the kind of extension that an instruction represents.
LLVM_ABI InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, OperandValueInfo Op1Info={OK_AnyValue, OP_None}, OperandValueInfo Op2Info={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool shouldConsiderVectorizationRegPressure() const
LLVM_ABI bool enableWritePrefetching() const
LLVM_ABI bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
LLVM_ABI bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
LLVM_ABI bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
LLVM_ABI bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace) const
Return true is the target supports interleaved access for the given vector type VTy,...
LLVM_ABI unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
LLVM_ABI bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
LLVM_ABI bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
static LLVM_ABI TargetTransformInfo::VectorInstrContext combineVectorInstrContexts(TargetTransformInfo::VectorInstrContext Ctx1, TargetTransformInfo::VectorInstrContext Ctx2)
Combines 2 context hints into a single value.
LLVM_ABI unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
LLVM_ABI InstructionCost getRegisterClassReloadCost(unsigned ClassID, TargetCostKind CostKind) const
LLVM_ABI ReductionShuffle getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const
static LLVM_ABI OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
LLVM_ABI InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
LLVM_ABI InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI unsigned getAddressSpaceJoin(unsigned AS1, unsigned AS2) const
Return the most specific common address space containing AS1 and AS2.
LLVM_ABI unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
LLVM_ABI bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr, int64_t ScalableOffset=0) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_ABI PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
LLVM_ABI unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
LLVM_ABI bool isElementTypeLegalForScalableVector(Type *Ty) const
LLVM_ABI bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
LLVM_ABI InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of vector reduction intrinsics.
LLVM_ABI unsigned getMaxPrefetchIterationsAhead() const
LLVM_ABI bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
LLVM_ABI ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
LLVM_ABI InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
LLVM_ABI bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
LLVM_ABI InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
LLVM_ABI bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
LLVM_ABI TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
LLVM_ABI InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
LLVM_ABI bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
LLVM_ABI bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
LLVM_ABI int getInliningLastCallToStaticBonus() const
LLVM_ABI bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
LLVM_ABI unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
LLVM_ABI bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
LLVM_ABI bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
LLVM_ABI std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
LLVM_ABI bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
LLVM_ABI bool isUniform(const Instruction *I, const SmallBitVector &UniformArgs) const
Determine if an instruction with Custom uniformity can be proven uniform based on which operands are ...
LLVM_ABI InstructionCost getMemcpyCost(const Instruction *I) const
LLVM_ABI unsigned adjustInliningThreshold(const CallBase *CB) const
LLVM_ABI bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
LLVM_ABI bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, int RetIdx) const
Identifies if the vector form of the intrinsic that returns a struct is overloaded at the struct elem...
LLVM_ABI unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI InstructionCost getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
LLVM_ABI Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
LLVM_ABI InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
LLVM_ABI bool canSaveCmp(Loop *L, CondBrInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
LLVM_ABI unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
LLVM_ABI bool shouldPrefetchAddressSpace(unsigned AS) const
LLVM_ABI InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
LLVM_ABI unsigned getMinVectorRegisterBitWidth() const
LLVM_ABI InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr, TTI::TargetCostKind CostKind) const
LLVM_ABI bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
LLVM_ABI unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
LLVM_ABI bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
LLVM_ABI bool hasArmWideBranch(bool Thumb) const
LLVM_ABI const char * getRegisterClassName(unsigned ClassID) const
LLVM_ABI bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
LLVM_ABI APInt getPriorityMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
LLVM_ABI TargetTransformInfo(std::unique_ptr< const TargetTransformInfoImplBase > Impl)
Construct a TTI object using a type implementing the Concept API below.
LLVM_ABI bool preferInLoopReduction(RecurKind Kind, Type *Ty) const
LLVM_ABI unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
LLVM_ABI bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const
LLVM_ABI InstructionCost getMulAccReductionCost(bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add/...
LLVM_ABI unsigned getCacheLineSize() const
LLVM_ABI bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
LLVM_ABI bool shouldCopyAttributeWhenOutliningFrom(const Function *Caller, const Attribute &Attr) const
LLVM_ABI APInt getAddrSpaceCastPreservedPtrMask(unsigned SrcAS, unsigned DstAS) const
Returns a mask indicating which bits of a pointer remain unchanged when casting between address space...
LLVM_ABI int getInlinerVectorBonusPercent() const
LLVM_ABI unsigned getEpilogueVectorizationMinVF() const
LLVM_ABI InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, TTI::TargetCostKind CostKind, ArrayRef< int > Mask={}, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
LLVM_ABI void collectKernelLaunchBounds(const Function &F, SmallVectorImpl< std::pair< StringRef, int64_t > > &LB) const
Collect kernel launch bounds for F into LB.
PopcntSupportKind
Flags indicating the kind of support for population count.
LLVM_ABI bool preferPredicatedReductionSelect() const
LLVM_ABI InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
LLVM_ABI AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
LLVM_ABI bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
llvm::VectorInstrContext VectorInstrContext
LLVM_ABI bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
LLVM_ABI unsigned getInliningThresholdMultiplier() const
LLVM_ABI InstructionCost getBranchMispredictPenalty() const
Returns estimated penalty of a branch misprediction in latency.
LLVM_ABI unsigned getNumberOfRegisters(unsigned ClassID) const
LLVM_ABI bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
LLVM_ABI bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
LLVM_ABI bool supportsScalableVectors() const
LLVM_ABI bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
LLVM_ABI bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
Return true if the target supports masked compress store.
LLVM_ABI std::optional< unsigned > getMinPageSize() const
LLVM_ABI bool preferSLPInstCountCheck() const
LLVM_ABI bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
LLVM_ABI InstructionCost getInsertExtractValueCost(unsigned Opcode, TTI::TargetCostKind CostKind) const
LLVM_ABI bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
LLVM_ABI std::optional< unsigned > getCacheSize(CacheLevel Level) const
LLVM_ABI std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool isLegalAddScalableImmediate(int64_t Imm) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
LLVM_ABI bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, unsigned ScalarOpdIdx) const
Identifies if the vector form of the intrinsic has a scalar operand.
LLVM_ABI bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
LLVM_ABI bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
LLVM_ABI unsigned getMinTripCountTailFoldingThreshold() const
LLVM_ABI InstructionCost getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, ElementCount VF, PartialReductionExtendKind OpAExtend, PartialReductionExtendKind OpBExtend, std::optional< unsigned > BinOp, TTI::TargetCostKind CostKind, std::optional< FastMathFlags > FMF) const
LLVM_ABI InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
LLVM_ABI bool enableScalableVectorization() const
LLVM_ABI bool useFastCCForInternalCall(Function &F) const
Return true if the input function is internal, should use fastcc calling convention.
LLVM_ABI bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
LLVM_ABI bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
LLVM_ABI unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
LLVM_ABI bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const
LLVM_ABI unsigned getGISelRematGlobalCost() const
LLVM_ABI unsigned getNumBytesToPadGlobalArray(unsigned Size, Type *ArrayType) const
static LLVM_ABI Instruction::CastOps getOpcodeForPartialReductionExtendKind(PartialReductionExtendKind Kind)
Get the cast opcode for an extension kind.
MemIndexedMode
The type of load/store indexing.
LLVM_ABI InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr, const TargetLibraryInfo *TLibInfo=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
LLVM_ABI bool isLegalMaskedLoad(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked load.
LLVM_ABI InstructionCost getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
LLVM_ABI bool areInlineCompatible(const Function *Caller, const Function *Callee) const
LLVM_ABI bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
LLVM_ABI InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
LLVM_ABI bool supportsTailCalls() const
If the target supports tail calls.
LLVM_ABI bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
LLVM_ABI bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
LLVM_ABI unsigned getNumberOfParts(Type *Tp) const
AddressingModeKind
Which addressing mode Loop Strength Reduction will try to generate.
LLVM_ABI InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
LLVM_ABI bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
LLVM_ABI bool isProfitableToSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const
Return true if sinking I's operands to the same basic block as I is profitable, e....
LLVM_ABI void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
LLVM_ABI bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
LLVM_ABI bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, int OpdIdx) const
Identifies if the vector form of the intrinsic is overloaded on the type of the operand at index OpdI...
static LLVM_ABI VectorInstrContext getVectorInstrContextHint(const Instruction *I)
Calculates a VectorInstrContext from I.
LLVM_ABI InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, const TargetCostKind CostKind) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
LLVM_ABI bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
LLVM_ABI bool shouldExpandReduction(const IntrinsicInst *II) const
LLVM_ABI InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, bool ForPoisonSrc=true, ArrayRef< Value * > VL={}, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing an instruction.
LLVM_ABI uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
LLVM_ABI APInt getFeatureMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
CastContextHint
Represents a hint about the context in which a cast is used.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ GatherScatter
The cast is used with a gather/scatter.
LLVM_ABI InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getRegisterClassSpillCost(unsigned ClassID, TargetCostKind CostKind) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
LLVM_ABI bool preferFixedOverScalableIfEqualCost() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:46
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
Definition Type.cpp:299
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition Type.h:363
LLVM_ABI bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
Definition Type.cpp:61
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition Value.h:75
Type * getType() const
All values are typed, get the type of this value.
Definition Value.h:257
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition TypeSize.h:165
An efficient, type-erasing, non-owning reference to a callable.
CallInst * Call
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
@ Length
Definition DWP.cpp:577
InstructionCost Cost
@ Known
Known to have no common set bits.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
VectorInstrContext
Represents a hint about the context in which a vector instruction or intrinsic is used.
@ None
The instruction is not folded.
@ Load
The value being inserted comes from a load (InsertElement only).
@ Store
The extracted value is stored (ExtractElement only).
LLVM_ABI Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool containsIrreducibleCFG(RPOTraversalT &RPOTraversal, const LoopInfoT &LI)
Return true if the control flow in RPOTraversal is irreducible.
Definition CFG.h:154
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:547
LLVM_ABI ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
RecurKind
These are the kinds of recurrences that we support.
@ Fast
Assign the register banks as fast as possible (default).
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1933
auto predecessors(const MachineBasicBlock *BB)
AnalysisManager< Function > FunctionAnalysisManager
Convenience typedef for the Function analysis manager.
ValueUniformity
Enum describing how values behave with respect to uniformity and divergence, to answer the question: ...
Definition Uniformity.h:18
@ NeverUniform
The result value can never be assumed to be uniform.
Definition Uniformity.h:26
@ Default
The result value is uniform if and only if all operands are uniform.
Definition Uniformity.h:20
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:878
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition Analysis.h:29
Attributes of a target dependent hardware loop.
LLVM_ABI bool canAnalyze(LoopInfo &LI)
LLVM_ABI bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
OperandValueInfo mergeWith(const OperandValueInfo OpInfoY)
Describe known properties for a set of pointers.
Parameters that control the generic loop unrolling transformation.