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LLVM 20.0.0git
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This is the complete list of members for llvm::AMDGPURegisterBankInfo, including all inherited members.
| addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps > > Table) const | llvm::AMDGPURegisterBankInfo | |
| addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps > > Table) const | llvm::AMDGPURegisterBankInfo | |
| AMDGPURegisterBankInfo(const GCNSubtarget &STI) | llvm::AMDGPURegisterBankInfo | |
| applyDefaultMapping(const OperandsMapper &OpdMapper) | llvm::RegisterBankInfo | static |
| applyMapping(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const | llvm::RegisterBankInfo | inline |
| applyMappingBFE(MachineIRBuilder &B, const OperandsMapper &OpdMapper, bool Signed) const | llvm::AMDGPURegisterBankInfo | |
| applyMappingDynStackAlloc(MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const | llvm::AMDGPURegisterBankInfo | |
| applyMappingImage(MachineIRBuilder &B, MachineInstr &MI, const OperandsMapper &OpdMapper, int RSrcIdx) const | llvm::AMDGPURegisterBankInfo | |
| applyMappingImpl(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const override | llvm::AMDGPURegisterBankInfo | virtual |
| applyMappingLoad(MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const | llvm::AMDGPURegisterBankInfo | |
| applyMappingMAD_64_32(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const | llvm::AMDGPURegisterBankInfo | |
| applyMappingSBufferLoad(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const | llvm::AMDGPURegisterBankInfo | |
| applyMappingSMULU64(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const | llvm::AMDGPURegisterBankInfo | |
| buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Src) const | llvm::AMDGPURegisterBankInfo | |
| buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const | llvm::AMDGPURegisterBankInfo | |
| cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const | llvm::RegisterBankInfo | inline |
| collectWaterfallOperands(SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const | llvm::AMDGPURegisterBankInfo | |
| constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) | llvm::RegisterBankInfo | static |
| constrainOpWithReadfirstlane(MachineIRBuilder &B, MachineInstr &MI, unsigned OpIdx) const | llvm::AMDGPURegisterBankInfo | |
| copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override | llvm::AMDGPURegisterBankInfo | virtual |
| DefaultMappingID | llvm::RegisterBankInfo | static |
| executeInWaterfallLoop(MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs) const | llvm::AMDGPURegisterBankInfo | |
| executeInWaterfallLoop(MachineIRBuilder &B, MachineInstr &MI, ArrayRef< unsigned > OpIndices) const | llvm::AMDGPURegisterBankInfo | |
| getAGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::AMDGPURegisterBankInfo | |
| getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const override | llvm::AMDGPURegisterBankInfo | virtual |
| getDefaultMappingAllVGPR(const MachineInstr &MI) const | llvm::AMDGPURegisterBankInfo | |
| getDefaultMappingSOP(const MachineInstr &MI) const | llvm::AMDGPURegisterBankInfo | |
| getDefaultMappingVOP(const MachineInstr &MI) const | llvm::AMDGPURegisterBankInfo | |
| getImageMapping(const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const | llvm::AMDGPURegisterBankInfo | |
| getInstrAlternativeMappings(const MachineInstr &MI) const override | llvm::AMDGPURegisterBankInfo | virtual |
| getInstrAlternativeMappingsIntrinsic(const MachineInstr &MI, const MachineRegisterInfo &MRI) const | llvm::AMDGPURegisterBankInfo | |
| getInstrAlternativeMappingsIntrinsicWSideEffects(const MachineInstr &MI, const MachineRegisterInfo &MRI) const | llvm::AMDGPURegisterBankInfo | |
| getInstrMapping(const MachineInstr &MI) const override | llvm::AMDGPURegisterBankInfo | virtual |
| getInstrMappingForLoad(const MachineInstr &MI) const | llvm::AMDGPURegisterBankInfo | |
| getInstrMappingImpl(const MachineInstr &MI) const | llvm::RegisterBankInfo | protected |
| getInstrPossibleMappings(const MachineInstr &MI) const | llvm::RegisterBankInfo | |
| getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const | llvm::RegisterBankInfo | inline |
| getInvalidInstructionMapping() const | llvm::RegisterBankInfo | inline |
| getMappingType(const MachineRegisterInfo &MRI, const MachineInstr &MI) const | llvm::AMDGPURegisterBankInfo | |
| getMaximumSize(unsigned RegBankID) const | llvm::RegisterBankInfo | inline |
| getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | protected |
| getNumRegBanks() const | llvm::RegisterBankInfo | inline |
| getOperandsMapping(Iterator Begin, Iterator End) const | llvm::RegisterBankInfo | protected |
| getOperandsMapping(const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const | llvm::RegisterBankInfo | protected |
| getOperandsMapping(std::initializer_list< const ValueMapping * > OpdsMapping) const | llvm::RegisterBankInfo | protected |
| getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
| getRegBank(unsigned ID) | llvm::RegisterBankInfo | inlineprotected |
| getRegBank(unsigned ID) const | llvm::RegisterBankInfo | inline |
| getRegBank(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const | llvm::RegisterBankInfo | |
| getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override | llvm::AMDGPURegisterBankInfo | virtual |
| getRegBankID(Register Reg, const MachineRegisterInfo &MRI, unsigned Default=AMDGPU::VGPRRegBankID) const | llvm::AMDGPURegisterBankInfo | |
| getSGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::AMDGPURegisterBankInfo | |
| getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
| getValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) const | llvm::RegisterBankInfo | protected |
| getValueMappingForPtr(const MachineRegisterInfo &MRI, Register Ptr) const | llvm::AMDGPURegisterBankInfo | |
| getVGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::AMDGPURegisterBankInfo | |
| handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const | llvm::AMDGPURegisterBankInfo | |
| HwMode | llvm::RegisterBankInfo | protected |
| InstructionMappings typedef | llvm::RegisterBankInfo | |
| InvalidMappingID | llvm::RegisterBankInfo | static |
| isDivergentRegBank(const RegisterBank *RB) const override | llvm::AMDGPURegisterBankInfo | virtual |
| isSALUMapping(const MachineInstr &MI) const | llvm::AMDGPURegisterBankInfo | |
| isScalarLoadLegal(const MachineInstr &MI) const | llvm::AMDGPURegisterBankInfo | |
| MapOfInstructionMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfOperandsMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfPartialMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfValueMappings | llvm::RegisterBankInfo | mutableprotected |
| NumRegBanks | llvm::RegisterBankInfo | protected |
| PhysRegMinimalRCs | llvm::RegisterBankInfo | mutableprotected |
| RegBanks | llvm::RegisterBankInfo | protected |
| RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode) | llvm::RegisterBankInfo | protected |
| RegisterBankInfo() | llvm::RegisterBankInfo | inlineprotected |
| setBufferOffsets(MachineIRBuilder &B, Register CombinedOffset, Register &VOffsetReg, Register &SOffsetReg, int64_t &InstOffsetVal, Align Alignment) const | llvm::AMDGPURegisterBankInfo | |
| Sizes | llvm::RegisterBankInfo | protected |
| split64BitValueForMapping(MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) const | llvm::AMDGPURegisterBankInfo | |
| splitBufferOffsets(MachineIRBuilder &B, Register Offset) const | llvm::AMDGPURegisterBankInfo | |
| Subtarget | llvm::AMDGPURegisterBankInfo | |
| TII | llvm::AMDGPURegisterBankInfo | |
| TRI | llvm::AMDGPURegisterBankInfo | |
| verify(const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| ~RegisterBankInfo()=default | llvm::RegisterBankInfo | virtual |
1.9.6