LLVM 20.0.0git
llvm::HexagonRegisterInfo Member List

This is the complete list of members for llvm::HexagonRegisterInfo, including all inherited members.

eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const overridellvm::HexagonRegisterInfo
getCalleeSavedRegs(const MachineFunction *MF) const overridellvm::HexagonRegisterInfo
getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) constllvm::HexagonRegisterInfo
getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const overridellvm::HexagonRegisterInfo
getFrameRegister(const MachineFunction &MF) const overridellvm::HexagonRegisterInfo
getFrameRegister() constllvm::HexagonRegisterInfo
getHexagonSubRegIndex(const TargetRegisterClass &RC, unsigned GenIdx) constllvm::HexagonRegisterInfo
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const overridellvm::HexagonRegisterInfo
getReservedRegs(const MachineFunction &MF) const overridellvm::HexagonRegisterInfo
getStackRegister() constllvm::HexagonRegisterInfo
HexagonRegisterInfo(unsigned HwMode)llvm::HexagonRegisterInfo
isEHReturnCalleeSaveReg(Register Reg) constllvm::HexagonRegisterInfo
requiresFrameIndexScavenging(const MachineFunction &MF) const overridellvm::HexagonRegisterInfoinline
requiresRegisterScavenging(const MachineFunction &MF) const overridellvm::HexagonRegisterInfoinline
shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const overridellvm::HexagonRegisterInfo
useFPForScavengingIndex(const MachineFunction &MF) const overridellvm::HexagonRegisterInfo