LLVM 20.0.0git
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This is the complete list of members for llvm::LanaiInstrInfo, including all inherited members.
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl< MachineOperand > &Condition, bool AllowModify) const override | llvm::LanaiInstrInfo | |
analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override | llvm::LanaiInstrInfo | |
analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override | llvm::LanaiInstrInfo | |
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override | llvm::LanaiInstrInfo | |
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, MCRegister DestinationRegister, MCRegister SourceRegister, bool KillSource) const override | llvm::LanaiInstrInfo | |
decomposeMachineOperandsTargetFlags(unsigned TF) const override | llvm::LanaiInstrInfo | |
expandPostRAPseudo(MachineInstr &MI) const override | llvm::LanaiInstrInfo | |
getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override | llvm::LanaiInstrInfo | |
getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const | llvm::LanaiInstrInfo | |
getRegisterInfo() const | llvm::LanaiInstrInfo | inlinevirtual |
getSerializableDirectMachineOperandTargetFlags() const override | llvm::LanaiInstrInfo | |
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef< MachineOperand > Condition, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::LanaiInstrInfo | |
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::LanaiInstrInfo | |
isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override | llvm::LanaiInstrInfo | |
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::LanaiInstrInfo | |
LanaiInstrInfo() | llvm::LanaiInstrInfo | |
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo, Register VReg) const override | llvm::LanaiInstrInfo | |
optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override | llvm::LanaiInstrInfo | |
optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool PreferFalse) const override | llvm::LanaiInstrInfo | |
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::LanaiInstrInfo | |
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Condition) const override | llvm::LanaiInstrInfo | |
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo, Register VReg) const override | llvm::LanaiInstrInfo |