LLVM 22.0.0git
llvm::LanaiInstrInfo Class Reference

#include "Target/Lanai/LanaiInstrInfo.h"

Inheritance diagram for llvm::LanaiInstrInfo:
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Public Member Functions

 LanaiInstrInfo (const LanaiSubtarget &STI)
virtual const LanaiRegisterInfogetRegisterInfo () const
bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
Register isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
Register isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, Register DestinationRegister, Register SourceRegister, bool KillSource, bool RenamableDest=false, bool RenamableSrc=false) const override
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
bool expandPostRAPseudo (MachineInstr &MI) const override
bool getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
bool getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl< MachineOperand > &Condition, bool AllowModify) const override
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
bool optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
bool analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
MachineInstroptimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool PreferFalse) const override
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Condition) const override
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef< MachineOperand > Condition, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Detailed Description

Definition at line 27 of file LanaiInstrInfo.h.

Constructor & Destructor Documentation

◆ LanaiInstrInfo()

LanaiInstrInfo::LanaiInstrInfo ( const LanaiSubtarget & STI)

Definition at line 29 of file LanaiInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

◆ analyzeCompare()

bool LanaiInstrInfo::analyzeCompare ( const MachineInstr & MI,
Register & SrcReg,
Register & SrcReg2,
int64_t & CmpMask,
int64_t & CmpValue ) const
override

Definition at line 180 of file LanaiInstrInfo.cpp.

References MI, and Register.

◆ analyzeSelect()

bool LanaiInstrInfo::analyzeSelect ( const MachineInstr & MI,
SmallVectorImpl< MachineOperand > & Cond,
unsigned & TrueOp,
unsigned & FalseOp,
bool & Optimizable ) const
override

Definition at line 440 of file LanaiInstrInfo.cpp.

References assert(), Cond, and MI.

◆ areMemAccessesTriviallyDisjoint()

◆ copyPhysReg()

void LanaiInstrInfo::copyPhysReg ( MachineBasicBlock & MBB,
MachineBasicBlock::iterator Position,
const DebugLoc & DL,
Register DestinationRegister,
Register SourceRegister,
bool KillSource,
bool RenamableDest = false,
bool RenamableSrc = false ) const
override

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > LanaiInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned TF) const
override

Definition at line 166 of file LanaiInstrInfo.cpp.

◆ expandPostRAPseudo()

bool LanaiInstrInfo::expandPostRAPseudo ( MachineInstr & MI) const
override

Definition at line 122 of file LanaiInstrInfo.cpp.

◆ getMemOperandsWithOffsetWidth()

bool LanaiInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr & LdSt,
SmallVectorImpl< const MachineOperand * > & BaseOps,
int64_t & Offset,
bool & OffsetIsScalable,
LocationSize & Width,
const TargetRegisterInfo * TRI ) const
override

◆ getMemOperandWithOffsetWidth()

◆ getRegisterInfo()

virtual const LanaiRegisterInfo & llvm::LanaiInstrInfo::getRegisterInfo ( ) const
inlinevirtual

Definition at line 36 of file LanaiInstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), and optimizeCompareInstr().

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > LanaiInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

Definition at line 171 of file LanaiInstrInfo.cpp.

References llvm::ArrayRef().

◆ insertBranch()

unsigned LanaiInstrInfo::insertBranch ( MachineBasicBlock & MBB,
MachineBasicBlock * TrueBlock,
MachineBasicBlock * FalseBlock,
ArrayRef< MachineOperand > Condition,
const DebugLoc & DL,
int * BytesAdded = nullptr ) const
override

◆ isLoadFromStackSlot()

Register LanaiInstrInfo::isLoadFromStackSlot ( const MachineInstr & MI,
int & FrameIndex ) const
override

Definition at line 716 of file LanaiInstrInfo.cpp.

References MI.

Referenced by isLoadFromStackSlotPostFE().

◆ isLoadFromStackSlotPostFE()

Register LanaiInstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr & MI,
int & FrameIndex ) const
override

Definition at line 727 of file LanaiInstrInfo.cpp.

References Accesses, llvm::cast(), isLoadFromStackSlot(), and MI.

◆ isStoreToStackSlot()

Register LanaiInstrInfo::isStoreToStackSlot ( const MachineInstr & MI,
int & FrameIndex ) const
override

Definition at line 745 of file LanaiInstrInfo.cpp.

References MI.

◆ loadRegFromStackSlot()

void LanaiInstrInfo::loadRegFromStackSlot ( MachineBasicBlock & MBB,
MachineBasicBlock::iterator Position,
Register DestinationRegister,
int FrameIndex,
const TargetRegisterClass * RegisterClass,
const TargetRegisterInfo * RegisterInfo,
Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags ) const
override

◆ optimizeCompareInstr()

◆ optimizeSelect()

◆ removeBranch()

unsigned LanaiInstrInfo::removeBranch ( MachineBasicBlock & MBB,
int * BytesRemoved = nullptr ) const
override

◆ reverseBranchCondition()

bool LanaiInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > & Condition) const
override

◆ storeRegToStackSlot()


The documentation for this class was generated from the following files: