| get(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| getCodeViewRegNum(MCRegister RegNum) const | llvm::MCRegisterInfo | |
| getDwarfRegNum(MCRegister RegNum, bool isEH) const | llvm::MCRegisterInfo | virtual |
| getDwarfRegNumFromDwarfEHRegNum(uint64_t RegNum) const | llvm::MCRegisterInfo | |
| getEncodingValue(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| getLLVMRegNum(uint64_t RegNum, bool isEH) const | llvm::MCRegisterInfo | |
| getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const | llvm::MCRegisterInfo | |
| getName(MCRegister RegNo) const | llvm::MCRegisterInfo | inline |
| getNumRegClasses() const | llvm::MCRegisterInfo | inline |
| getNumRegs() const | llvm::MCRegisterInfo | inline |
| getNumRegUnits() const | llvm::MCRegisterInfo | inline |
| getNumSubRegIndices() const | llvm::MCRegisterInfo | inline |
| getProgramCounter() const | llvm::MCRegisterInfo | inline |
| getRARegister() const | llvm::MCRegisterInfo | inline |
| getRegClass(unsigned i) const | llvm::MCRegisterInfo | inline |
| getRegClassName(const MCRegisterClass *Class) const | llvm::MCRegisterInfo | inline |
| getSEHRegNum(MCRegister RegNum) const | llvm::MCRegisterInfo | |
| getSubReg(MCRegister Reg, unsigned Idx) const | llvm::MCRegisterInfo | |
| getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const | llvm::MCRegisterInfo | |
| InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const int16_t *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const uint16_t *RET) | llvm::MCRegisterInfo | inline |
| isArtificial(MCRegister RegNo) const | llvm::MCRegisterInfo | inline |
| isArtificialRegUnit(MCRegUnit Unit) const | llvm::MCRegisterInfo | |
| isConstant(MCRegister RegNo) const | llvm::MCRegisterInfo | inline |
| isSubRegister(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| isSubRegisterEq(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| isSuperRegister(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | inline |
| mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH) | llvm::MCRegisterInfo | inline |
| mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH) | llvm::MCRegisterInfo | inline |
| mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) | llvm::MCRegisterInfo | inline |
| mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) | llvm::MCRegisterInfo | inline |
| MCRegAliasIterator | llvm::MCRegisterInfo | friend |
| MCRegUnitIterator | llvm::MCRegisterInfo | friend |
| MCRegUnitMaskIterator | llvm::MCRegisterInfo | friend |
| MCRegUnitRootIterator | llvm::MCRegisterInfo | friend |
| MCSubRegIndexIterator | llvm::MCRegisterInfo | friend |
| MCSubRegIterator | llvm::MCRegisterInfo | friend |
| MCSuperRegIterator | llvm::MCRegisterInfo | friend |
| operator[](MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| regclass_begin() const | llvm::MCRegisterInfo | inline |
| regclass_end() const | llvm::MCRegisterInfo | inline |
| regclass_iterator typedef | llvm::MCRegisterInfo | |
| regclasses() const | llvm::MCRegisterInfo | inline |
| regsOverlap(MCRegister RegA, MCRegister RegB) const | llvm::MCRegisterInfo | |
| regunits(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| sub_and_superregs_inclusive(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| subregs(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| subregs_inclusive(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| superregs(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| superregs_inclusive(MCRegister Reg) const | llvm::MCRegisterInfo | inline |
| ~MCRegisterInfo() | llvm::MCRegisterInfo | inlinevirtual |
