LLVM 20.0.0git
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This is the complete list of members for llvm::MipsInstrInfo, including all inherited members.
adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0 | llvm::MipsInstrInfo | pure virtual |
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override | llvm::MipsInstrInfo | |
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify, SmallVectorImpl< MachineInstr * > &BranchInstrs) const | llvm::MipsInstrInfo | |
BranchType enum name | llvm::MipsInstrInfo | |
BT_Cond enum value | llvm::MipsInstrInfo | |
BT_CondUncond enum value | llvm::MipsInstrInfo | |
BT_Indirect enum value | llvm::MipsInstrInfo | |
BT_NoBranch enum value | llvm::MipsInstrInfo | |
BT_None enum value | llvm::MipsInstrInfo | |
BT_Uncond enum value | llvm::MipsInstrInfo | |
create(MipsSubtarget &STI) | llvm::MipsInstrInfo | static |
decomposeMachineOperandsTargetFlags(unsigned TF) const override | llvm::MipsInstrInfo | |
describeLoadedValue(const MachineInstr &MI, Register Reg) const override | llvm::MipsInstrInfo | |
findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override | llvm::MipsInstrInfo | |
genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const | llvm::MipsInstrInfo | |
getEquivalentCompactForm(const MachineBasicBlock::iterator I) const | llvm::MipsInstrInfo | |
getInstSizeInBytes(const MachineInstr &MI) const override | llvm::MipsInstrInfo | |
GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const | llvm::MipsInstrInfo | protected |
getOppositeBranchOpc(unsigned Opc) const =0 | llvm::MipsInstrInfo | pure virtual |
getRegisterInfo() const =0 | llvm::MipsInstrInfo | pure virtual |
getSerializableDirectMachineOperandTargetFlags() const override | llvm::MipsInstrInfo | |
HasForbiddenSlot(const MachineInstr &MI) const | llvm::MipsInstrInfo | |
HasFPUDelaySlot(const MachineInstr &MI) const | llvm::MipsInstrInfo | |
HasLoadDelaySlot(const MachineInstr &MI) const | llvm::MipsInstrInfo | |
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::MipsInstrInfo | |
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::MipsInstrInfo | |
insertNop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const | llvm::MipsInstrInfo | |
isAddImmediate(const MachineInstr &MI, Register Reg) const override | llvm::MipsInstrInfo | |
isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override | llvm::MipsInstrInfo | |
isBranchWithImm(unsigned Opc) const | llvm::MipsInstrInfo | inlinevirtual |
IsMfloOrMfhi(const MachineInstr &MI) const | llvm::MipsInstrInfo | |
isZeroImm(const MachineOperand &op) const | llvm::MipsInstrInfo | protected |
loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0 | llvm::MipsInstrInfo | pure virtual |
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override | llvm::MipsInstrInfo | inline |
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc) | llvm::MipsInstrInfo | explicit |
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::MipsInstrInfo | |
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::MipsInstrInfo | |
SafeAfterMflo(const MachineInstr &MI) const | llvm::MipsInstrInfo | |
SafeInForbiddenSlot(const MachineInstr &MI) const | llvm::MipsInstrInfo | |
SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const | llvm::MipsInstrInfo | |
SafeInLoadDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const | llvm::MipsInstrInfo | |
storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0 | llvm::MipsInstrInfo | pure virtual |
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override | llvm::MipsInstrInfo | inline |
Subtarget | llvm::MipsInstrInfo | protected |
UncondBrOpc | llvm::MipsInstrInfo | protected |
verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override | llvm::MipsInstrInfo |