LLVM 20.0.0git
Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
llvm::MipsInstrInfo Class Referenceabstract

#include "Target/Mips/MipsInstrInfo.h"

Inheritance diagram for llvm::MipsInstrInfo:
Inheritance graph
[legend]

Public Types

enum  BranchType {
  BT_None , BT_NoBranch , BT_Uncond , BT_Cond ,
  BT_CondUncond , BT_Indirect
}
 

Public Member Functions

 MipsInstrInfo (const MipsSubtarget &STI, unsigned UncondBrOpc)
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 Branch Analysis.
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
 
BranchType analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify, SmallVectorImpl< MachineInstr * > &BranchInstrs) const
 
unsigned getEquivalentCompactForm (const MachineBasicBlock::iterator I) const
 Determine the opcode of a non-delay slot form for a branch if one exists.
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 Determine if the branch target is in range.
 
bool SafeInForbiddenSlot (const MachineInstr &MI) const
 Predicate to determine if an instruction can go in a forbidden slot.
 
bool SafeInFPUDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
 Predicate to determine if an instruction can go in an FPU delay slot.
 
bool SafeInLoadDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const
 Predicate to determine if an instruction can go in a load delay slot.
 
bool HasForbiddenSlot (const MachineInstr &MI) const
 Predicate to determine if an instruction has a forbidden slot.
 
bool HasFPUDelaySlot (const MachineInstr &MI) const
 Predicate to determine if an instruction has an FPU delay slot.
 
bool HasLoadDelaySlot (const MachineInstr &MI) const
 Predicate to determine if an instruction has a load delay slot.
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 Insert nop instruction when hazard condition is found.
 
MachineInstrBuilder insertNop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const
 Insert an ISA appropriate nop.
 
virtual const MipsRegisterInfo & getRegisterInfo () const =0
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
 
virtual unsigned getOppositeBranchOpc (unsigned Opc) const =0
 
virtual bool isBranchWithImm (unsigned Opc) const
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 Return the number of bytes of code the specified instruction may be.
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
 
virtual void storeRegToStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
 
virtual void loadRegFromStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
 
virtual void adjustStackPtr (unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0
 
MachineInstrBuilder genInstrWithNewOpc (unsigned NewOpc, MachineBasicBlock::iterator I) const
 Create an instruction which has the same operands and memory operands as MI but has a new opcode.
 
bool findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
bool verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
 Perform target specific instruction verification.
 
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
std::optional< RegImmPair > isAddImmediate (const MachineInstr &MI, Register Reg) const override
 
std::optional< ParamLoadedValue > describeLoadedValue (const MachineInstr &MI, Register Reg) const override
 

Static Public Member Functions

static const MipsInstrInfo * create (MipsSubtarget &STI)
 

Protected Member Functions

bool isZeroImm (const MachineOperand &op) const
 
MachineMemOperand * GetMemOperand (MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
 

Protected Attributes

const MipsSubtarget & Subtarget
 
unsigned UncondBrOpc
 

Detailed Description

Definition at line 41 of file MipsInstrInfo.h.

Member Enumeration Documentation

◆ BranchType

enum llvm::MipsInstrInfo::BranchType
Enumerator
BT_None 
BT_NoBranch 
BT_Uncond 
BT_Cond 
BT_CondUncond 
BT_Indirect 

Definition at line 49 of file MipsInstrInfo.h.

Constructor & Destructor Documentation

◆ MipsInstrInfo()

MipsInstrInfo::MipsInstrInfo ( const MipsSubtarget &  STI,
unsigned  UncondBrOpc 
)
explicit

Definition at line 40 of file MipsInstrInfo.cpp.

Member Function Documentation

◆ adjustStackPtr()

virtual void llvm::MipsInstrInfo::adjustStackPtr ( unsigned  SP,
int64_t  Amount,
MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I 
) const
pure virtual

Implemented in llvm::Mips16InstrInfo, and llvm::MipsSEInstrInfo.

Referenced by llvm::MipsFrameLowering::eliminateCallFramePseudoInstr().

◆ analyzeBranch() [1/2]

bool MipsInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

Branch Analysis.

Definition at line 108 of file MipsInstrInfo.cpp.

References analyzeBranch(), BT_Indirect, BT_None, Cond, MBB, and TBB.

Referenced by analyzeBranch().

◆ analyzeBranch() [2/2]

MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify,
SmallVectorImpl< MachineInstr * > &  BranchInstrs 
) const

Definition at line 204 of file MipsInstrInfo.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), BT_Cond, BT_CondUncond, BT_Indirect, BT_NoBranch, BT_None, BT_Uncond, Cond, llvm::MachineInstr::eraseFromParent(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::SmallVectorImpl< T >::insert(), llvm::MachineInstr::isIndirectBranch(), llvm::MachineInstr::isUnconditionalBranch(), MBB, llvm::SmallVectorTemplateBase< T, bool >::pop_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineBasicBlock::rbegin(), llvm::MachineBasicBlock::rend(), and TBB.

◆ create()

const MipsInstrInfo * MipsInstrInfo::create ( MipsSubtarget &  STI)
static

Definition at line 44 of file MipsInstrInfo.cpp.

References llvm::createMips16InstrInfo(), llvm::createMipsSEInstrInfo(), and llvm::MipsSubtarget::inMips16Mode().

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > MipsInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Definition at line 899 of file MipsInstrInfo.cpp.

◆ describeLoadedValue()

std::optional< ParamLoadedValue > MipsInstrInfo::describeLoadedValue ( const MachineInstr &  MI,
Register  Reg 
) const
override

Definition at line 937 of file MipsInstrInfo.cpp.

References llvm::DIExpression::ApplyOffset, llvm::MachineOperand::CreateReg(), llvm::TargetInstrInfo::describeLoadedValue(), llvm::MDNode::get(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), isAddImmediate(), MI, llvm::Offset, llvm::DIExpression::prepend(), and TRI.

◆ findCommutedOpIndices()

bool MipsInstrInfo::findCommutedOpIndices ( const MachineInstr &  MI,
unsigned &  SrcOpIdx1,
unsigned &  SrcOpIdx2 
) const
override

Definition at line 771 of file MipsInstrInfo.cpp.

References assert(), llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::MCInstrDesc::isCommutable(), and MI.

◆ genInstrWithNewOpc()

MachineInstrBuilder MipsInstrInfo::genInstrWithNewOpc ( unsigned  NewOpc,
MachineBasicBlock::iterator  I 
) const

Create an instruction which has the same operands and memory operands as MI but has a new opcode.

Definition at line 685 of file MipsInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addSym(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::get(), llvm::MachineOperand::getMCSymbol(), llvm::MachineOperand::getTargetFlags(), I, llvm::MachineOperand::isMCSymbol(), llvm::MipsII::MO_JALR, llvm::MachineInstr::removeOperand(), and TRI.

◆ getEquivalentCompactForm()

unsigned MipsInstrInfo::getEquivalentCompactForm ( const MachineBasicBlock::iterator  I) const

Determine the opcode of a non-delay slot form for a branch if one exists.

Return the corresponding compact (no delay slot) form of a branch.

Definition at line 452 of file MipsInstrInfo.cpp.

References llvm::MipsSubtarget::getABI(), llvm::MipsABIInfo::GetZeroReg(), llvm::MipsSubtarget::hasMips32r6(), I, llvm::MipsSubtarget::inMicroMipsMode(), and Subtarget.

◆ getInstSizeInBytes()

unsigned MipsInstrInfo::getInstSizeInBytes ( const MachineInstr &  MI) const
override

Return the number of bytes of code the specified instruction may be.

Definition at line 667 of file MipsInstrInfo.cpp.

References llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getTarget(), and MI.

◆ GetMemOperand()

MachineMemOperand * MipsInstrInfo::GetMemOperand ( MachineBasicBlock &  MBB,
int  FI,
MachineMemOperand::Flags  Flags 
) const
protected

Definition at line 79 of file MipsInstrInfo.cpp.

References llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), and MBB.

Referenced by llvm::Mips16InstrInfo::loadRegFromStack(), llvm::MipsSEInstrInfo::loadRegFromStack(), llvm::Mips16InstrInfo::storeRegToStack(), and llvm::MipsSEInstrInfo::storeRegToStack().

◆ getOppositeBranchOpc()

virtual unsigned llvm::MipsInstrInfo::getOppositeBranchOpc ( unsigned  Opc) const
pure virtual

Implemented in llvm::Mips16InstrInfo, and llvm::MipsSEInstrInfo.

Referenced by reverseBranchCondition().

◆ getRegisterInfo()

virtual const MipsRegisterInfo & llvm::MipsInstrInfo::getRegisterInfo ( ) const
pure virtual

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Implemented in llvm::Mips16InstrInfo, and llvm::MipsSEInstrInfo.

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

Definition at line 904 of file MipsInstrInfo.cpp.

◆ HasForbiddenSlot()

bool MipsInstrInfo::HasForbiddenSlot ( const MachineInstr &  MI) const

Predicate to determine if an instruction has a forbidden slot.

Predicate for distingushing instructions that have forbidden slots.

Definition at line 627 of file MipsInstrInfo.cpp.

References llvm::MipsII::HasForbiddenSlot, and MI.

◆ HasFPUDelaySlot()

bool MipsInstrInfo::HasFPUDelaySlot ( const MachineInstr &  MI) const

Predicate to determine if an instruction has an FPU delay slot.

Predicate for distingushing instructions that have FPU delay slots.

Definition at line 632 of file MipsInstrInfo.cpp.

References MI.

Referenced by SafeInFPUDelaySlot().

◆ HasLoadDelaySlot()

bool MipsInstrInfo::HasLoadDelaySlot ( const MachineInstr &  MI) const

Predicate to determine if an instruction has a load delay slot.

Predicate for distingushing instructions that have load delay slots.

Definition at line 651 of file MipsInstrInfo.cpp.

References MI.

◆ insertBranch()

unsigned MipsInstrInfo::insertBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock *  TBB,
MachineBasicBlock *  FBB,
ArrayRef< MachineOperand >  Cond,
const DebugLoc &  DL,
int *  BytesAdded = nullptr 
) const
override

Definition at line 134 of file MipsInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), MBB, TBB, and UncondBrOpc.

◆ insertNoop()

void MipsInstrInfo::insertNoop ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI 
) const
override

Insert nop instruction when hazard condition is found.

insertNoop - If data hazard condition is found insert the target nop instruction.

Definition at line 57 of file MipsInstrInfo.cpp.

References llvm::BuildMI(), DL, llvm::get(), MBB, and MI.

◆ insertNop()

MachineInstrBuilder MipsInstrInfo::insertNop ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
DebugLoc  DL 
) const

Insert an ISA appropriate nop.

Definition at line 64 of file MipsInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::get(), llvm::MipsSubtarget::hasMips32r6(), llvm::MipsSubtarget::inMicroMipsMode(), llvm::MipsSubtarget::inMips16Mode(), MBB, MI, and Subtarget.

◆ isAddImmediate()

std::optional< RegImmPair > MipsInstrInfo::isAddImmediate ( const MachineInstr &  MI,
Register  Reg 
) const
override

Definition at line 965 of file MipsInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), and MI.

Referenced by describeLoadedValue().

◆ isBranchOffsetInRange()

bool MipsInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
override

Determine if the branch target is in range.

Definition at line 292 of file MipsInstrInfo.cpp.

References llvm_unreachable.

◆ isBranchWithImm()

virtual bool llvm::MipsInstrInfo::isBranchWithImm ( unsigned  Opc) const
inlinevirtual

Reimplemented in llvm::MipsSEInstrInfo.

Definition at line 129 of file MipsInstrInfo.h.

◆ isZeroImm()

bool MipsInstrInfo::isZeroImm ( const MachineOperand &  op) const
protected

Definition at line 51 of file MipsInstrInfo.cpp.

References op.

Referenced by llvm::MipsSEInstrInfo::isLoadFromStackSlot(), and llvm::MipsSEInstrInfo::isStoreToStackSlot().

◆ loadRegFromStack()

virtual void llvm::MipsInstrInfo::loadRegFromStack ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
Register  DestReg,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI,
int64_t  Offset 
) const
pure virtual

Implemented in llvm::Mips16InstrInfo, and llvm::MipsSEInstrInfo.

Referenced by loadRegFromStackSlot().

◆ loadRegFromStackSlot()

void llvm::MipsInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MBBI,
Register  DestReg,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI,
Register  VReg 
) const
inlineoverride

Definition at line 145 of file MipsInstrInfo.h.

References loadRegFromStack(), MBB, MBBI, and TRI.

◆ removeBranch()

unsigned MipsInstrInfo::removeBranch ( MachineBasicBlock &  MBB,
int *  BytesRemoved = nullptr 
) const
override

Definition at line 168 of file MipsInstrInfo.cpp.

References assert(), I, MBB, llvm::MachineBasicBlock::rbegin(), and llvm::MachineBasicBlock::rend().

◆ reverseBranchCondition()

bool MipsInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.

Definition at line 196 of file MipsInstrInfo.cpp.

References assert(), Cond, and getOppositeBranchOpc().

◆ SafeInForbiddenSlot()

bool MipsInstrInfo::SafeInForbiddenSlot ( const MachineInstr &  MI) const

Predicate to determine if an instruction can go in a forbidden slot.

Predicate for distingushing between control transfer instructions and all other instructions for handling forbidden slots.

Consider inline assembly as unsafe as well.

Definition at line 577 of file MipsInstrInfo.cpp.

References llvm::MipsII::IsCTI, and MI.

◆ SafeInFPUDelaySlot()

bool MipsInstrInfo::SafeInFPUDelaySlot ( const MachineInstr &  MIInSlot,
const MachineInstr &  FPUMI 
) const

Predicate to determine if an instruction can go in an FPU delay slot.

Definition at line 584 of file MipsInstrInfo.cpp.

References llvm::MachineInstr::defs(), llvm::MachineInstr::getOpcode(), HasFPUDelaySlot(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::readsWritesVirtualRegister(), and Writes.

◆ SafeInLoadDelaySlot()

bool MipsInstrInfo::SafeInLoadDelaySlot ( const MachineInstr &  MIInSlot,
const MachineInstr &  LoadMI 
) const

Predicate to determine if an instruction can go in a load delay slot.

Predicate for distinguishing instructions that are hazardous in a load delay slot.

Consider inline assembly as unsafe as well.

Definition at line 616 of file MipsInstrInfo.cpp.

References llvm::any_of(), llvm::MachineInstr::defs(), and llvm::MachineInstr::isInlineAsm().

◆ storeRegToStack()

virtual void llvm::MipsInstrInfo::storeRegToStack ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
Register  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI,
int64_t  Offset 
) const
pure virtual

Implemented in llvm::Mips16InstrInfo, and llvm::MipsSEInstrInfo.

Referenced by storeRegToStackSlot().

◆ storeRegToStackSlot()

void llvm::MipsInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MBBI,
Register  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI,
Register  VReg 
) const
inlineoverride

Definition at line 136 of file MipsInstrInfo.h.

References MBB, MBBI, storeRegToStack(), and TRI.

◆ verifyInstruction()

bool MipsInstrInfo::verifyInstruction ( const MachineInstr &  MI,
StringRef &  ErrInfo 
) const
override

Perform target specific instruction verification.

Definition at line 850 of file MipsInstrInfo.cpp.

References MI, Subtarget, llvm::MipsSubtarget::useIndirectJumpsHazard(), and verifyInsExtInstruction().

Member Data Documentation

◆ Subtarget

const MipsSubtarget& llvm::MipsInstrInfo::Subtarget
protected

Definition at line 45 of file MipsInstrInfo.h.

Referenced by llvm::MipsSEInstrInfo::adjustStackPtr(), llvm::MipsSEInstrInfo::copyPhysReg(), llvm::MipsSEInstrInfo::expandPostRAPseudo(), getEquivalentCompactForm(), insertNop(), llvm::MipsSEInstrInfo::loadImmediate(), llvm::MipsSEInstrInfo::loadRegFromStack(), and verifyInstruction().

◆ UncondBrOpc

unsigned llvm::MipsInstrInfo::UncondBrOpc
protected

Definition at line 46 of file MipsInstrInfo.h.

Referenced by insertBranch().

The documentation for this class was generated from the following files:
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