LLVM 20.0.0git
MipsSEInstrInfo.cpp
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1//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsSEInstrInfo.h"
14#include "MipsAnalyzeImmediate.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/MC/TargetRegistry.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/MathExtras.h"
21
22using namespace llvm;
23
24static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
25 if (STI.inMicroMipsMode())
26 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
27 return STI.isPositionIndependent() ? Mips::B : Mips::J;
28}
29
30MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
31 : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {}
32
33const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
34 return RI;
35}
36
37/// isLoadFromStackSlot - If the specified machine instruction is a direct
38/// load from a stack slot, return the virtual or physical register number of
39/// the destination along with the FrameIndex of the loaded stack slot. If
40/// not, return 0. This predicate must return 0 if the instruction has
41/// any side effects other than loading from the stack slot.
42Register MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
43 int &FrameIndex) const {
44 unsigned Opc = MI.getOpcode();
45
46 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
47 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
48 if ((MI.getOperand(1).isFI()) && // is a stack slot
49 (MI.getOperand(2).isImm()) && // the imm is zero
50 (isZeroImm(MI.getOperand(2)))) {
51 FrameIndex = MI.getOperand(1).getIndex();
52 return MI.getOperand(0).getReg();
53 }
54 }
55
56 return 0;
57}
58
59/// isStoreToStackSlot - If the specified machine instruction is a direct
60/// store to a stack slot, return the virtual or physical register number of
61/// the source reg along with the FrameIndex of the loaded stack slot. If
62/// not, return 0. This predicate must return 0 if the instruction has
63/// any side effects other than storing to the stack slot.
64Register MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
65 int &FrameIndex) const {
66 unsigned Opc = MI.getOpcode();
67
68 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
69 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
70 if ((MI.getOperand(1).isFI()) && // is a stack slot
71 (MI.getOperand(2).isImm()) && // the imm is zero
72 (isZeroImm(MI.getOperand(2)))) {
73 FrameIndex = MI.getOperand(1).getIndex();
74 return MI.getOperand(0).getReg();
75 }
76 }
77 return 0;
78}
79
80void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator I,
82 const DebugLoc &DL, MCRegister DestReg,
83 MCRegister SrcReg, bool KillSrc,
84 bool RenamableDest, bool RenamableSrc) const {
85 unsigned Opc = 0, ZeroReg = 0;
86 bool isMicroMips = Subtarget.inMicroMipsMode();
87
88 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
89 if (Mips::GPR32RegClass.contains(SrcReg)) {
90 if (isMicroMips)
91 Opc = Mips::MOVE16_MM;
92 else
93 Opc = Mips::OR, ZeroReg = Mips::ZERO;
94 } else if (Mips::CCRRegClass.contains(SrcReg))
95 Opc = Mips::CFC1;
96 else if (Mips::FGR32RegClass.contains(SrcReg))
97 Opc = Mips::MFC1;
98 else if (Mips::HI32RegClass.contains(SrcReg)) {
99 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
100 SrcReg = 0;
101 } else if (Mips::LO32RegClass.contains(SrcReg)) {
102 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
103 SrcReg = 0;
104 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
105 Opc = Mips::MFHI_DSP;
106 else if (Mips::LO32DSPRegClass.contains(SrcReg))
107 Opc = Mips::MFLO_DSP;
108 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
109 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
110 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
111 return;
112 }
113 else if (Mips::MSACtrlRegClass.contains(SrcReg))
114 Opc = Mips::CFCMSA;
115 }
116 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
117 if (Mips::CCRRegClass.contains(DestReg))
118 Opc = Mips::CTC1;
119 else if (Mips::FGR32RegClass.contains(DestReg))
120 Opc = Mips::MTC1;
121 else if (Mips::HI32RegClass.contains(DestReg))
122 Opc = Mips::MTHI, DestReg = 0;
123 else if (Mips::LO32RegClass.contains(DestReg))
124 Opc = Mips::MTLO, DestReg = 0;
125 else if (Mips::HI32DSPRegClass.contains(DestReg))
126 Opc = Mips::MTHI_DSP;
127 else if (Mips::LO32DSPRegClass.contains(DestReg))
128 Opc = Mips::MTLO_DSP;
129 else if (Mips::DSPCCRegClass.contains(DestReg)) {
130 BuildMI(MBB, I, DL, get(Mips::WRDSP))
131 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
132 .addReg(DestReg, RegState::ImplicitDefine);
133 return;
134 } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
135 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
136 .addReg(DestReg)
137 .addReg(SrcReg, getKillRegState(KillSrc));
138 return;
139 }
140 }
141 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
142 Opc = Mips::FMOV_S;
143 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
144 Opc = Mips::FMOV_D32;
145 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
146 Opc = Mips::FMOV_D64;
147 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
148 if (Mips::GPR64RegClass.contains(SrcReg))
149 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
150 else if (Mips::HI64RegClass.contains(SrcReg))
151 Opc = Mips::MFHI64, SrcReg = 0;
152 else if (Mips::LO64RegClass.contains(SrcReg))
153 Opc = Mips::MFLO64, SrcReg = 0;
154 else if (Mips::FGR64RegClass.contains(SrcReg))
155 Opc = Mips::DMFC1;
156 }
157 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
158 if (Mips::HI64RegClass.contains(DestReg))
159 Opc = Mips::MTHI64, DestReg = 0;
160 else if (Mips::LO64RegClass.contains(DestReg))
161 Opc = Mips::MTLO64, DestReg = 0;
162 else if (Mips::FGR64RegClass.contains(DestReg))
163 Opc = Mips::DMTC1;
164 }
165 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
166 if (Mips::MSA128BRegClass.contains(SrcReg))
167 Opc = Mips::MOVE_V;
168 }
169
170 assert(Opc && "Cannot copy registers");
171
172 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
173
174 if (DestReg)
175 MIB.addReg(DestReg, RegState::Define);
176
177 if (SrcReg)
178 MIB.addReg(SrcReg, getKillRegState(KillSrc));
179
180 if (ZeroReg)
181 MIB.addReg(ZeroReg);
182}
183
184static bool isORCopyInst(const MachineInstr &MI) {
185 switch (MI.getOpcode()) {
186 default:
187 break;
188 case Mips::OR_MM:
189 case Mips::OR:
190 if (MI.getOperand(2).getReg() == Mips::ZERO)
191 return true;
192 break;
193 case Mips::OR64:
194 if (MI.getOperand(2).getReg() == Mips::ZERO_64)
195 return true;
196 break;
197 }
198 return false;
199}
200
201/// We check for the common case of 'or', as it's MIPS' preferred instruction
202/// for GPRs but we have to check the operands to ensure that is the case.
203/// Other move instructions for MIPS are directly identifiable.
204std::optional<DestSourcePair>
205MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
206 if (MI.isMoveReg() || isORCopyInst(MI))
207 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
208
209 return std::nullopt;
210}
211
212void MipsSEInstrInfo::
213storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
214 Register SrcReg, bool isKill, int FI,
215 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
216 int64_t Offset) const {
217 DebugLoc DL;
218 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
219
220 unsigned Opc = 0;
221
222 if (Mips::GPR32RegClass.hasSubClassEq(RC))
223 Opc = Mips::SW;
224 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
225 Opc = Mips::SD;
226 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
227 Opc = Mips::STORE_ACC64;
228 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
229 Opc = Mips::STORE_ACC64DSP;
230 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
231 Opc = Mips::STORE_ACC128;
232 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
233 Opc = Mips::STORE_CCOND_DSP;
234 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
235 Opc = Mips::SWC1;
236 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
237 Opc = Mips::SDC1;
238 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
239 Opc = Mips::SDC164;
240 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
241 Opc = Mips::ST_B;
242 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
243 TRI->isTypeLegalForClass(*RC, MVT::v8f16))
244 Opc = Mips::ST_H;
245 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
246 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
247 Opc = Mips::ST_W;
248 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
249 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
250 Opc = Mips::ST_D;
251 else if (Mips::LO32RegClass.hasSubClassEq(RC))
252 Opc = Mips::SW;
253 else if (Mips::LO64RegClass.hasSubClassEq(RC))
254 Opc = Mips::SD;
255 else if (Mips::HI32RegClass.hasSubClassEq(RC))
256 Opc = Mips::SW;
257 else if (Mips::HI64RegClass.hasSubClassEq(RC))
258 Opc = Mips::SD;
259 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
260 Opc = Mips::SWDSP;
261
262 // Hi, Lo are normally caller save but they are callee save
263 // for interrupt handling.
264 const Function &Func = MBB.getParent()->getFunction();
265 if (Func.hasFnAttribute("interrupt")) {
266 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
267 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
268 SrcReg = Mips::K0;
269 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
270 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
271 SrcReg = Mips::K0_64;
272 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
273 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
274 SrcReg = Mips::K0;
275 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
276 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
277 SrcReg = Mips::K0_64;
278 }
279 }
280
281 assert(Opc && "Register class not handled!");
282 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
283 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
284}
285
286void MipsSEInstrInfo::
287loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
288 Register DestReg, int FI, const TargetRegisterClass *RC,
289 const TargetRegisterInfo *TRI, int64_t Offset) const {
290 DebugLoc DL;
291 if (I != MBB.end()) DL = I->getDebugLoc();
292 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
293 unsigned Opc = 0;
294
295 const Function &Func = MBB.getParent()->getFunction();
296 bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") &&
297 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
298 DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
299
300 if (Mips::GPR32RegClass.hasSubClassEq(RC))
301 Opc = Mips::LW;
302 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
303 Opc = Mips::LD;
304 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
305 Opc = Mips::LOAD_ACC64;
306 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
307 Opc = Mips::LOAD_ACC64DSP;
308 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
309 Opc = Mips::LOAD_ACC128;
310 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
311 Opc = Mips::LOAD_CCOND_DSP;
312 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
313 Opc = Mips::LWC1;
314 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
315 Opc = Mips::LDC1;
316 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
317 Opc = Mips::LDC164;
318 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
319 Opc = Mips::LD_B;
320 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
321 TRI->isTypeLegalForClass(*RC, MVT::v8f16))
322 Opc = Mips::LD_H;
323 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
324 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
325 Opc = Mips::LD_W;
326 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
327 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
328 Opc = Mips::LD_D;
329 else if (Mips::HI32RegClass.hasSubClassEq(RC))
330 Opc = Mips::LW;
331 else if (Mips::HI64RegClass.hasSubClassEq(RC))
332 Opc = Mips::LD;
333 else if (Mips::LO32RegClass.hasSubClassEq(RC))
334 Opc = Mips::LW;
335 else if (Mips::LO64RegClass.hasSubClassEq(RC))
336 Opc = Mips::LD;
337 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
338 Opc = Mips::LWDSP;
339
340 assert(Opc && "Register class not handled!");
341
342 if (!ReqIndirectLoad)
343 BuildMI(MBB, I, DL, get(Opc), DestReg)
344 .addFrameIndex(FI)
345 .addImm(Offset)
346 .addMemOperand(MMO);
347 else {
348 // Load HI/LO through K0. Notably the DestReg is encoded into the
349 // instruction itself.
350 unsigned Reg = Mips::K0;
351 unsigned LdOp = Mips::MTLO;
352 if (DestReg == Mips::HI0)
353 LdOp = Mips::MTHI;
354
355 if (Subtarget.getABI().ArePtrs64bit()) {
356 Reg = Mips::K0_64;
357 if (DestReg == Mips::HI0_64)
358 LdOp = Mips::MTHI64;
359 else
360 LdOp = Mips::MTLO64;
361 }
362
363 BuildMI(MBB, I, DL, get(Opc), Reg)
364 .addFrameIndex(FI)
365 .addImm(Offset)
366 .addMemOperand(MMO);
367 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
368 }
369}
370
371bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
372 MachineBasicBlock &MBB = *MI.getParent();
373 bool isMicroMips = Subtarget.inMicroMipsMode();
374 unsigned Opc;
375
376 switch (MI.getDesc().getOpcode()) {
377 default:
378 return false;
379 case Mips::RetRA:
380 expandRetRA(MBB, MI);
381 break;
382 case Mips::ERet:
383 expandERet(MBB, MI);
384 break;
385 case Mips::PseudoMFHI:
386 expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
387 break;
388 case Mips::PseudoMFHI_MM:
389 expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
390 break;
391 case Mips::PseudoMFLO:
392 expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
393 break;
394 case Mips::PseudoMFLO_MM:
395 expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
396 break;
397 case Mips::PseudoMFHI64:
398 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
399 break;
400 case Mips::PseudoMFLO64:
401 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
402 break;
403 case Mips::PseudoMTLOHI:
404 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
405 break;
406 case Mips::PseudoMTLOHI64:
407 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
408 break;
409 case Mips::PseudoMTLOHI_DSP:
410 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
411 break;
412 case Mips::PseudoMTLOHI_MM:
413 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
414 break;
415 case Mips::PseudoCVT_S_W:
416 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
417 break;
418 case Mips::PseudoCVT_D32_W:
419 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
420 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
421 break;
422 case Mips::PseudoCVT_S_L:
423 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
424 break;
425 case Mips::PseudoCVT_D64_W:
426 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
427 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
428 break;
429 case Mips::PseudoCVT_D64_L:
430 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
431 break;
432 case Mips::BuildPairF64:
433 expandBuildPairF64(MBB, MI, isMicroMips, false);
434 break;
435 case Mips::BuildPairF64_64:
436 expandBuildPairF64(MBB, MI, isMicroMips, true);
437 break;
438 case Mips::ExtractElementF64:
439 expandExtractElementF64(MBB, MI, isMicroMips, false);
440 break;
441 case Mips::ExtractElementF64_64:
442 expandExtractElementF64(MBB, MI, isMicroMips, true);
443 break;
444 case Mips::MIPSeh_return32:
445 case Mips::MIPSeh_return64:
446 expandEhReturn(MBB, MI);
447 break;
448 }
449
450 MBB.erase(MI);
451 return true;
452}
453
454/// isBranchWithImm - Return true if the branch contains an immediate
455/// operand (\see lib/Target/Mips/MipsBranchExpansion.cpp).
456bool MipsSEInstrInfo::isBranchWithImm(unsigned Opc) const {
457 switch (Opc) {
458 default:
459 return false;
460 case Mips::BBIT0:
461 case Mips::BBIT1:
462 case Mips::BBIT032:
463 case Mips::BBIT132:
464 return true;
465 }
466}
467
468/// getOppositeBranchOpc - Return the inverse of the specified
469/// opcode, e.g. turning BEQ to BNE.
470unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
471 switch (Opc) {
472 default: llvm_unreachable("Illegal opcode!");
473 case Mips::BEQ: return Mips::BNE;
474 case Mips::BEQ_MM: return Mips::BNE_MM;
475 case Mips::BNE: return Mips::BEQ;
476 case Mips::BNE_MM: return Mips::BEQ_MM;
477 case Mips::BGTZ: return Mips::BLEZ;
478 case Mips::BGEZ: return Mips::BLTZ;
479 case Mips::BLTZ: return Mips::BGEZ;
480 case Mips::BLEZ: return Mips::BGTZ;
481 case Mips::BGTZ_MM: return Mips::BLEZ_MM;
482 case Mips::BGEZ_MM: return Mips::BLTZ_MM;
483 case Mips::BLTZ_MM: return Mips::BGEZ_MM;
484 case Mips::BLEZ_MM: return Mips::BGTZ_MM;
485 case Mips::BEQ64: return Mips::BNE64;
486 case Mips::BNE64: return Mips::BEQ64;
487 case Mips::BGTZ64: return Mips::BLEZ64;
488 case Mips::BGEZ64: return Mips::BLTZ64;
489 case Mips::BLTZ64: return Mips::BGEZ64;
490 case Mips::BLEZ64: return Mips::BGTZ64;
491 case Mips::BC1T: return Mips::BC1F;
492 case Mips::BC1F: return Mips::BC1T;
493 case Mips::BC1T_MM: return Mips::BC1F_MM;
494 case Mips::BC1F_MM: return Mips::BC1T_MM;
495 case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
496 case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
497 case Mips::BEQZC_MM: return Mips::BNEZC_MM;
498 case Mips::BNEZC_MM: return Mips::BEQZC_MM;
499 case Mips::BEQZC: return Mips::BNEZC;
500 case Mips::BNEZC: return Mips::BEQZC;
501 case Mips::BLEZC: return Mips::BGTZC;
502 case Mips::BGEZC: return Mips::BLTZC;
503 case Mips::BGEC: return Mips::BLTC;
504 case Mips::BGTZC: return Mips::BLEZC;
505 case Mips::BLTZC: return Mips::BGEZC;
506 case Mips::BLTC: return Mips::BGEC;
507 case Mips::BGEUC: return Mips::BLTUC;
508 case Mips::BLTUC: return Mips::BGEUC;
509 case Mips::BEQC: return Mips::BNEC;
510 case Mips::BNEC: return Mips::BEQC;
511 case Mips::BC1EQZ: return Mips::BC1NEZ;
512 case Mips::BC1NEZ: return Mips::BC1EQZ;
513 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6;
514 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6;
515 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
516 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
517 case Mips::BGEC_MMR6: return Mips::BLTC_MMR6;
518 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
519 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
520 case Mips::BLTC_MMR6: return Mips::BGEC_MMR6;
521 case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6;
522 case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6;
523 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
524 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
525 case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
526 case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
527 case Mips::BEQZC64: return Mips::BNEZC64;
528 case Mips::BNEZC64: return Mips::BEQZC64;
529 case Mips::BEQC64: return Mips::BNEC64;
530 case Mips::BNEC64: return Mips::BEQC64;
531 case Mips::BGEC64: return Mips::BLTC64;
532 case Mips::BGEUC64: return Mips::BLTUC64;
533 case Mips::BLTC64: return Mips::BGEC64;
534 case Mips::BLTUC64: return Mips::BGEUC64;
535 case Mips::BGTZC64: return Mips::BLEZC64;
536 case Mips::BGEZC64: return Mips::BLTZC64;
537 case Mips::BLTZC64: return Mips::BGEZC64;
538 case Mips::BLEZC64: return Mips::BGTZC64;
539 case Mips::BBIT0: return Mips::BBIT1;
540 case Mips::BBIT1: return Mips::BBIT0;
541 case Mips::BBIT032: return Mips::BBIT132;
542 case Mips::BBIT132: return Mips::BBIT032;
543 case Mips::BZ_B: return Mips::BNZ_B;
544 case Mips::BZ_H: return Mips::BNZ_H;
545 case Mips::BZ_W: return Mips::BNZ_W;
546 case Mips::BZ_D: return Mips::BNZ_D;
547 case Mips::BZ_V: return Mips::BNZ_V;
548 case Mips::BNZ_B: return Mips::BZ_B;
549 case Mips::BNZ_H: return Mips::BZ_H;
550 case Mips::BNZ_W: return Mips::BZ_W;
551 case Mips::BNZ_D: return Mips::BZ_D;
552 case Mips::BNZ_V: return Mips::BZ_V;
553 }
554}
555
556/// Adjust SP by Amount bytes.
557void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
558 MachineBasicBlock &MBB,
559 MachineBasicBlock::iterator I) const {
560 MipsABIInfo ABI = Subtarget.getABI();
561 DebugLoc DL;
562 unsigned ADDiu = ABI.GetPtrAddiuOp();
563
564 if (Amount == 0)
565 return;
566
567 if (isInt<16>(Amount)) {
568 // addi sp, sp, amount
569 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
570 } else {
571 // For numbers which are not 16bit integers we synthesize Amount inline
572 // then add or subtract it from sp.
573 unsigned Opc = ABI.GetPtrAdduOp();
574 if (Amount < 0) {
575 Opc = ABI.GetPtrSubuOp();
576 Amount = -Amount;
577 }
578 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
579 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
580 }
581}
582
583/// This function generates the sequence of instructions needed to get the
584/// result of adding register REG and immediate IMM.
585unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
586 MachineBasicBlock::iterator II,
587 const DebugLoc &DL,
588 unsigned *NewImm) const {
589 MipsAnalyzeImmediate AnalyzeImm;
590 const MipsSubtarget &STI = Subtarget;
591 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
592 unsigned Size = STI.isABI_N64() ? 64 : 32;
593 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
594 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
595 const TargetRegisterClass *RC = STI.isABI_N64() ?
596 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
597 bool LastInstrIsADDiu = NewImm;
598
599 const MipsAnalyzeImmediate::InstSeq &Seq =
600 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
601 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
602
603 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
604
605 // The first instruction can be a LUi, which is different from other
606 // instructions (ADDiu, ORI and SLL) in that it does not have a register
607 // operand.
608 Register Reg = RegInfo.createVirtualRegister(RC);
609
610 if (Inst->Opc == LUi)
611 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
612 else
613 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
614 .addImm(SignExtend64<16>(Inst->ImmOpnd));
615
616 // Build the remaining instructions in Seq.
617 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
618 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
619 .addImm(SignExtend64<16>(Inst->ImmOpnd));
620
621 if (LastInstrIsADDiu)
622 *NewImm = Inst->ImmOpnd;
623
624 return Reg;
625}
626
627unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
628 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
629 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
630 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
631 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
632 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
633 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
634 Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM ||
635 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC ||
636 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC ||
637 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC ||
638 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC ||
639 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
640 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
641 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
642 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
643 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
644 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
645 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 ||
646 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
647 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
648 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
649 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
650 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
651 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
652}
653
654void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
655 MachineBasicBlock::iterator I) const {
656
657 MachineInstrBuilder MIB;
658 if (Subtarget.isGP64bit())
659 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
660 .addReg(Mips::RA_64, RegState::Undef);
661 else
662 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
663 .addReg(Mips::RA, RegState::Undef);
664
665 // Retain any imp-use flags.
666 for (auto & MO : I->operands()) {
667 if (MO.isImplicit())
668 MIB.add(MO);
669 }
670}
671
672void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
673 MachineBasicBlock::iterator I) const {
674 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
675}
676
677std::pair<bool, bool>
678MipsSEInstrInfo::compareOpndSize(unsigned Opc,
679 const MachineFunction &MF) const {
680 const MCInstrDesc &Desc = get(Opc);
681 assert(Desc.NumOperands == 2 && "Unary instruction expected.");
682 const MipsRegisterInfo *RI = &getRegisterInfo();
683 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
684 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
685
686 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
687}
688
689void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
690 MachineBasicBlock::iterator I,
691 unsigned NewOpc) const {
692 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
693}
694
695void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
696 MachineBasicBlock::iterator I,
697 unsigned LoOpc,
698 unsigned HiOpc,
699 bool HasExplicitDef) const {
700 // Expand
701 // lo_hi pseudomtlohi $gpr0, $gpr1
702 // to these two instructions:
703 // mtlo $gpr0
704 // mthi $gpr1
705
706 DebugLoc DL = I->getDebugLoc();
707 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
708 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
709 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
710
711 // Add lo/hi registers if the mtlo/hi instructions created have explicit
712 // def registers.
713 if (HasExplicitDef) {
714 Register DstReg = I->getOperand(0).getReg();
715 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
716 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
717 LoInst.addReg(DstLo, RegState::Define);
718 HiInst.addReg(DstHi, RegState::Define);
719 }
720
721 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
722 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
723}
724
725void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
726 MachineBasicBlock::iterator I,
727 unsigned CvtOpc, unsigned MovOpc,
728 bool IsI64) const {
729 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
730 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
731 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
732 unsigned KillSrc = getKillRegState(Src.isKill());
733 DebugLoc DL = I->getDebugLoc();
734 bool DstIsLarger, SrcIsLarger;
735
736 std::tie(DstIsLarger, SrcIsLarger) =
737 compareOpndSize(CvtOpc, *MBB.getParent());
738
739 if (DstIsLarger)
740 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
741
742 if (SrcIsLarger)
743 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
744
745 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
746 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
747}
748
749void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
750 MachineBasicBlock::iterator I,
751 bool isMicroMips,
752 bool FP64) const {
753 Register DstReg = I->getOperand(0).getReg();
754 Register SrcReg = I->getOperand(1).getReg();
755 unsigned N = I->getOperand(2).getImm();
756 DebugLoc dl = I->getDebugLoc();
757
758 assert(N < 2 && "Invalid immediate");
759 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
760 Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
761
762 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
763 // in MipsSEFrameLowering.cpp.
764 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
765
766 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
767 // in MipsSEFrameLowering.cpp.
768 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
769
770 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
771 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
772 // claim to read the whole 64-bits as part of a white lie used to
773 // temporarily work around a widespread bug in the -mfp64 support.
774 // The problem is that none of the 32-bit fpu ops mention the fact
775 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
776 // requires a major overhaul of the FPU implementation which can't
777 // be done right now due to time constraints.
778 // MFHC1 is one of two instructions that are affected since they are
779 // the only instructions that don't read the lower 32-bits.
780 // We therefore pretend that it reads the bottom 32-bits to
781 // artificially create a dependency and prevent the scheduler
782 // changing the behaviour of the code.
783 BuildMI(MBB, I, dl,
784 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
785 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
786 DstReg)
787 .addReg(SrcReg);
788 } else
789 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
790}
791
792void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
793 MachineBasicBlock::iterator I,
794 bool isMicroMips, bool FP64) const {
795 Register DstReg = I->getOperand(0).getReg();
796 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
797 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
798 DebugLoc dl = I->getDebugLoc();
799 const TargetRegisterInfo &TRI = getRegisterInfo();
800
801 // When mthc1 is available, use:
802 // mtc1 Lo, $fp
803 // mthc1 Hi, $fp
804 //
805 // Otherwise, for O32 FPXX ABI:
806 // spill + reload via ldc1
807 // This case is handled by the frame lowering code.
808 //
809 // Otherwise, for FP32:
810 // mtc1 Lo, $fp
811 // mtc1 Hi, $fp + 1
812 //
813 // The case where dmtc1 is available doesn't need to be handled here
814 // because it never creates a BuildPairF64 node.
815
816 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
817 // in MipsSEFrameLowering.cpp.
818 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
819
820 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
821 // in MipsSEFrameLowering.cpp.
822 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
823
824 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
825 .addReg(LoReg);
826
827 if (Subtarget.hasMTHC1()) {
828 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
829 // around a widespread bug in the -mfp64 support.
830 // The problem is that none of the 32-bit fpu ops mention the fact
831 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
832 // requires a major overhaul of the FPU implementation which can't
833 // be done right now due to time constraints.
834 // MTHC1 is one of two instructions that are affected since they are
835 // the only instructions that don't read the lower 32-bits.
836 // We therefore pretend that it reads the bottom 32-bits to
837 // artificially create a dependency and prevent the scheduler
838 // changing the behaviour of the code.
839 BuildMI(MBB, I, dl,
840 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
841 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
842 DstReg)
843 .addReg(DstReg)
844 .addReg(HiReg);
845 } else if (Subtarget.isABI_FPXX())
846 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
847 else
848 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
849 .addReg(HiReg);
850}
851
852void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
853 MachineBasicBlock::iterator I) const {
854 // This pseudo instruction is generated as part of the lowering of
855 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
856 // indirect jump to TargetReg
857 MipsABIInfo ABI = Subtarget.getABI();
858 unsigned ADDU = ABI.GetPtrAdduOp();
859 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
860 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
861 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
862 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
863 Register OffsetReg = I->getOperand(0).getReg();
864 Register TargetReg = I->getOperand(1).getReg();
865
866 // addu $ra, $v0, $zero
867 // addu $sp, $sp, $v1
868 // jr $ra (via RetRA)
869 const TargetMachine &TM = MBB.getParent()->getTarget();
870 if (TM.isPositionIndependent())
871 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
872 .addReg(TargetReg)
873 .addReg(ZERO);
874 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
875 .addReg(TargetReg)
876 .addReg(ZERO);
877 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
878 expandRetRA(MBB, I);
879}
880
881const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
882 return new MipsSEInstrInfo(STI);
883}
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
getRegClass
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
Definition: AArch64InstrInfo.cpp:4575
MBB
MachineBasicBlock & MBB
Definition: ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: ARMSLSHardening.cpp:73
BlockExecWeight::ZERO
@ ZERO
Special weight used for cases with exact zero probability.
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:112
I
#define I(x, y, z)
Definition: MD5.cpp:58
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1944
isORCopyInst
static bool isORCopyInst(const MachineInstr &MI)
Definition: MipsSEInstrInfo.cpp:184
getUnconditionalBranch
static unsigned getUnconditionalBranch(const MipsSubtarget &STI)
Definition: MipsSEInstrInfo.cpp:24
isMicroMips
static bool isMicroMips(const MCSubtargetInfo *STI)
Definition: MipsTargetStreamer.cpp:40
II
uint64_t IntrinsicInst * II
Definition: NVVMIntrRange.cpp:51
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
contains
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:311
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1443
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:724
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:685
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:710
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:133
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:226
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:154
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:99
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:204
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:69
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:129
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:136
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:138
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:369
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:157
llvm::MipsABIInfo::ArePtrs64bit
bool ArePtrs64bit() const
Definition: MipsABIInfo.h:73
llvm::MipsAnalyzeImmediate::Analyze
const InstSeq & Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu)
Analyze - Get an instruction sequence to load immediate Imm.
Definition: MipsAnalyzeImmediate.cpp:129
llvm::MipsInstrInfo::Subtarget
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:45
llvm::MipsInstrInfo::GetMemOperand
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
Definition: MipsInstrInfo.cpp:80
llvm::MipsInstrInfo::isZeroImm
bool isZeroImm(const MachineOperand &op) const
Definition: MipsInstrInfo.cpp:52
llvm::MipsSEInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
Definition: MipsSEInstrInfo.cpp:80
llvm::MipsSEInstrInfo::isLoadFromStackSlot
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Definition: MipsSEInstrInfo.cpp:42
llvm::MipsSEInstrInfo::isStoreToStackSlot
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition: MipsSEInstrInfo.cpp:64
llvm::MipsSEInstrInfo::adjustStackPtr
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
Definition: MipsSEInstrInfo.cpp:557
llvm::MipsSEInstrInfo::loadRegFromStack
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
Definition: MipsSEInstrInfo.cpp:287
llvm::MipsSEInstrInfo::isCopyInstrImpl
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: MipsSEInstrInfo.cpp:205
llvm::MipsSEInstrInfo::loadImmediate
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
Definition: MipsSEInstrInfo.cpp:585
llvm::MipsSEInstrInfo::isBranchWithImm
bool isBranchWithImm(unsigned Opc) const override
isBranchWithImm - Return true if the branch contains an immediate operand (
Definition: MipsSEInstrInfo.cpp:456
llvm::MipsSEInstrInfo::MipsSEInstrInfo
MipsSEInstrInfo(const MipsSubtarget &STI)
Definition: MipsSEInstrInfo.cpp:30
llvm::MipsSEInstrInfo::storeRegToStack
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
Definition: MipsSEInstrInfo.cpp:213
llvm::MipsSEInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: MipsSEInstrInfo.cpp:371
llvm::MipsSEInstrInfo::getRegisterInfo
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: MipsSEInstrInfo.cpp:33
llvm::MipsSEInstrInfo::getOppositeBranchOpc
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
Definition: MipsSEInstrInfo.cpp:470
llvm::MipsSubtarget::isFP64bit
bool isFP64bit() const
Definition: MipsSubtarget.h:290
llvm::MipsSubtarget::inMicroMipsMode
bool inMicroMipsMode() const
Definition: MipsSubtarget.h:317
llvm::MipsSubtarget::isABI_N64
bool isABI_N64() const
Definition: MipsSubtarget.cpp:284
llvm::MipsSubtarget::useOddSPReg
bool useOddSPReg() const
Definition: MipsSubtarget.h:291
llvm::MipsSubtarget::isABI_FPXX
bool isABI_FPXX() const
Definition: MipsSubtarget.h:238
llvm::MipsSubtarget::isPositionIndependent
bool isPositionIndependent() const
Definition: MipsSubtarget.cpp:228
llvm::MipsSubtarget::isGP64bit
bool isGP64bit() const
Definition: MipsSubtarget.h:295
llvm::MipsSubtarget::hasMips32r2
bool hasMips32r2() const
Definition: MipsSubtarget.h:262
llvm::MipsSubtarget::hasMTHC1
bool hasMTHC1() const
Definition: MipsSubtarget.h:351
llvm::MipsSubtarget::getABI
const MipsABIInfo & getABI() const
Definition: MipsSubtarget.cpp:287
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallVectorBase::size
size_t size() const
Definition: SmallVector.h:78
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:235
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:48
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:46
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:50
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:54
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:480
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:373
llvm::createMipsSEInstrInfo
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
Definition: MipsSEInstrInfo.cpp:881
llvm::get
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
Definition: PointerIntPair.h:270
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:555
N
#define N
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
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