13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
35 int &FrameIndex)
const override;
43 int &FrameIndex)
const override;
47 bool KillSrc)
const override;
51 Register SrcReg,
bool isKill,
int FrameIndex,
54 int64_t
Offset)
const override;
61 int64_t
Offset)
const override;
78 unsigned *NewImm)
const;
84 std::optional<DestSourcePair>
88 unsigned getAnalyzableBrOpc(
unsigned Opc)
const override;
94 std::pair<bool, bool> compareOpndSize(
unsigned Opc,
98 unsigned NewOpc)
const;
101 unsigned LoOpc,
unsigned HiOpc,
102 bool HasExplicitDef)
const;
115 unsigned CvtOpc,
unsigned MovOpc,
bool IsI64)
const;
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned const TargetRegisterInfo * TRI
static bool isMicroMips(const MCSubtargetInfo *STI)
uint64_t IntrinsicInst * II
Wrapper class representing physical registers. Should be passed by value.
Representation of each machine instruction.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
bool isBranchWithImm(unsigned Opc) const override
isBranchWithImm - Return true if the branch contains an immediate operand (
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
Wrapper class representing virtual and physical registers.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.