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LLVM 20.0.0git
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This is the complete list of members for llvm::PPCInstrInfo, including all inherited members.
| analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override | llvm::PPCInstrInfo | |
| analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override | llvm::PPCInstrInfo | |
| analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override | llvm::PPCInstrInfo | |
| areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override | llvm::PPCInstrInfo | |
| canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override | llvm::PPCInstrInfo | |
| ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override | llvm::PPCInstrInfo | |
| combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const | llvm::PPCInstrInfo | |
| commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override | llvm::PPCInstrInfo | protected |
| convertToImmediateForm(MachineInstr &MI, SmallSet< Register, 4 > &RegsToUpdate, MachineInstr **KilledDef=nullptr) const | llvm::PPCInstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override | llvm::PPCInstrInfo | |
| CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override | llvm::PPCInstrInfo | |
| CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override | llvm::PPCInstrInfo | |
| decomposeMachineOperandsTargetFlags(unsigned TF) const override | llvm::PPCInstrInfo | |
| expandPostRAPseudo(MachineInstr &MI) const override | llvm::PPCInstrInfo | |
| expandVSXMemPseudo(MachineInstr &MI) const | llvm::PPCInstrInfo | |
| finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override | llvm::PPCInstrInfo | |
| findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override | llvm::PPCInstrInfo | |
| findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const | llvm::PPCInstrInfo | |
| foldFrameOffset(MachineInstr &MI) const | llvm::PPCInstrInfo | |
| foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override | llvm::PPCInstrInfo | |
| genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override | llvm::PPCInstrInfo | |
| getCombinerObjective(unsigned Pattern) const override | llvm::PPCInstrInfo | |
| getConstantFromConstantPool(MachineInstr *I) const | llvm::PPCInstrInfo | |
| getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const | llvm::PPCInstrInfo | |
| getExtendResourceLenLimit() const override | llvm::PPCInstrInfo | inline |
| getFMAPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const | llvm::PPCInstrInfo | |
| getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override | llvm::PPCInstrInfo | |
| getInstSizeInBytes(const MachineInstr &MI) const override | llvm::PPCInstrInfo | |
| getLoadOpcodeForSpill(const TargetRegisterClass *RC) const | llvm::PPCInstrInfo | |
| getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override | llvm::PPCInstrInfo | |
| getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override | llvm::PPCInstrInfo | |
| getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const | llvm::PPCInstrInfo | |
| getNop() const override | llvm::PPCInstrInfo | |
| getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override | llvm::PPCInstrInfo | |
| getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override | llvm::PPCInstrInfo | inline |
| getRecordFormOpcode(unsigned Opcode) | llvm::PPCInstrInfo | static |
| getRegisterInfo() const | llvm::PPCInstrInfo | inline |
| getSerializableDirectMachineOperandTargetFlags() const override | llvm::PPCInstrInfo | |
| getStoreOpcodeForSpill(const TargetRegisterClass *RC) const | llvm::PPCInstrInfo | |
| hasGOTFlag(unsigned TF) | llvm::PPCInstrInfo | inlinestatic |
| hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override | llvm::PPCInstrInfo | inline |
| hasPCRelFlag(unsigned TF) | llvm::PPCInstrInfo | inlinestatic |
| hasTLSFlag(unsigned TF) | llvm::PPCInstrInfo | inlinestatic |
| insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::PPCInstrInfo | |
| insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::PPCInstrInfo | |
| insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override | llvm::PPCInstrInfo | |
| instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const | llvm::PPCInstrInfo | |
| isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const | llvm::PPCInstrInfo | |
| isADDInstrEligibleForFolding(MachineInstr &ADDMI) const | llvm::PPCInstrInfo | |
| isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override | llvm::PPCInstrInfo | |
| isBDNZ(unsigned Opcode) const | llvm::PPCInstrInfo | |
| isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override | llvm::PPCInstrInfo | |
| isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const | llvm::PPCInstrInfo | |
| isLoadFromConstantPool(MachineInstr *I) const | llvm::PPCInstrInfo | |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::PPCInstrInfo | |
| isPredicated(const MachineInstr &MI) const override | llvm::PPCInstrInfo | |
| isPrefixed(unsigned Opcode) const | llvm::PPCInstrInfo | inline |
| isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override | llvm::PPCInstrInfo | inline |
| isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override | llvm::PPCInstrInfo | inline |
| isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override | llvm::PPCInstrInfo | |
| isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override | llvm::PPCInstrInfo | inline |
| isReallyTriviallyReMaterializable(const MachineInstr &MI) const override | llvm::PPCInstrInfo | |
| isSameClassPhysRegCopy(unsigned Opcode) | llvm::PPCInstrInfo | inlinestatic |
| isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override | llvm::PPCInstrInfo | |
| isSExt32To64(unsigned Opcode) const | llvm::PPCInstrInfo | inline |
| isSignExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const | llvm::PPCInstrInfo | inline |
| isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const | llvm::PPCInstrInfo | |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::PPCInstrInfo | |
| isTOCSaveMI(const MachineInstr &MI) const | llvm::PPCInstrInfo | |
| isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const | llvm::PPCInstrInfo | |
| isXFormMemOp(unsigned Opcode) const | llvm::PPCInstrInfo | inline |
| isZeroExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const | llvm::PPCInstrInfo | inline |
| isZExt32To64(unsigned Opcode) const | llvm::PPCInstrInfo | inline |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override | llvm::PPCInstrInfo | |
| loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const | llvm::PPCInstrInfo | |
| materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const | llvm::PPCInstrInfo | |
| onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const | llvm::PPCInstrInfo | |
| optimizeCmpPostRA(MachineInstr &MI) const | llvm::PPCInstrInfo | |
| optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override | llvm::PPCInstrInfo | |
| PPCInstrInfo(PPCSubtarget &STI) | llvm::PPCInstrInfo | explicit |
| PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override | llvm::PPCInstrInfo | |
| removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::PPCInstrInfo | |
| replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const | llvm::PPCInstrInfo | |
| replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const | llvm::PPCInstrInfo | |
| reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::PPCInstrInfo | |
| setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const | llvm::PPCInstrInfo | |
| setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const | llvm::PPCInstrInfo | inline |
| shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override | llvm::PPCInstrInfo | |
| shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override | llvm::PPCInstrInfo | |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override | llvm::PPCInstrInfo | |
| storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const | llvm::PPCInstrInfo | |
| SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override | llvm::PPCInstrInfo | |
| updatedRC(const TargetRegisterClass *RC) const | llvm::PPCInstrInfo | |
| useMachineCombiner() const override | llvm::PPCInstrInfo | inline |
1.9.6