llvm::PPCInstrInfo Class Reference

#include "Target/PowerPC/PPCInstrInfo.h"

Inheritance diagram for llvm::PPCInstrInfo:

Public Member Functions
	PPCInstrInfo (const PPCSubtarget &STI)
bool	isLoadFromConstantPool (MachineInstr *I) const
const Constant *	getConstantFromConstantPool (MachineInstr *I) const
const PPCRegisterInfo &	getRegisterInfo () const
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
const TargetRegisterClass *	getInlineAsmMemoryOperandRegClass (InlineAsm::ConstraintCode C) const override
bool	isXFormMemOp (unsigned Opcode) const
bool	isPrefixed (unsigned Opcode) const
bool	isSExt32To64 (unsigned Opcode) const
bool	isZExt32To64 (unsigned Opcode) const
bool	isMemriOp (unsigned Opcode) const
ScheduleHazardRecognizer *	CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
	CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.
ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
	CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.
unsigned	getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
std::optional< unsigned >	getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
std::optional< unsigned >	getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
bool	hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
bool	useMachineCombiner () const override
void	genAlternativeCodeSequence (MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const override
	When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
bool	getFMAPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const
	Return true when there is potentially a faster code sequence for a fma chain ending in Root.
CombinerObjective	getCombinerObjective (unsigned Pattern) const override
bool	getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
	Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.
bool	shouldReduceRegisterPressure (const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override
	On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB.
void	finalizeInsInstrs (MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
	Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
bool	isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert) const override
int	getExtendResourceLenLimit () const override
	On PowerPC, we try to reassociate FMA chain which will increase instruction size.
void	setSpecialOperandAttr (MachineInstr &MI, uint32_t Flags) const
bool	isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
bool	isReMaterializableImpl (const MachineInstr &MI) const override
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
void	insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool	canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, SelectExpansion &) const override
void	insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	storeRegToStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC) const
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, unsigned SubReg=0, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	loadRegFromStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC) const
unsigned	getStoreOpcodeForSpill (const TargetRegisterClass *RC) const
unsigned	getLoadOpcodeForSpill (const TargetRegisterClass *RC) const
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	foldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
bool	onlyFoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
bool	isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool	isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool	isPredicated (const MachineInstr &MI) const override
bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool	PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool	SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool	ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool	analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
bool	optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
bool	getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width) const
	Return true if get the base operand, byte offset of an instruction and the memory width.
bool	optimizeCmpPostRA (MachineInstr &MI) const
bool	getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const override
	Get the base operand and byte offset of an instruction that reads/writes memory.
bool	shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
	Returns true if the two given memory operations should be scheduled adjacent.
bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
	Return true if two MIs access different memory addresses and false otherwise.
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	GetInstSize - Return the number of bytes of code the specified instruction may be.
InstSizeVerifyMode	getInstSizeVerifyMode (const MachineInstr &MI) const override
MCInst	getNop () const override
	Return the noop instruction to use for a noop.
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
bool	expandVSXMemPseudo (MachineInstr &MI) const
bool	expandPostRAPseudo (MachineInstr &MI) const override
bool	expandAMOCSNEPseudo (MachineInstr &MI) const
const TargetRegisterClass *	updatedRC (const TargetRegisterClass *RC) const
bool	isTOCSaveMI (const MachineInstr &MI) const
std::pair< bool, bool >	isSignOrZeroExtended (const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const
bool	isSignExtended (const unsigned Reg, const MachineRegisterInfo *MRI) const
bool	isZeroExtended (const unsigned Reg, const MachineRegisterInfo *MRI) const
void	promoteInstr32To64ForElimEXTSW (const Register &Reg, MachineRegisterInfo *MRI, unsigned BinOpDepth) const
bool	convertToImmediateForm (MachineInstr &MI, SmallSet< Register, 4 > &RegsToUpdate, MachineInstr **KilledDef=nullptr) const
bool	foldFrameOffset (MachineInstr &MI) const
bool	combineRLWINM (MachineInstr &MI, MachineInstr **ToErase=nullptr) const
bool	isADDIInstrEligibleForFolding (MachineInstr &ADDIMI, int64_t &Imm) const
bool	isADDInstrEligibleForFolding (MachineInstr &ADDMI) const
bool	isImmInstrEligibleForFolding (MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
bool	isValidToBeChangedReg (MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
void	replaceInstrWithLI (MachineInstr &MI, const LoadImmediateInfo &LII) const
void	replaceInstrOperandWithImm (MachineInstr &MI, unsigned OpNo, int64_t Imm) const
bool	instrHasImmForm (unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
MachineInstr *	getDefMIPostRA (unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
void	materializeImmPostRA (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
bool	isBDNZ (unsigned Opcode) const
	Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
MachineInstr *	findLoopInstr (MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
	Find the hardware loop instruction used to set-up the specified loop.
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo >	analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
	Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
virtual void	setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
	This is an architecture-specific helper function of reassociateOps.

Static Public Member Functions
static bool	isSameClassPhysRegCopy (unsigned Opcode)
static bool	hasPCRelFlag (unsigned TF)
static bool	hasGOTFlag (unsigned TF)
static bool	hasTLSFlag (unsigned TF)
static int	getRecordFormOpcode (unsigned Opcode)

Protected Member Functions
MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
	Commutes the operands in the given instruction.

Detailed Description

Definition at line 280 of file PPCInstrInfo.h.

Constructor & Destructor Documentation

PPCInstrInfo()

PPCInstrInfo::PPCInstrInfo ( const PPCSubtarget & STI )

explicit

Definition at line 96 of file PPCInstrInfo.cpp.

Member Function Documentation

analyzeBranch()

bool PPCInstrInfo::analyzeBranch ( MachineBasicBlock & MBB, MachineBasicBlock *& TBB, MachineBasicBlock *& FBB, SmallVectorImpl< MachineOperand > & Cond, bool AllowModify ) const

override

Definition at line 1265 of file PPCInstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), EnableCTRLoopAnal, llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineOperand::isMBB(), MBB, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and TBB.

analyzeCompare()

bool PPCInstrInfo::analyzeCompare ( const MachineInstr & MI, Register & SrcReg, Register & SrcReg2, int64_t & Mask, int64_t & Value ) const

override

Definition at line 2408 of file PPCInstrInfo.cpp.

References MI, and Opc.

Referenced by optimizeCmpPostRA().

analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > PPCInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const

override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 5814 of file PPCInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), I, isBDNZ(), and llvm::MachineBasicBlock::pred_begin().

areMemAccessesTriviallyDisjoint()

bool PPCInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa, const MachineInstr & MIb ) const

override

Return true if two MIs access different memory addresses and false otherwise.

Definition at line 5870 of file PPCInstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), llvm::LocationSize::getValue(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::LocationSize::hasValue(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::mayLoadOrStore(), and llvm::LocationSize::precise().

canInsertSelect()

bool PPCInstrInfo::canInsertSelect ( const MachineBasicBlock & MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, SelectExpansion & Exp ) const

override

Definition at line 1525 of file PPCInstrInfo.cpp.

References Cond, getReg(), llvm::MachineRegisterInfo::getRegClass(), isPhysical(), and MBB.

ClobbersPredicate()

bool PPCInstrInfo::ClobbersPredicate ( MachineInstr & MI, std::vector< MachineOperand > & Pred, bool SkipDead ) const

override

Definition at line 2373 of file PPCInstrInfo.cpp.

References llvm::MCRegisterClass::contains(), and MI.

combineRLWINM()

bool PPCInstrInfo::combineRLWINM	(	MachineInstr &	MI,
		MachineInstr **	ToErase = nullptr ) const

Definition at line 3917 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::get(), llvm::APInt::getBitsSetWithWrap(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::APInt::getZExtValue(), llvm::MachineInstr::hasImplicitDef(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::isRunOfOnes(), llvm::Register::isVirtual(), llvm::APInt::isZero(), LLVM_DEBUG, MI, llvm::APInt::rotl(), llvm::MachineOperand::setIsKill(), and llvm::MachineRegisterInfo::use_nodbg_empty().

commuteInstructionImpl()

MachineInstr * PPCInstrInfo::commuteInstructionImpl ( MachineInstr & MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2 ) const

overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

For example, we can commute rlwimi instructions, but only if the rotate amt is zero. We also have to munge the immediates a bit.

Definition at line 1136 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::Define, llvm::getDeadRegState(), llvm::getKillRegState(), MI, and llvm::MCOI::TIED_TO.

convertToImmediateForm()

bool PPCInstrInfo::convertToImmediateForm	(	MachineInstr &	MI,
		SmallSet< Register, 4 > &	RegsToUpdate,
		MachineInstr **	KilledDef = nullptr ) const

Definition at line 3854 of file PPCInstrInfo.cpp.

References assert(), DefMI, llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SmallSet< T, N, C >::insert(), instrHasImmForm(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineRegisterInfo::isSSA(), llvm::PPC::isVFRegister(), and MI.

copyPhysReg()

void PPCInstrInfo::copyPhysReg ( MachineBasicBlock & MBB, MachineBasicBlock::iterator I, const DebugLoc & DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false ) const

override

Definition at line 1684 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), llvm::Define, DL, llvm::PPCRegisterInfo::emitAccCopyInfo(), llvm::get(), getCRBitValue(), llvm::getCRFromCRBit(), llvm::getKillRegState(), I, llvm::Implicit, llvm::ImplicitDefine, llvm::Kill, llvm_unreachable, MBB, Opc, and VSXSelfCopyCrash.

CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI, const ScheduleDAG * DAG ) const

override

CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.

Definition at line 111 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, and II.

CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II, const ScheduleDAG * DAG ) const

override

CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.

Definition at line 128 of file PPCInstrInfo.cpp.

References assert(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::MachineFunction::getSubtarget(), II, llvm::ScheduleDAG::MF, and llvm::ScheduleDAG::TII.

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > PPCInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned TF ) const

override

Definition at line 3076 of file PPCInstrInfo.cpp.

expandAMOCSNEPseudo()

bool PPCInstrInfo::expandAMOCSNEPseudo

(

MachineInstr &

MI

)

const

Definition at line 5906 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::Implicit, MBB, MI, and Register.

Referenced by expandPostRAPseudo().

expandPostRAPseudo()

bool PPCInstrInfo::expandPostRAPseudo ( MachineInstr & MI ) const

override

Definition at line 3187 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), DL, expandAMOCSNEPseudo(), expandPostRAPseudo(), expandVSXMemPseudo(), llvm::get(), isAnImmediateOperand(), MBB, MI, llvm::Offset, and llvm::PPC::PRED_NE_MINUS.

Referenced by expandPostRAPseudo().

expandVSXMemPseudo()

bool PPCInstrInfo::expandVSXMemPseudo

(

MachineInstr &

MI

)

const

Definition at line 3121 of file PPCInstrInfo.cpp.

References llvm::get(), llvm_unreachable, and MI.

Referenced by expandPostRAPseudo().

finalizeInsInstrs()

void PPCInstrInfo::finalizeInsInstrs ( MachineInstr & Root, unsigned & Pattern, SmallVectorImpl< MachineInstr * > & InsInstrs ) const

override

Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.

Definition at line 534 of file PPCInstrInfo.cpp.

References assert(), C(), llvm::APFloat::changeSign(), llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), FMAOpIdxInfo, getConstantFromConstantPool(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), getContext(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::DataLayout::getPrefTypeAlign(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getVRegDef(), InfoArrayIdxMULOpIdx, llvm::isa(), llvm::REASSOC_XY_BAC, and llvm::REASSOC_XY_BCA.

findCommutedOpIndices()

bool PPCInstrInfo::findCommutedOpIndices ( const MachineInstr & MI, unsigned & SrcOpIdx1, unsigned & SrcOpIdx2 ) const

override

Definition at line 1220 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::PPC::getAltVSXFMAOpcode(), and MI.

findLoopInstr()

MachineInstr * PPCInstrInfo::findLoopInstr	(	MachineBasicBlock &	PreHeader,
		SmallPtrSet< MachineBasicBlock *, 8 > &	Visited ) const

Find the hardware loop instruction used to set-up the specified loop.

On PPC, we have two instructions used to set-up the hardware loop (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) instructions to indicate the end of a loop.

Definition at line 5834 of file PPCInstrInfo.cpp.

References I, and llvm::MachineBasicBlock::instrs().

Referenced by analyzeLoopForPipelining().

foldFrameOffset()

bool PPCInstrInfo::foldFrameOffset

(

MachineInstr &

MI

)

const

Definition at line 3645 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::End, llvm::MachineInstr::eraseFromParent(), llvm::get(), getDefMIPostRA(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::ImmInstrInfo::ImmOpNo, isADDInstrEligibleForFolding(), isImmInstrEligibleForFolding(), llvm::MachineOperand::isKill(), llvm::MachineRegisterInfo::isSSA(), isValidToBeChangedReg(), LLVM_DEBUG, MI, llvm::ImmInstrInfo::OpNoForForwarding, llvm::MachineOperand::setImm(), and llvm::ImmInstrInfo::ZeroIsSpecialOrig.

foldImmediate()

bool PPCInstrInfo::foldImmediate ( MachineInstr & UseMI, MachineInstr & DefMI, Register Reg, MachineRegisterInfo * MRI ) const

override

Definition at line 2179 of file PPCInstrInfo.cpp.

References Changed, DefMI, onlyFoldImmediate(), llvm::MachineRegisterInfo::use_nodbg_empty(), and UseMI.

genAlternativeCodeSequence()

void PPCInstrInfo::genAlternativeCodeSequence ( MachineInstr & Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > & InsInstrs, SmallVectorImpl< MachineInstr * > & DelInstrs, DenseMap< Register, unsigned > & InstrIdxForVirtReg ) const

override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 774 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, and llvm::REASSOC_XY_BCA.

getCombinerObjective()

CombinerObjective PPCInstrInfo::getCombinerObjective ( unsigned Pattern ) const

override

Definition at line 746 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::getCombinerObjective(), llvm::MustReduceDepth, llvm::MustReduceRegisterPressure, llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, and llvm::REASSOC_XY_BCA.

getConstantFromConstantPool()

const Constant * PPCInstrInfo::getConstantFromConstantPool

(

MachineInstr *

I

)

const

Definition at line 726 of file PPCInstrInfo.cpp.

References assert(), DefMI, llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstants(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getVRegDef(), and I.

Referenced by finalizeInsInstrs().

getDefMIPostRA()

MachineInstr * PPCInstrInfo::getDefMIPostRA	(	unsigned	Reg,
		MachineInstr &	MI,
		bool &	SeenIntermediateUse ) const

Definition at line 3456 of file PPCInstrInfo.cpp.

References assert(), and MI.

Referenced by foldFrameOffset(), isValidToBeChangedReg(), and optimizeCmpPostRA().

getExtendResourceLenLimit()

int llvm::PPCInstrInfo::getExtendResourceLenLimit ( ) const

inlineoverride

On PowerPC, we try to reassociate FMA chain which will increase instruction size.

Set extension resource length limit to 1 for edge case. Resource Length is calculated by scaled resource usage in getCycles(). Because of the division in getCycles(), it returns different cycles due to legacy scaled resource usage. So new resource length may be same with legacy or 1 bigger than legacy. We need to execlude the 1 bigger case even the resource length is not perserved for more FMA chain reassociations on PowerPC.

Definition at line 524 of file PPCInstrInfo.h.

getFMAPatterns()

bool PPCInstrInfo::getFMAPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns,
		bool	DoRegPressureReduce ) const

Return true when there is potentially a faster code sequence for a fma chain ending in Root.

All potential patterns are output in the P array.

Definition at line 361 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), FMAOpIdxInfo, llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), InfoArrayIdxAddOpIdx, InfoArrayIdxFAddInst, InfoArrayIdxFSubInst, InfoArrayIdxMULOpIdx, isLoadFromConstantPool(), llvm::Register::isVirtual(), LLVM_DEBUG, MBB, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, and llvm::REASSOC_XY_BCA.

Referenced by getMachineCombinerPatterns().

getInlineAsmMemoryOperandRegClass()

const TargetRegisterClass * PPCInstrInfo::getInlineAsmMemoryOperandRegClass ( InlineAsm::ConstraintCode C ) const

override

Definition at line 102 of file PPCInstrInfo.cpp.

References C().

getInstrLatency()

unsigned PPCInstrInfo::getInstrLatency ( const InstrItineraryData * ItinData, const MachineInstr & MI, unsigned * PredCost = nullptr ) const

override

Definition at line 148 of file PPCInstrInfo.cpp.

References llvm::InstrItineraryData::getOperandCycle(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::Latency, MI, and UseOldLatencyCalc.

Referenced by getOperandLatency().

getInstSizeInBytes()

unsigned PPCInstrInfo::getInstSizeInBytes ( const MachineInstr & MI ) const

override

GetInstSize - Return the number of bytes of code the specified instruction may be.

This returns the maximum number of bytes.

Definition at line 3026 of file PPCInstrInfo.cpp.

References F, llvm::get(), llvm::MachineFunction::getFunction(), llvm::TargetMachine::getMCAsmInfo(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::StackMapOpers::getNumPatchBytes(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::getTargetTriple(), llvm::Triple::isLittleEndian(), llvm::Triple::isOSAIX(), and MI.

getInstSizeVerifyMode()

TargetInstrInfo::InstSizeVerifyMode PPCInstrInfo::getInstSizeVerifyMode ( const MachineInstr & MI ) const

override

Definition at line 3068 of file PPCInstrInfo.cpp.

References MI.

getLoadOpcodeForSpill()

unsigned PPCInstrInfo::getLoadOpcodeForSpill

(

const TargetRegisterClass *

RC

)

const

Definition at line 1994 of file PPCInstrInfo.cpp.

getMachineCombinerPatterns()

bool PPCInstrInfo::getMachineCombinerPatterns ( MachineInstr & Root, SmallVectorImpl< unsigned > & Patterns, bool DoRegPressureReduce ) const

override

Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.

All potential patterns are output in the <Pattern> array.

Definition at line 759 of file PPCInstrInfo.cpp.

References llvm::Aggressive, getFMAPatterns(), and llvm::TargetInstrInfo::getMachineCombinerPatterns().

getMemOperandsWithOffsetWidth()

bool PPCInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr & LdSt, SmallVectorImpl< const MachineOperand * > & BaseOps, int64_t & Offset, bool & OffsetIsScalable, LocationSize & Width ) const

override

Get the base operand and byte offset of an instruction that reads/writes memory.

Definition at line 2916 of file PPCInstrInfo.cpp.

References getMemOperandWithOffsetWidth(), llvm::Offset, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

getMemOperandWithOffsetWidth()

bool PPCInstrInfo::getMemOperandWithOffsetWidth	(	const MachineInstr &	LdSt,
		const MachineOperand *&	BaseOp,
		int64_t &	Offset,
		LocationSize &	Width ) const

Return true if get the base operand, byte offset of an instruction and the memory width.

Width is the size of memory that is being loaded/stored (e.g. 1, 2, 4, 8).

Definition at line 5849 of file PPCInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::memoperands_begin(), and llvm::Offset.

Referenced by areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), and shouldClusterMemOps().

getNop()

MCInst PPCInstrInfo::getNop ( ) const

override

Return the noop instruction to use for a noop.

Definition at line 1256 of file PPCInstrInfo.cpp.

References llvm::MCInst::setOpcode().

getOperandLatency() [1/2]

std::optional< unsigned > PPCInstrInfo::getOperandLatency ( const InstrItineraryData * ItinData, const MachineInstr & DefMI, unsigned DefIdx, const MachineInstr & UseMI, unsigned UseIdx ) const

override

Definition at line 178 of file PPCInstrInfo.cpp.

References DefMI, llvm::PPC::DIR_7400, llvm::PPC::DIR_750, llvm::PPC::DIR_970, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR4, llvm::PPC::DIR_PWR5, llvm::PPC::DIR_PWR5X, llvm::PPC::DIR_PWR6, llvm::PPC::DIR_PWR6X, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, getInstrLatency(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MCRegisterClass::hasSuperClassEq(), llvm::Latency, and UseMI.

getOperandLatency() [2/2]

std::optional< unsigned > llvm::PPCInstrInfo::getOperandLatency ( const InstrItineraryData * ItinData, SDNode * DefNode, unsigned DefIdx, SDNode * UseNode, unsigned UseIdx ) const

inlineoverride

Definition at line 455 of file PPCInstrInfo.h.

getRecordFormOpcode()

int PPCInstrInfo::getRecordFormOpcode ( unsigned Opcode )

static

Definition at line 5243 of file PPCInstrInfo.cpp.

getRegisterInfo()

const PPCRegisterInfo & llvm::PPCInstrInfo::getRegisterInfo ( ) const

inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 381 of file PPCInstrInfo.h.

Referenced by foldFrameOffset(), and llvm::PPCSubtarget::getRegisterInfo().

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 3082 of file PPCInstrInfo.cpp.

References llvm::ArrayRef().

getStoreOpcodeForSpill()

unsigned PPCInstrInfo::getStoreOpcodeForSpill

(

const TargetRegisterClass *

RC

)

const

Definition at line 1988 of file PPCInstrInfo.cpp.

hasGOTFlag()

bool llvm::PPCInstrInfo::hasGOTFlag ( unsigned TF )

inlinestatic

Definition at line 421 of file PPCInstrInfo.h.

References llvm::PPCII::MO_GOT_FLAG, llvm::PPCII::MO_GOT_PCREL_FLAG, llvm::PPCII::MO_GOT_TLSGD_PCREL_FLAG, llvm::PPCII::MO_GOT_TLSLD_PCREL_FLAG, and llvm::PPCII::MO_GOT_TPREL_PCREL_FLAG.

hasLowDefLatency()

bool llvm::PPCInstrInfo::hasLowDefLatency ( const TargetSchedModel & SchedModel, const MachineInstr & DefMI, unsigned DefIdx ) const

inlineoverride

Definition at line 463 of file PPCInstrInfo.h.

References DefMI.

hasPCRelFlag()

bool llvm::PPCInstrInfo::hasPCRelFlag ( unsigned TF )

inlinestatic

Definition at line 413 of file PPCInstrInfo.h.

References llvm::PPCII::MO_GOT_PCREL_FLAG, llvm::PPCII::MO_GOT_TLSGD_PCREL_FLAG, llvm::PPCII::MO_GOT_TLSLD_PCREL_FLAG, llvm::PPCII::MO_GOT_TPREL_PCREL_FLAG, llvm::PPCII::MO_PCREL_FLAG, llvm::PPCII::MO_TLS_PCREL_FLAG, and llvm::PPCII::MO_TPREL_PCREL_FLAG.

Referenced by isValidPCRelNode().

hasTLSFlag()

bool llvm::PPCInstrInfo::hasTLSFlag ( unsigned TF )

inlinestatic

Definition at line 428 of file PPCInstrInfo.h.

References llvm::PPCII::MO_DTPREL_LO, llvm::PPCII::MO_GOT_TLSGD_PCREL_FLAG, llvm::PPCII::MO_GOT_TLSLD_PCREL_FLAG, llvm::PPCII::MO_GOT_TPREL_PCREL_FLAG, llvm::PPCII::MO_TLS, llvm::PPCII::MO_TLS_PCREL_FLAG, llvm::PPCII::MO_TLSGD_FLAG, llvm::PPCII::MO_TLSGDM_FLAG, llvm::PPCII::MO_TLSLD_FLAG, llvm::PPCII::MO_TLSLD_LO, llvm::PPCII::MO_TPREL_FLAG, llvm::PPCII::MO_TPREL_HA, llvm::PPCII::MO_TPREL_LO, and llvm::PPCII::MO_TPREL_PCREL_FLAG.

Referenced by getTOCEntryTypeForMO().

insertBranch()

unsigned PPCInstrInfo::insertBranch ( MachineBasicBlock & MBB, MachineBasicBlock * TBB, MachineBasicBlock * FBB, ArrayRef< MachineOperand > Cond, const DebugLoc & DL, int * BytesAdded = nullptr ) const

override

Definition at line 1472 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::getImm(), getReg(), MBB, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and TBB.

insertNoop()

void PPCInstrInfo::insertNoop ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MI ) const

override

Definition at line 1236 of file PPCInstrInfo.cpp.

References llvm::BuildMI(), llvm::PPC::DIR_PWR6, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::PPC::DIR_PWR9, DL, llvm::get(), MBB, and MI.

insertSelect()

void PPCInstrInfo::insertSelect ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, const DebugLoc & DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg ) const

override

Definition at line 1571 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, llvm::MCRegisterClass::contains(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::get(), getReg(), llvm::MachineRegisterInfo::getRegClass(), MBB, MI, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, llvm::PPC::PRED_EQ, llvm::PPC::PRED_EQ_MINUS, llvm::PPC::PRED_EQ_PLUS, llvm::PPC::PRED_GE, llvm::PPC::PRED_GE_MINUS, llvm::PPC::PRED_GE_PLUS, llvm::PPC::PRED_GT, llvm::PPC::PRED_GT_MINUS, llvm::PPC::PRED_GT_PLUS, llvm::PPC::PRED_LE, llvm::PPC::PRED_LE_MINUS, llvm::PPC::PRED_LE_PLUS, llvm::PPC::PRED_LT, llvm::PPC::PRED_LT_MINUS, llvm::PPC::PRED_LT_PLUS, llvm::PPC::PRED_NE, llvm::PPC::PRED_NE_MINUS, llvm::PPC::PRED_NE_PLUS, llvm::PPC::PRED_NU, llvm::PPC::PRED_NU_MINUS, llvm::PPC::PRED_NU_PLUS, llvm::PPC::PRED_UN, llvm::PPC::PRED_UN_MINUS, and llvm::PPC::PRED_UN_PLUS.

instrHasImmForm()

bool PPCInstrInfo::instrHasImmForm	(	unsigned	Opc,
		bool	IsVFReg,
		ImmInstrInfo &	III,
		bool	PostRA ) const

Definition at line 4056 of file PPCInstrInfo.cpp.

References llvm::ImmInstrInfo::ImmMustBeMultipleOf, llvm::ImmInstrInfo::ImmOpcode, llvm::ImmInstrInfo::ImmOpNo, llvm::ImmInstrInfo::ImmWidth, llvm::ImmInstrInfo::IsCommutative, llvm::ImmInstrInfo::IsSummingOperands, llvm_unreachable, Opc, llvm::ImmInstrInfo::OpNoForForwarding, llvm::ImmInstrInfo::SignedImm, llvm::ImmInstrInfo::TruncateImmTo, llvm::ImmInstrInfo::ZeroIsSpecialNew, and llvm::ImmInstrInfo::ZeroIsSpecialOrig.

Referenced by convertToImmediateForm(), and isImmInstrEligibleForFolding().

isADDIInstrEligibleForFolding()

bool PPCInstrInfo::isADDIInstrEligibleForFolding	(	MachineInstr &	ADDIMI,
		int64_t &	Imm ) const

Definition at line 3742 of file PPCInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), Imm, llvm::MachineOperand::isImm(), and Opc.

Referenced by isValidToBeChangedReg().

isADDInstrEligibleForFolding()

bool PPCInstrInfo::isADDInstrEligibleForFolding

(

MachineInstr &

ADDMI

)

const

Definition at line 3759 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and Opc.

Referenced by foldFrameOffset().

isAssociativeAndCommutative()

bool PPCInstrInfo::isAssociativeAndCommutative ( const MachineInstr & Inst, bool Invert ) const

override

Definition at line 243 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getFlag(), and llvm::MachineInstr::getOpcode().

isBDNZ()

bool PPCInstrInfo::isBDNZ

(

unsigned

Opcode

)

const

Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).

Definition at line 5736 of file PPCInstrInfo.cpp.

Referenced by analyzeLoopForPipelining().

isCoalescableExtInstr()

bool PPCInstrInfo::isCoalescableExtInstr ( const MachineInstr & MI, Register & SrcReg, Register & DstReg, unsigned & SubIdx ) const

override

Definition at line 1053 of file PPCInstrInfo.cpp.

References MI.

isImmInstrEligibleForFolding()

bool PPCInstrInfo::isImmInstrEligibleForFolding	(	MachineInstr &	MI,
		unsigned &	BaseReg,
		unsigned &	XFormOpcode,
		int64_t &	OffsetOfImmInstr,
		ImmInstrInfo &	III ) const

Definition at line 3766 of file PPCInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::ImmInstrInfo::ImmOpNo, instrHasImmForm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::ImmInstrInfo::IsSummingOperands, llvm::PPC::isVFRegister(), MI, Opc, and llvm::ImmInstrInfo::OpNoForForwarding.

Referenced by foldFrameOffset().

isLoadFromConstantPool()

bool PPCInstrInfo::isLoadFromConstantPool

(

MachineInstr *

I

)

const

Definition at line 662 of file PPCInstrInfo.cpp.

References llvm::PseudoSourceValue::ConstantPool, and I.

Referenced by getFMAPatterns().

isLoadFromStackSlot()

Register PPCInstrInfo::isLoadFromStackSlot ( const MachineInstr & MI, int & FrameIndex ) const

override

Definition at line 1068 of file PPCInstrInfo.cpp.

References llvm::is_contained(), and MI.

isMemriOp()

bool llvm::PPCInstrInfo::isMemriOp ( unsigned Opcode ) const

inline

Definition at line 398 of file PPCInstrInfo.h.

References llvm::get(), and llvm::PPCII::MemriOp.

isPredicated()

bool PPCInstrInfo::isPredicated ( const MachineInstr & MI ) const

override

Definition at line 2210 of file PPCInstrInfo.cpp.

References MI.

isPrefixed()

bool llvm::PPCInstrInfo::isPrefixed ( unsigned Opcode ) const

inline

Definition at line 389 of file PPCInstrInfo.h.

References llvm::get(), and llvm::PPCII::Prefixed.

isProfitableToDupForIfCvt()

bool llvm::PPCInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock & MBB, unsigned NumCycles, BranchProbability Probability ) const

inlineoverride

Definition at line 630 of file PPCInstrInfo.h.

References MBB.

isProfitableToIfCvt() [1/2]

bool llvm::PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock & MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability ) const

inlineoverride

Definition at line 618 of file PPCInstrInfo.h.

References MBB.

isProfitableToIfCvt() [2/2]

bool PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock & TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock & FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability ) const

override

Definition at line 2201 of file PPCInstrInfo.cpp.

References MBBDefinesCTR().

isProfitableToUnpredicate()

bool llvm::PPCInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock & TMBB, MachineBasicBlock & FMBB ) const

inlineoverride

Definition at line 635 of file PPCInstrInfo.h.

isReMaterializableImpl()

bool PPCInstrInfo::isReMaterializableImpl ( const MachineInstr & MI ) const

override

Definition at line 1084 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::isReMaterializableImpl(), and MI.

isSameClassPhysRegCopy()

bool llvm::PPCInstrInfo::isSameClassPhysRegCopy ( unsigned Opcode )

inlinestatic

Definition at line 402 of file PPCInstrInfo.h.

isSchedulingBoundary()

bool PPCInstrInfo::isSchedulingBoundary ( const MachineInstr & MI, const MachineBasicBlock * MBB, const MachineFunction & MF ) const

override

Definition at line 2221 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::isSchedulingBoundary(), MBB, and MI.

isSExt32To64()

bool llvm::PPCInstrInfo::isSExt32To64 ( unsigned Opcode ) const

inline

Definition at line 392 of file PPCInstrInfo.h.

References llvm::get(), and llvm::PPCII::SExt32To64.

Referenced by promoteInstr32To64ForElimEXTSW().

isSignExtended()

bool llvm::PPCInstrInfo::isSignExtended ( const unsigned Reg, const MachineRegisterInfo * MRI ) const

inline

Definition at line 731 of file PPCInstrInfo.h.

References isSignOrZeroExtended(), and Reg.

Referenced by optimizeCompareInstr().

isSignOrZeroExtended()

std::pair< bool, bool > PPCInstrInfo::isSignOrZeroExtended	(	const unsigned	Reg,
		const unsigned	BinOpDepth,
		const MachineRegisterInfo *	MRI ) const

Definition at line 5568 of file PPCInstrInfo.cpp.

References definedBySignExtendingOp(), definedByZeroExtendingOp(), llvm::dyn_cast(), llvm::dyn_cast_if_present(), llvm::Function::getAttributes(), llvm::Function::getEntryBlock(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getGlobal(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOperand(), llvm::MachineFunction::getRegInfo(), llvm::Function::getReturnType(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getVRegDef(), I, II, Imm, llvm::MachineInstr::isCall(), llvm::MachineOperand::isGlobal(), llvm::MachineRegisterInfo::isLiveIn(), llvm::PPCFunctionInfo::isLiveInSExt(), llvm::PPCFunctionInfo::isLiveInZExt(), isSignOrZeroExtended(), llvm::PPCSubtarget::isSVR4ABI(), llvm::Register::isVirtualRegister(), MAX_BINOP_DEPTH, MBB, and MI.

Referenced by isSignExtended(), isSignOrZeroExtended(), and isZeroExtended().

isStoreToStackSlot()

Register PPCInstrInfo::isStoreToStackSlot ( const MachineInstr & MI, int & FrameIndex ) const

override

Definition at line 1124 of file PPCInstrInfo.cpp.

References llvm::is_contained(), and MI.

isTOCSaveMI()

bool PPCInstrInfo::isTOCSaveMI

(

const MachineInstr &

MI

)

const

Definition at line 5354 of file PPCInstrInfo.cpp.

References MI, and SPReg.

isValidToBeChangedReg()

bool PPCInstrInfo::isValidToBeChangedReg	(	MachineInstr *	ADDMI,
		unsigned	Index,
		MachineInstr *&	ADDIMI,
		int64_t &	OffsetAddi,
		int64_t	OffsetImm ) const

Definition at line 3809 of file PPCInstrInfo.cpp.

References assert(), getDefMIPostRA(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), isADDIInstrEligibleForFolding(), llvm::isInt(), and llvm::MachineOperand::isKill().

Referenced by foldFrameOffset().

isXFormMemOp()

bool llvm::PPCInstrInfo::isXFormMemOp ( unsigned Opcode ) const

inline

Definition at line 386 of file PPCInstrInfo.h.

References llvm::get(), and llvm::PPCII::XFormMemOp.

isZeroExtended()

bool llvm::PPCInstrInfo::isZeroExtended ( const unsigned Reg, const MachineRegisterInfo * MRI ) const

inline

Definition at line 737 of file PPCInstrInfo.h.

References isSignOrZeroExtended(), and Reg.

Referenced by optimizeCompareInstr().

isZExt32To64()

bool llvm::PPCInstrInfo::isZExt32To64 ( unsigned Opcode ) const

inline

Definition at line 395 of file PPCInstrInfo.h.

References llvm::get(), and llvm::PPCII::ZExt32To64.

loadRegFromStackSlot()

void PPCInstrInfo::loadRegFromStackSlot ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass * RC, Register VReg, unsigned SubReg = 0, MachineInstr::MIFlag Flags = MachineInstr::NoFlags ) const

override

Definition at line 2086 of file PPCInstrInfo.cpp.

References loadRegFromStackSlotNoUpd(), MBB, MI, and updatedRC().

loadRegFromStackSlotNoUpd()

void PPCInstrInfo::loadRegFromStackSlotNoUpd	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC ) const

Definition at line 2065 of file PPCInstrInfo.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::back(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), MBB, MI, and llvm::MachineMemOperand::MOLoad.

Referenced by loadRegFromStackSlot().

materializeImmPostRA()

void PPCInstrInfo::materializeImmPostRA	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		Register	Reg,
		int64_t	Imm ) const

Definition at line 3472 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::get(), Imm, llvm::isInt(), llvm::Kill, MBB, and MBBI.

onlyFoldImmediate()

bool PPCInstrInfo::onlyFoldImmediate	(	MachineInstr &	UseMI,
		MachineInstr &	DefMI,
		Register	Reg ) const

Definition at line 2118 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), DefMI, llvm::MCInstrDesc::getNumOperands(), llvm::MCInstrDesc::isPseudo(), LLVM_DEBUG, llvm::MCInstrDesc::operands(), and UseMI.

Referenced by foldImmediate().

optimizeCmpPostRA()

bool PPCInstrInfo::optimizeCmpPostRA

(

MachineInstr &

MI

)

const

Definition at line 2841 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), analyzeCompare(), assert(), llvm::MachineInstr::clearRegisterDeads(), llvm::dbgs(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::dump(), llvm::get(), getDefMIPostRA(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::hasImplicitDef(), llvm::ImplicitDefine, llvm::MachineRegisterInfo::isSSA(), LLVM_DEBUG, Opc, and llvm::MachineInstr::setDesc().

optimizeCompareInstr()

bool PPCInstrInfo::optimizeCompareInstr ( MachineInstr & CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo * MRI ) const

override

Definition at line 2438 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), B(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), EnableCmpOpt, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::getKillRegState(), llvm::PPC::getNonRecordFormOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::PPC::getPredicate(), llvm::PPC::getPredicateCondition(), llvm::PPC::getPredicateHint(), llvm::MachineOperand::getReg(), llvm::PPC::getSwappedPredicate(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneUse(), I, llvm::MCInstrDesc::implicit_defs(), llvm::MCInstrDesc::implicit_uses(), isSignExtended(), llvm::Register::isVirtual(), isZeroExtended(), llvm::MachineBasicBlock::LQR_Dead, MBB, MI, llvm::MachineInstr::NoSWrap, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineOperand::setImm(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Sub, llvm::MachineRegisterInfo::use_empty(), llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), and UseMI.

PredicateInstruction()

bool PPCInstrInfo::PredicateInstruction ( MachineInstr & MI, ArrayRef< MachineOperand > Pred ) const

override

Definition at line 2238 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::get(), llvm::getImm(), getReg(), llvm::Implicit, llvm::ImplicitDefine, llvm_unreachable, MBB, MI, llvm::PPC::PRED_BIT_SET, and llvm::PPC::PRED_BIT_UNSET.

promoteInstr32To64ForElimEXTSW()

void PPCInstrInfo::promoteInstr32To64ForElimEXTSW	(	const Register &	Reg,
		MachineRegisterInfo *	MRI,
		unsigned	BinOpDepth ) const

Definition at line 5380 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::DenseMapBase< StorageT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< StorageT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::get(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MCRegisterClass::hasSubClassEq(), I, llvm::MachineOperand::isReg(), isSExt32To64(), llvm::PPCSubtarget::isSVR4ABI(), llvm::Register::isVirtual(), llvm::Kill, MAX_BINOP_DEPTH, MBB, MI, promoteInstr32To64ForElimEXTSW(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), and llvm::MachineOperand::setSubReg().

Referenced by promoteInstr32To64ForElimEXTSW().

removeBranch()

unsigned PPCInstrInfo::removeBranch ( MachineBasicBlock & MBB, int * BytesRemoved = nullptr ) const

override

Definition at line 1440 of file PPCInstrInfo.cpp.

References assert(), I, and MBB.

replaceInstrOperandWithImm()

void PPCInstrInfo::replaceInstrOperandWithImm	(	MachineInstr &	MI,
		unsigned	OpNo,
		int64_t	Imm ) const

Definition at line 3403 of file PPCInstrInfo.cpp.

References assert(), Imm, llvm::MachineOperand::isImplicit(), and MI.

replaceInstrWithLI()

void PPCInstrInfo::replaceInstrWithLI	(	MachineInstr &	MI,
		const LoadImmediateInfo &	LII ) const

Definition at line 3433 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::get(), llvm::LoadImmediateInfo::Imm, llvm::ImplicitDefine, llvm::LoadImmediateInfo::Is64Bit, MI, and llvm::LoadImmediateInfo::SetCR.

reverseBranchCondition()

bool PPCInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const

override

Definition at line 2104 of file PPCInstrInfo.cpp.

References assert(), Cond, llvm::getImm(), getReg(), and llvm::PPC::InvertPredicate().

setSpecialOperandAttr() [1/2]

void PPCInstrInfo::setSpecialOperandAttr	(	MachineInstr &	MI,
		uint32_t	Flags ) const

Definition at line 230 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::IsExact, MI, llvm::MachineInstr::NoSWrap, and llvm::MachineInstr::NoUWrap.

setSpecialOperandAttr() [2/2]

virtual void llvm::TargetInstrInfo::setSpecialOperandAttr ( MachineInstr & OldMI1, MachineInstr & OldMI2, MachineInstr & NewMI1, MachineInstr & NewMI2 ) const

inline

This is an architecture-specific helper function of reassociateOps.

Set special operand attributes for new instructions after reassociation.

Definition at line 1465 of file TargetInstrInfo.h.

shouldClusterMemOps()

bool PPCInstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes ) const

override

Returns true if the two given memory operations should be scheduled adjacent.

Definition at line 2966 of file PPCInstrInfo.cpp.

References assert(), llvm::ArrayRef< T >::front(), llvm::MachineOperand::getIndex(), getMemOperandWithOffsetWidth(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::LocationSize::getValue(), isClusterableLdStOpcPair(), llvm::MachineOperand::isFI(), isLdStSafeToCluster(), llvm::MachineOperand::isReg(), llvm::LocationSize::precise(), and llvm::ArrayRef< T >::size().

shouldReduceRegisterPressure()

bool PPCInstrInfo::shouldReduceRegisterPressure ( const MachineBasicBlock * MBB, const RegisterClassInfo * RegClassInfo ) const

override

On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB.

Return true if register pressure for MBB is high and ABI is supported to reduce register pressure. Otherwise return false.

Definition at line 603 of file PPCInstrInfo.cpp.

References assert(), llvm::RegPressureTracker::closeRegion(), llvm::RegisterOperands::collect(), EnableFMARegPressureReduction, FMARPFactor, llvm::RegPressureTracker::getPos(), llvm::RegPressureTracker::getPressure(), llvm::MachineFunction::getRegInfo(), llvm::RegisterClassInfo::getRegPressureSetLimit(), llvm::RegPressureTracker::init(), llvm::RegisterPressure::MaxSetPressure, MBB, llvm::CodeModel::Medium, MI, llvm::RegPressureTracker::recede(), llvm::RegPressureTracker::recedeSkipDebugValues(), and llvm::reverse().

storeRegToStackSlot()

void PPCInstrInfo::storeRegToStackSlot ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass * RC, Register VReg, MachineInstr::MIFlag Flags = MachineInstr::NoFlags ) const

override

Definition at line 2040 of file PPCInstrInfo.cpp.

References MBB, MI, storeRegToStackSlotNoUpd(), and updatedRC().

storeRegToStackSlotNoUpd()

void PPCInstrInfo::storeRegToStackSlotNoUpd	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC ) const

Definition at line 2021 of file PPCInstrInfo.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), MBB, MI, and llvm::MachineMemOperand::MOStore.

Referenced by storeRegToStackSlot().

SubsumesPredicate()

bool PPCInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2 ) const

override

Definition at line 2342 of file PPCInstrInfo.cpp.

References assert(), llvm::getImm(), getReg(), llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, and llvm::ArrayRef< T >::size().

updatedRC()

const TargetRegisterClass * PPCInstrInfo::updatedRC

(

const TargetRegisterClass *

RC

)

const

Definition at line 5237 of file PPCInstrInfo.cpp.

Referenced by loadRegFromStackSlot(), and storeRegToStackSlot().

useMachineCombiner()

bool llvm::PPCInstrInfo::useMachineCombiner ( ) const

inlineoverride

Definition at line 472 of file PPCInstrInfo.h.

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The documentation for this class was generated from the following files:

• lib/Target/PowerPC/PPCInstrInfo.h
• lib/Target/PowerPC/PPCInstrInfo.cpp