14#ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15#define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
20#define GET_REGINFO_HEADER
21#include "PPCGenRegisterInfo.inc"
24class PPCTargetMachine;
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
40 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
43 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
46 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
49 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
53 assert(
Reg != 0 &&
"Invalid CR bit register");
68 if (!ImmToIdxMap.
count(ImmOpcode))
69 return PPC::INSTRUCTION_LIST_END;
70 return ImmToIdxMap.
find(ImmOpcode)->second;
121 Register &NegSizeReg,
bool &KillNegSizeReg,
125 unsigned FrameIndex)
const;
127 unsigned FrameIndex)
const;
129 unsigned FrameIndex)
const;
131 unsigned FrameIndex)
const;
134 unsigned FrameIndex)
const;
136 unsigned FrameIndex)
const;
138 unsigned FrameIndex)
const;
141 unsigned FrameIndex)
const;
143 unsigned FrameIndex)
const;
146 unsigned FrameIndex)
const;
148 unsigned FrameIndex)
const;
154 int &FrameIdx)
const override;
156 unsigned FIOperandNum,
162 int64_t
Offset)
const override;
164 int64_t
Offset)
const override;
166 int64_t
Offset)
const override;
176 return Reg == PPC::LR ||
Reg == PPC::LR8;
This file defines the DenseMap class.
uint64_t IntrinsicInst * II
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
iterator find(const_arg_type_t< KeyT > Val)
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Wrapper class representing physical registers. Should be passed by value.
Representation of each machine instruction.
bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Register getFrameRegister(const MachineFunction &MF) const override
bool hasBasePointer(const MachineFunction &MF) const
Register getBaseRegister(const MachineFunction &MF) const
void prepareDynamicAlloca(MachineBasicBlock::iterator II, Register &NegSizeReg, bool &KillNegSizeReg, Register &FramePointer) const
To accomplish dynamic stack allocation, we have to calculate exact size subtracted from the stack poi...
unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const
getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode for a given imm form load/s...
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerACCSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCSpilling - Generate the code for spilling the accumulator register.
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
We require the register scavenger.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
const uint32_t * getNoPreservedMask() const override
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
void lowerQuadwordRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordRestore - Generate code to restore paired general register.
static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg, MCRegister SrcReg)
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
void lowerWACCRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerWACCRestore - Generate the code to restore the wide accumulator register.
void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const
void lowerQuadwordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerQuadwordSpilling - Generate code to spill paired general register.
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void lowerWACCSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerWACCSpilling - Generate the code for spilling the wide accumulator register.
void lowerOctWordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Remove any STXVP[X] instructions and split them out into a pair of STXV[X] instructions if –disable-a...
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
void lowerACCRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerACCRestore - Generate the code to restore the accumulator register.
Common code between 32-bit and 64-bit PowerPC targets.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is an optimization pass for GlobalISel generic memory operations.
static unsigned getCRFromCRBit(unsigned SrcReg)