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LLVM 20.0.0git
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This is the complete list of members for llvm::X86GenRegisterBankInfo, including all inherited members.
| applyDefaultMapping(const OperandsMapper &OpdMapper) | llvm::RegisterBankInfo | static |
| applyMapping(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const | llvm::RegisterBankInfo | inline |
| applyMappingImpl(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const | llvm::RegisterBankInfo | inlinevirtual |
| cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const | llvm::RegisterBankInfo | inline |
| constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) | llvm::RegisterBankInfo | static |
| copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const | llvm::RegisterBankInfo | inlinevirtual |
| DefaultMappingID | llvm::RegisterBankInfo | static |
| getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const | llvm::RegisterBankInfo | inlinevirtual |
| getInstrAlternativeMappings(const MachineInstr &MI) const | llvm::RegisterBankInfo | virtual |
| getInstrMapping(const MachineInstr &MI) const | llvm::RegisterBankInfo | virtual |
| getInstrMappingImpl(const MachineInstr &MI) const | llvm::RegisterBankInfo | protected |
| getInstrPossibleMappings(const MachineInstr &MI) const | llvm::RegisterBankInfo | |
| getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const | llvm::RegisterBankInfo | inline |
| getInvalidInstructionMapping() const | llvm::RegisterBankInfo | inline |
| getMaximumSize(unsigned RegBankID) const | llvm::RegisterBankInfo | inline |
| getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | protected |
| getNumRegBanks() const | llvm::RegisterBankInfo | inline |
| getOperandsMapping(Iterator Begin, Iterator End) const | llvm::RegisterBankInfo | protected |
| getOperandsMapping(const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const | llvm::RegisterBankInfo | protected |
| getOperandsMapping(std::initializer_list< const ValueMapping * > OpdsMapping) const | llvm::RegisterBankInfo | protected |
| getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
| getPartialMappingIdx(const MachineInstr &MI, const LLT &Ty, bool isFP) | llvm::X86GenRegisterBankInfo | protectedstatic |
| getRegBank(unsigned ID) | llvm::RegisterBankInfo | inlineprotected |
| getRegBank(unsigned ID) const | llvm::RegisterBankInfo | inline |
| getRegBank(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const | llvm::RegisterBankInfo | |
| getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const | llvm::RegisterBankInfo | inlinevirtual |
| getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| getValueMapping(PartialMappingIdx Idx, unsigned NumOperands) | llvm::X86GenRegisterBankInfo | protectedstatic |
| llvm::RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
| llvm::RegisterBankInfo::getValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) const | llvm::RegisterBankInfo | protected |
| HwMode | llvm::RegisterBankInfo | protected |
| InstructionMappings typedef | llvm::RegisterBankInfo | |
| InvalidMappingID | llvm::RegisterBankInfo | static |
| isDivergentRegBank(const RegisterBank *RB) const | llvm::RegisterBankInfo | inlinevirtual |
| MapOfInstructionMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfOperandsMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfPartialMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfValueMappings | llvm::RegisterBankInfo | mutableprotected |
| NumRegBanks | llvm::RegisterBankInfo | protected |
| PartMappings | llvm::X86GenRegisterBankInfo | protectedstatic |
| PhysRegMinimalRCs | llvm::RegisterBankInfo | mutableprotected |
| RegBanks | llvm::RegisterBankInfo | protected |
| RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode) | llvm::RegisterBankInfo | protected |
| RegisterBankInfo() | llvm::RegisterBankInfo | inlineprotected |
| Sizes | llvm::RegisterBankInfo | protected |
| ValMappings | llvm::X86GenRegisterBankInfo | protectedstatic |
| verify(const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| ~RegisterBankInfo()=default | llvm::RegisterBankInfo | virtual |
1.9.6