20#include "llvm/IR/IntrinsicsAMDGPU.h"
21#include "llvm/IR/IntrinsicsR600.h"
31#define GET_INSTRINFO_NAMED_OPS
32#define GET_INSTRMAP_INFO
33#include "AMDGPUGenInstrInfo.inc"
38 llvm::cl::desc(
"Set default AMDHSA Code Object Version (module flag "
39 "or asm directive still take priority if present)"));
44unsigned getBitMask(
unsigned Shift,
unsigned Width) {
45 return ((1 << Width) - 1) << Shift;
51unsigned packBits(
unsigned Src,
unsigned Dst,
unsigned Shift,
unsigned Width) {
52 unsigned Mask = getBitMask(Shift, Width);
53 return ((Src << Shift) & Mask) | (Dst & ~Mask);
59unsigned unpackBits(
unsigned Src,
unsigned Shift,
unsigned Width) {
60 return (Src & getBitMask(Shift, Width)) >> Shift;
64unsigned getVmcntBitShiftLo(
unsigned VersionMajor) {
69unsigned getVmcntBitWidthLo(
unsigned VersionMajor) {
74unsigned getExpcntBitShift(
unsigned VersionMajor) {
79unsigned getExpcntBitWidth(
unsigned VersionMajor) {
return 3; }
82unsigned getLgkmcntBitShift(
unsigned VersionMajor) {
87unsigned getLgkmcntBitWidth(
unsigned VersionMajor) {
92unsigned getVmcntBitShiftHi(
unsigned VersionMajor) {
return 14; }
95unsigned getVmcntBitWidthHi(
unsigned VersionMajor) {
96 return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0;
100unsigned getLoadcntBitWidth(
unsigned VersionMajor) {
105unsigned getSamplecntBitWidth(
unsigned VersionMajor) {
110unsigned getBvhcntBitWidth(
unsigned VersionMajor) {
115unsigned getDscntBitWidth(
unsigned VersionMajor) {
120unsigned getDscntBitShift(
unsigned VersionMajor) {
return 0; }
123unsigned getStorecntBitWidth(
unsigned VersionMajor) {
128unsigned getKmcntBitWidth(
unsigned VersionMajor) {
133unsigned getLoadcntStorecntBitShift(
unsigned VersionMajor) {
138inline unsigned getVmVsrcBitWidth() {
return 3; }
141inline unsigned getVmVsrcBitShift() {
return 2; }
144inline unsigned getVaVdstBitWidth() {
return 4; }
147inline unsigned getVaVdstBitShift() {
return 12; }
150inline unsigned getSaSdstBitWidth() {
return 1; }
153inline unsigned getSaSdstBitShift() {
return 0; }
167 if (
auto Ver = mdconst::extract_or_null<ConstantInt>(
168 M.getModuleFlag(
"amdhsa_code_object_version"))) {
169 return (
unsigned)Ver->getZExtValue() / 100;
180 switch (ABIVersion) {
196 switch (CodeObjectVersion) {
205 Twine(CodeObjectVersion));
210 switch (CodeObjectVersion) {
224 switch (CodeObjectVersion) {
235 switch (CodeObjectVersion) {
246 switch (CodeObjectVersion) {
256#define GET_MIMGBaseOpcodesTable_IMPL
257#define GET_MIMGDimInfoTable_IMPL
258#define GET_MIMGInfoTable_IMPL
259#define GET_MIMGLZMappingTable_IMPL
260#define GET_MIMGMIPMappingTable_IMPL
261#define GET_MIMGBiasMappingTable_IMPL
262#define GET_MIMGOffsetMappingTable_IMPL
263#define GET_MIMGG16MappingTable_IMPL
264#define GET_MAIInstInfoTable_IMPL
265#include "AMDGPUGenSearchableTables.inc"
268 unsigned VDataDwords,
unsigned VAddrDwords) {
269 const MIMGInfo *
Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
270 VDataDwords, VAddrDwords);
289 bool IsG16Supported) {
296 AddrWords += AddrComponents;
304 if ((IsA16 && !IsG16Supported) || BaseOpcode->
G16)
375#define GET_MTBUFInfoTable_DECL
376#define GET_MTBUFInfoTable_IMPL
377#define GET_MUBUFInfoTable_DECL
378#define GET_MUBUFInfoTable_IMPL
379#define GET_SMInfoTable_DECL
380#define GET_SMInfoTable_IMPL
381#define GET_VOP1InfoTable_DECL
382#define GET_VOP1InfoTable_IMPL
383#define GET_VOP2InfoTable_DECL
384#define GET_VOP2InfoTable_IMPL
385#define GET_VOP3InfoTable_DECL
386#define GET_VOP3InfoTable_IMPL
387#define GET_VOPC64DPPTable_DECL
388#define GET_VOPC64DPPTable_IMPL
389#define GET_VOPC64DPP8Table_DECL
390#define GET_VOPC64DPP8Table_IMPL
391#define GET_VOPCAsmOnlyInfoTable_DECL
392#define GET_VOPCAsmOnlyInfoTable_IMPL
393#define GET_VOP3CAsmOnlyInfoTable_DECL
394#define GET_VOP3CAsmOnlyInfoTable_IMPL
395#define GET_VOPDComponentTable_DECL
396#define GET_VOPDComponentTable_IMPL
397#define GET_VOPDPairs_DECL
398#define GET_VOPDPairs_IMPL
399#define GET_VOPTrue16Table_DECL
400#define GET_VOPTrue16Table_IMPL
401#define GET_WMMAOpcode2AddrMappingTable_DECL
402#define GET_WMMAOpcode2AddrMappingTable_IMPL
403#define GET_WMMAOpcode3AddrMappingTable_DECL
404#define GET_WMMAOpcode3AddrMappingTable_IMPL
405#include "AMDGPUGenSearchableTables.inc"
409 return Info ?
Info->BaseOpcode : -1;
413 const MTBUFInfo *
Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
424 return Info ?
Info->has_vaddr :
false;
429 return Info ?
Info->has_srsrc :
false;
434 return Info ?
Info->has_soffset :
false;
439 return Info ?
Info->BaseOpcode : -1;
443 const MUBUFInfo *
Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
454 return Info ?
Info->has_vaddr :
false;
459 return Info ?
Info->has_srsrc :
false;
464 return Info ?
Info->has_soffset :
false;
469 return Info ?
Info->IsBufferInv :
false;
478 const SMInfo *
Info = getSMEMOpcodeHelper(Opc);
479 return Info ?
Info->IsBuffer :
false;
484 return Info ?
Info->IsSingle :
false;
489 return Info ?
Info->IsSingle :
false;
494 return Info ?
Info->IsSingle :
false;
498 return isVOPC64DPPOpcodeHelper(Opc) || isVOPC64DPP8OpcodeHelper(Opc);
505 return Info ?
Info->is_dgemm :
false;
510 return Info ?
Info->is_gfx940_xdl :
false;
514 if (ST.hasFeature(AMDGPU::FeatureGFX12Insts))
516 if (ST.hasFeature(AMDGPU::FeatureGFX11Insts))
524 return {
Info->CanBeVOPDX,
true};
526 return {
false,
false};
539 return Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
540 Opc == AMDGPU::V_MAC_F32_e64_gfx10 ||
541 Opc == AMDGPU::V_MAC_F32_e64_vi ||
542 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
543 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
544 Opc == AMDGPU::V_MAC_F16_e64_vi ||
545 Opc == AMDGPU::V_FMAC_F64_e64_gfx90a ||
546 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
547 Opc == AMDGPU::V_FMAC_F32_e64_gfx11 ||
548 Opc == AMDGPU::V_FMAC_F32_e64_gfx12 ||
549 Opc == AMDGPU::V_FMAC_F32_e64_vi ||
550 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
551 Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
552 Opc == AMDGPU::V_FMAC_F16_e64_gfx10 ||
553 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx11 ||
554 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx12 ||
555 Opc == AMDGPU::V_DOT2C_F32_F16_e64_vi ||
556 Opc == AMDGPU::V_DOT2C_I32_I16_e64_vi ||
557 Opc == AMDGPU::V_DOT4C_I32_I8_e64_vi ||
558 Opc == AMDGPU::V_DOT8C_I32_I4_e64_vi;
562 return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
563 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
564 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
565 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
566 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
567 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12 ||
568 Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12 ||
569 Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
573 return Opc == AMDGPU::V_CVT_F32_BF8_e64_gfx12 ||
574 Opc == AMDGPU::V_CVT_F32_FP8_e64_gfx12 ||
575 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12 ||
576 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12 ||
577 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12 ||
578 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12 ||
579 Opc == AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 ||
580 Opc == AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12;
584 return Opc == AMDGPU::G_AMDGPU_ATOMIC_FMIN ||
585 Opc == AMDGPU::G_AMDGPU_ATOMIC_FMAX ||
586 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP ||
587 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD ||
588 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB ||
589 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN ||
590 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN ||
591 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX ||
592 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX ||
593 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND ||
594 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR ||
595 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR ||
596 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC ||
597 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC ||
598 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD ||
599 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN ||
600 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX ||
601 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP ||
602 Opc == AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG;
607 return Info ?
Info->IsTrue16 :
false;
612 return Info ?
Info->Opcode3Addr : ~0u;
617 return Info ?
Info->Opcode2Addr : ~0u;
624 return getMCOpcodeGen(Opcode,
static_cast<Subtarget
>(Gen));
627int getVOPDFull(
unsigned OpX,
unsigned OpY,
unsigned EncodingFamily) {
629 getVOPDInfoFromComponentOpcodes(OpX, OpY, EncodingFamily);
636 auto OpX = getVOPDBaseFromComponent(
Info->OpX);
637 auto OpY = getVOPDBaseFromComponent(
Info->OpY);
639 return {OpX->BaseVOP, OpY->BaseVOP};
651 HasSrc2Acc = TiedIdx != -1;
658 for (CompOprIdx =
Component::SRC1; CompOprIdx < OperandsNum; ++CompOprIdx) {
660 MandatoryLiteralIdx = CompOprIdx;
681 std::function<
unsigned(
unsigned,
unsigned)> GetRegIdx,
bool SkipSrc)
const {
686 const unsigned CompOprNum =
689 for (CompOprIdx = 0; CompOprIdx < CompOprNum; ++CompOprIdx) {
691 if (OpXRegs[CompOprIdx] && OpYRegs[CompOprIdx] &&
692 ((OpXRegs[CompOprIdx] & BanksMasks) ==
693 (OpYRegs[CompOprIdx] & BanksMasks)))
709 std::function<
unsigned(
unsigned,
unsigned)> GetRegIdx)
const {
712 const auto &Comp = CompInfo[CompIdx];
715 RegIndices[
DST] = GetRegIdx(CompIdx, Comp.getIndexOfDstInMCOperands());
718 unsigned CompSrcIdx = CompOprIdx -
DST_NUM;
720 Comp.hasRegSrcOperand(CompSrcIdx)
721 ? GetRegIdx(CompIdx, Comp.getIndexOfSrcInMCOperands(CompSrcIdx))
736 const auto &OpXDesc = InstrInfo->
get(OpX);
737 const auto &OpYDesc = InstrInfo->
get(OpY);
759 std::optional<bool> XnackRequested;
760 std::optional<bool> SramEccRequested;
762 for (
const std::string &Feature : Features.
getFeatures()) {
763 if (Feature ==
"+xnack")
764 XnackRequested =
true;
765 else if (Feature ==
"-xnack")
766 XnackRequested =
false;
767 else if (Feature ==
"+sramecc")
768 SramEccRequested =
true;
769 else if (Feature ==
"-sramecc")
770 SramEccRequested =
false;
776 if (XnackRequested) {
777 if (XnackSupported) {
783 if (*XnackRequested) {
784 errs() <<
"warning: xnack 'On' was requested for a processor that does "
787 errs() <<
"warning: xnack 'Off' was requested for a processor that "
788 "does not support it!\n";
793 if (SramEccRequested) {
794 if (SramEccSupported) {
801 if (*SramEccRequested) {
802 errs() <<
"warning: sramecc 'On' was requested for a processor that "
803 "does not support it!\n";
805 errs() <<
"warning: sramecc 'Off' was requested for a processor that "
806 "does not support it!\n";
824 TargetID.
split(TargetIDSplit,
':');
826 for (
const auto &FeatureString : TargetIDSplit) {
827 if (FeatureString.starts_with(
"xnack"))
829 if (FeatureString.starts_with(
"sramecc"))
835 std::string StringRep;
841 StreamRep << TargetTriple.getArchName() <<
'-'
842 << TargetTriple.getVendorName() <<
'-'
843 << TargetTriple.getOSName() <<
'-'
844 << TargetTriple.getEnvironmentName() <<
'-';
846 std::string Processor;
850 if (Version.Major >= 9)
853 Processor = (
Twine(
"gfx") +
Twine(Version.Major) +
Twine(Version.Minor) +
854 Twine(Version.Stepping))
857 std::string Features;
861 Features +=
":sramecc-";
863 Features +=
":sramecc+";
866 Features +=
":xnack-";
868 Features +=
":xnack+";
871 StreamRep << Processor << Features;
887 unsigned BytesPerCU = 0;
922 unsigned FlatWorkGroupSize) {
923 assert(FlatWorkGroupSize != 0);
933 unsigned MaxBarriers = 16;
937 return std::min(MaxWaves /
N, MaxBarriers);
954 unsigned FlatWorkGroupSize) {
969 unsigned FlatWorkGroupSize) {
975 if (Version.Major >= 10)
977 if (Version.Major >= 8)
988 if (Version.Major >= 8)
998 if (Version.Major >= 10)
1000 if (Version.Major >= 8)
1009 if (Version.Major >= 10)
1028 if (Version.Major >= 10)
1029 return Addressable ? AddressableNumSGPRs : 108;
1030 if (Version.Major >= 8 && !Addressable)
1031 AddressableNumSGPRs = 112;
1036 return std::min(MaxNumSGPRs, AddressableNumSGPRs);
1040 bool FlatScrUsed,
bool XNACKUsed) {
1041 unsigned ExtraSGPRs = 0;
1046 if (Version.Major >= 10)
1049 if (Version.Major < 8) {
1072 return divideCeil(std::max(1u, NumRegs), Granule);
1082 std::optional<bool> EnableWavefrontSize32) {
1086 bool IsWave32 = EnableWavefrontSize32 ?
1087 *EnableWavefrontSize32 :
1091 return IsWave32 ? 24 : 12;
1094 return IsWave32 ? 16 : 8;
1096 return IsWave32 ? 8 : 4;
1100 std::optional<bool> EnableWavefrontSize32) {
1104 bool IsWave32 = EnableWavefrontSize32 ?
1105 *EnableWavefrontSize32 :
1108 return IsWave32 ? 8 : 4;
1118 return IsWave32 ? 1536 : 768;
1119 return IsWave32 ? 1024 : 512;
1131 unsigned NumVGPRs) {
1134 if (NumVGPRs < Granule)
1136 unsigned RoundedRegs =
alignTo(NumVGPRs, Granule);
1137 return std::min(std::max(
getTotalNumVGPRs(STI) / RoundedRegs, 1u), MaxWaves);
1144 if (WavesPerEU >= MaxWavesPerEU)
1150 unsigned MaxNumVGPRs =
alignDown(TotNumVGPRs / WavesPerEU, Granule);
1152 if (MaxNumVGPRs ==
alignDown(TotNumVGPRs / MaxWavesPerEU, Granule))
1156 if (WavesPerEU < MinWavesPerEU)
1159 unsigned MaxNumVGPRsNext =
alignDown(TotNumVGPRs / (WavesPerEU + 1), Granule);
1160 unsigned MinNumVGPRs = 1 + std::min(MaxNumVGPRs - Granule, MaxNumVGPRsNext);
1161 return std::min(MinNumVGPRs, AddrsableNumVGPRs);
1170 return std::min(MaxNumVGPRs, AddressableNumVGPRs);
1174 std::optional<bool> EnableWavefrontSize32) {
1182 std::optional<bool> EnableWavefrontSize32) {
1192 memset(&Header, 0,
sizeof(Header));
1194 Header.amd_kernel_code_version_major = 1;
1195 Header.amd_kernel_code_version_minor = 2;
1196 Header.amd_machine_kind = 1;
1197 Header.amd_machine_version_major = Version.Major;
1198 Header.amd_machine_version_minor = Version.Minor;
1199 Header.amd_machine_version_stepping = Version.Stepping;
1200 Header.kernel_code_entry_byte_offset =
sizeof(Header);
1201 Header.wavefront_size = 6;
1205 Header.call_convention = -1;
1209 Header.kernarg_segment_alignment = 4;
1210 Header.group_segment_alignment = 4;
1211 Header.private_segment_alignment = 4;
1213 if (Version.Major >= 10) {
1215 Header.wavefront_size = 5;
1218 Header.compute_pgm_resource_registers |=
1242std::pair<unsigned, unsigned>
1244 std::pair<unsigned, unsigned>
Default,
1245 bool OnlyFirstRequired) {
1247 if (!
A.isStringAttribute())
1251 std::pair<unsigned, unsigned> Ints =
Default;
1252 std::pair<StringRef, StringRef> Strs =
A.getValueAsString().split(
',');
1253 if (Strs.first.trim().getAsInteger(0, Ints.first)) {
1254 Ctx.
emitError(
"can't parse first integer attribute " +
Name);
1257 if (Strs.second.trim().getAsInteger(0, Ints.second)) {
1258 if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
1259 Ctx.
emitError(
"can't parse second integer attribute " +
Name);
1273 if (!
A.isStringAttribute())
1283 std::pair<StringRef, StringRef> Strs = S.
split(
',');
1285 if (Strs.first.trim().getAsInteger(0, IntVal)) {
1286 Ctx.
emitError(
"can't parse integer attribute " + Strs.first +
" in " +
1296 " has incorrect number of integers; expected " +
1297 llvm::utostr(
Size));
1304 return (1 << (getVmcntBitWidthLo(Version.Major) +
1305 getVmcntBitWidthHi(Version.Major))) -
1310 return (1 << getLoadcntBitWidth(Version.Major)) - 1;
1314 return (1 << getSamplecntBitWidth(Version.Major)) - 1;
1318 return (1 << getBvhcntBitWidth(Version.Major)) - 1;
1322 return (1 << getExpcntBitWidth(Version.Major)) - 1;
1326 return (1 << getLgkmcntBitWidth(Version.Major)) - 1;
1330 return (1 << getDscntBitWidth(Version.Major)) - 1;
1334 return (1 << getKmcntBitWidth(Version.Major)) - 1;
1338 return (1 << getStorecntBitWidth(Version.Major)) - 1;
1342 unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(Version.Major),
1343 getVmcntBitWidthLo(Version.Major));
1344 unsigned Expcnt = getBitMask(getExpcntBitShift(Version.Major),
1345 getExpcntBitWidth(Version.Major));
1346 unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(Version.Major),
1347 getLgkmcntBitWidth(Version.Major));
1348 unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(Version.Major),
1349 getVmcntBitWidthHi(Version.Major));
1350 return VmcntLo | Expcnt | Lgkmcnt | VmcntHi;
1354 unsigned VmcntLo = unpackBits(
Waitcnt, getVmcntBitShiftLo(Version.Major),
1355 getVmcntBitWidthLo(Version.Major));
1356 unsigned VmcntHi = unpackBits(
Waitcnt, getVmcntBitShiftHi(Version.Major),
1357 getVmcntBitWidthHi(Version.Major));
1358 return VmcntLo | VmcntHi << getVmcntBitWidthLo(Version.Major);
1362 return unpackBits(
Waitcnt, getExpcntBitShift(Version.Major),
1363 getExpcntBitWidth(Version.Major));
1367 return unpackBits(
Waitcnt, getLgkmcntBitShift(Version.Major),
1368 getLgkmcntBitWidth(Version.Major));
1372 unsigned &Vmcnt,
unsigned &Expcnt,
unsigned &Lgkmcnt) {
1388 Waitcnt = packBits(Vmcnt,
Waitcnt, getVmcntBitShiftLo(Version.Major),
1389 getVmcntBitWidthLo(Version.Major));
1390 return packBits(Vmcnt >> getVmcntBitWidthLo(Version.Major),
Waitcnt,
1391 getVmcntBitShiftHi(Version.Major),
1392 getVmcntBitWidthHi(Version.Major));
1397 return packBits(Expcnt,
Waitcnt, getExpcntBitShift(Version.Major),
1398 getExpcntBitWidth(Version.Major));
1403 return packBits(Lgkmcnt,
Waitcnt, getLgkmcntBitShift(Version.Major),
1404 getLgkmcntBitWidth(Version.Major));
1408 unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt) {
1422 unsigned Dscnt = getBitMask(getDscntBitShift(Version.Major),
1423 getDscntBitWidth(Version.Major));
1425 unsigned Storecnt = getBitMask(getLoadcntStorecntBitShift(Version.Major),
1426 getStorecntBitWidth(Version.Major));
1427 return Dscnt | Storecnt;
1429 unsigned Loadcnt = getBitMask(getLoadcntStorecntBitShift(Version.Major),
1430 getLoadcntBitWidth(Version.Major));
1431 return Dscnt | Loadcnt;
1438 unpackBits(LoadcntDscnt, getLoadcntStorecntBitShift(Version.Major),
1439 getLoadcntBitWidth(Version.Major));
1440 Decoded.
DsCnt = unpackBits(LoadcntDscnt, getDscntBitShift(Version.Major),
1441 getDscntBitWidth(Version.Major));
1448 unpackBits(StorecntDscnt, getLoadcntStorecntBitShift(Version.Major),
1449 getStorecntBitWidth(Version.Major));
1450 Decoded.
DsCnt = unpackBits(StorecntDscnt, getDscntBitShift(Version.Major),
1451 getDscntBitWidth(Version.Major));
1457 return packBits(Loadcnt,
Waitcnt, getLoadcntStorecntBitShift(Version.Major),
1458 getLoadcntBitWidth(Version.Major));
1462 unsigned Storecnt) {
1463 return packBits(Storecnt,
Waitcnt, getLoadcntStorecntBitShift(Version.Major),
1464 getStorecntBitWidth(Version.Major));
1469 return packBits(Dscnt,
Waitcnt, getDscntBitShift(Version.Major),
1470 getDscntBitWidth(Version.Major));
1486 unsigned Storecnt,
unsigned Dscnt) {
1507 const auto &
Op = Opr[
Idx];
1508 if (
Op.isSupported(STI))
1509 Enc |=
Op.encode(
Op.Default);
1515 int Size,
unsigned Code,
1516 bool &HasNonDefaultVal,
1518 unsigned UsedOprMask = 0;
1519 HasNonDefaultVal =
false;
1521 const auto &
Op = Opr[
Idx];
1522 if (!
Op.isSupported(STI))
1524 UsedOprMask |=
Op.getMask();
1525 unsigned Val =
Op.decode(Code);
1526 if (!
Op.isValid(Val))
1528 HasNonDefaultVal |= (Val !=
Op.Default);
1530 return (Code & ~UsedOprMask) == 0;
1535 unsigned &Val,
bool &IsDefault,
1538 const auto &
Op = Opr[
Idx++];
1539 if (
Op.isSupported(STI)) {
1541 Val =
Op.decode(Code);
1542 IsDefault = (Val ==
Op.Default);
1552 if (InputVal < 0 || InputVal >
Op.Max)
1554 return Op.encode(InputVal);
1559 unsigned &UsedOprMask,
1563 const auto &
Op = Opr[
Idx];
1565 if (!
Op.isSupported(STI)) {
1569 auto OprMask =
Op.getMask();
1570 if (OprMask & UsedOprMask)
1572 UsedOprMask |= OprMask;
1595 HasNonDefaultVal, STI);
1611 return unpackBits(Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1615 return unpackBits(Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1619 return unpackBits(Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1623 return packBits(VmVsrc, Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1631 return packBits(VaVdst, Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1639 return packBits(SaSdst, Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1672 if (Val.Tgt <= Id && Id <= Val.Tgt + Val.MaxIndex) {
1673 Index = (Val.MaxIndex == 0) ? -1 : (Id - Val.Tgt);
1684 if (Val.MaxIndex == 0 &&
Name == Val.Name)
1687 if (Val.MaxIndex > 0 &&
Name.starts_with(Val.Name)) {
1695 if (Suffix.
size() > 1 && Suffix[0] ==
'0')
1698 return Val.Tgt + Id;
1727namespace MTBUFFormat {
1753 if (
Name == lookupTable[Id])
1857 return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
1927 return F.getFnAttributeAsParsedInteger(
"InitialPSInputAddr", 0);
1932 return F.getFnAttributeAsParsedInteger(
1933 "amdgpu-color-export",
1938 return F.getFnAttributeAsParsedInteger(
"amdgpu-depth-export", 0) != 0;
2011 return STI.
hasFeature(AMDGPU::FeatureSRAMECC);
2027 return !STI.
hasFeature(AMDGPU::FeatureUnpackedD16VMem) && !
isCI(STI) &&
2037 if (Version.Major == 10)
2038 return Version.Minor >= 3 ? 13 : 5;
2039 if (Version.Major == 11)
2041 if (Version.Major >= 12)
2042 return HasSampler ? 4 : 5;
2049 return STI.
hasFeature(AMDGPU::FeatureSouthernIslands);
2053 return STI.
hasFeature(AMDGPU::FeatureSeaIslands);
2057 return STI.
hasFeature(AMDGPU::FeatureVolcanicIslands);
2127 return STI.
hasFeature(AMDGPU::FeatureGCN3Encoding);
2131 return STI.
hasFeature(AMDGPU::FeatureGFX10_AEncoding);
2135 return STI.
hasFeature(AMDGPU::FeatureGFX10_BEncoding);
2139 return STI.
hasFeature(AMDGPU::FeatureGFX10_3Insts);
2147 return STI.
hasFeature(AMDGPU::FeatureGFX90AInsts);
2151 return STI.
hasFeature(AMDGPU::FeatureGFX940Insts);
2155 return STI.
hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2159 return STI.
hasFeature(AMDGPU::FeatureMAIInsts);
2167 return STI.
hasFeature(AMDGPU::FeatureDPPSrc1SGPR);
2171 return STI.
hasFeature(AMDGPU::FeatureKernargPreload);
2175 int32_t ArgNumVGPR) {
2176 if (has90AInsts && ArgNumAGPR)
2177 return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
2178 return std::max(ArgNumVGPR, ArgNumAGPR);
2183 const unsigned FirstSubReg =
TRI->getSubReg(
Reg, AMDGPU::sub0);
2184 return SGPRClass.
contains(FirstSubReg != 0 ? FirstSubReg :
Reg) ||
2192#define MAP_REG2REG \
2193 using namespace AMDGPU; \
2195 default: return Reg; \
2196 CASE_CI_VI(FLAT_SCR) \
2197 CASE_CI_VI(FLAT_SCR_LO) \
2198 CASE_CI_VI(FLAT_SCR_HI) \
2199 CASE_VI_GFX9PLUS(TTMP0) \
2200 CASE_VI_GFX9PLUS(TTMP1) \
2201 CASE_VI_GFX9PLUS(TTMP2) \
2202 CASE_VI_GFX9PLUS(TTMP3) \
2203 CASE_VI_GFX9PLUS(TTMP4) \
2204 CASE_VI_GFX9PLUS(TTMP5) \
2205 CASE_VI_GFX9PLUS(TTMP6) \
2206 CASE_VI_GFX9PLUS(TTMP7) \
2207 CASE_VI_GFX9PLUS(TTMP8) \
2208 CASE_VI_GFX9PLUS(TTMP9) \
2209 CASE_VI_GFX9PLUS(TTMP10) \
2210 CASE_VI_GFX9PLUS(TTMP11) \
2211 CASE_VI_GFX9PLUS(TTMP12) \
2212 CASE_VI_GFX9PLUS(TTMP13) \
2213 CASE_VI_GFX9PLUS(TTMP14) \
2214 CASE_VI_GFX9PLUS(TTMP15) \
2215 CASE_VI_GFX9PLUS(TTMP0_TTMP1) \
2216 CASE_VI_GFX9PLUS(TTMP2_TTMP3) \
2217 CASE_VI_GFX9PLUS(TTMP4_TTMP5) \
2218 CASE_VI_GFX9PLUS(TTMP6_TTMP7) \
2219 CASE_VI_GFX9PLUS(TTMP8_TTMP9) \
2220 CASE_VI_GFX9PLUS(TTMP10_TTMP11) \
2221 CASE_VI_GFX9PLUS(TTMP12_TTMP13) \
2222 CASE_VI_GFX9PLUS(TTMP14_TTMP15) \
2223 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \
2224 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \
2225 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \
2226 CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \
2227 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
2228 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
2229 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2230 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2231 CASE_GFXPRE11_GFX11PLUS(M0) \
2232 CASE_GFXPRE11_GFX11PLUS(SGPR_NULL) \
2233 CASE_GFXPRE11_GFX11PLUS_TO(SGPR_NULL64, SGPR_NULL) \
2236#define CASE_CI_VI(node) \
2237 assert(!isSI(STI)); \
2238 case node: return isCI(STI) ? node##_ci : node##_vi;
2240#define CASE_VI_GFX9PLUS(node) \
2241 case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
2243#define CASE_GFXPRE11_GFX11PLUS(node) \
2244 case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
2246#define CASE_GFXPRE11_GFX11PLUS_TO(node, result) \
2247 case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
2256#undef CASE_VI_GFX9PLUS
2257#undef CASE_GFXPRE11_GFX11PLUS
2258#undef CASE_GFXPRE11_GFX11PLUS_TO
2260#define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
2261#define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
2262#define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
2263#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
2271 case AMDGPU::SRC_SHARED_BASE_LO:
2272 case AMDGPU::SRC_SHARED_BASE:
2273 case AMDGPU::SRC_SHARED_LIMIT_LO:
2274 case AMDGPU::SRC_SHARED_LIMIT:
2275 case AMDGPU::SRC_PRIVATE_BASE_LO:
2276 case AMDGPU::SRC_PRIVATE_BASE:
2277 case AMDGPU::SRC_PRIVATE_LIMIT_LO:
2278 case AMDGPU::SRC_PRIVATE_LIMIT:
2279 case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
2281 case AMDGPU::SRC_VCCZ:
2282 case AMDGPU::SRC_EXECZ:
2283 case AMDGPU::SRC_SCC:
2285 case AMDGPU::SGPR_NULL:
2293#undef CASE_VI_GFX9PLUS
2294#undef CASE_GFXPRE11_GFX11PLUS
2295#undef CASE_GFXPRE11_GFX11PLUS_TO
2300 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2307 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2314 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2340 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2351 case AMDGPU::SGPR_LO16RegClassID:
2352 case AMDGPU::AGPR_LO16RegClassID:
2354 case AMDGPU::SGPR_32RegClassID:
2355 case AMDGPU::VGPR_32RegClassID:
2356 case AMDGPU::VRegOrLds_32RegClassID:
2357 case AMDGPU::AGPR_32RegClassID:
2358 case AMDGPU::VS_32RegClassID:
2359 case AMDGPU::AV_32RegClassID:
2360 case AMDGPU::SReg_32RegClassID:
2361 case AMDGPU::SReg_32_XM0RegClassID:
2362 case AMDGPU::SRegOrLds_32RegClassID:
2364 case AMDGPU::SGPR_64RegClassID:
2365 case AMDGPU::VS_64RegClassID:
2366 case AMDGPU::SReg_64RegClassID:
2367 case AMDGPU::VReg_64RegClassID:
2368 case AMDGPU::AReg_64RegClassID:
2369 case AMDGPU::SReg_64_XEXECRegClassID:
2370 case AMDGPU::VReg_64_Align2RegClassID:
2371 case AMDGPU::AReg_64_Align2RegClassID:
2372 case AMDGPU::AV_64RegClassID:
2373 case AMDGPU::AV_64_Align2RegClassID:
2375 case AMDGPU::SGPR_96RegClassID:
2376 case AMDGPU::SReg_96RegClassID:
2377 case AMDGPU::VReg_96RegClassID:
2378 case AMDGPU::AReg_96RegClassID:
2379 case AMDGPU::VReg_96_Align2RegClassID:
2380 case AMDGPU::AReg_96_Align2RegClassID:
2381 case AMDGPU::AV_96RegClassID:
2382 case AMDGPU::AV_96_Align2RegClassID:
2384 case AMDGPU::SGPR_128RegClassID:
2385 case AMDGPU::SReg_128RegClassID:
2386 case AMDGPU::VReg_128RegClassID:
2387 case AMDGPU::AReg_128RegClassID:
2388 case AMDGPU::VReg_128_Align2RegClassID:
2389 case AMDGPU::AReg_128_Align2RegClassID:
2390 case AMDGPU::AV_128RegClassID:
2391 case AMDGPU::AV_128_Align2RegClassID:
2393 case AMDGPU::SGPR_160RegClassID:
2394 case AMDGPU::SReg_160RegClassID:
2395 case AMDGPU::VReg_160RegClassID:
2396 case AMDGPU::AReg_160RegClassID:
2397 case AMDGPU::VReg_160_Align2RegClassID:
2398 case AMDGPU::AReg_160_Align2RegClassID:
2399 case AMDGPU::AV_160RegClassID:
2400 case AMDGPU::AV_160_Align2RegClassID:
2402 case AMDGPU::SGPR_192RegClassID:
2403 case AMDGPU::SReg_192RegClassID:
2404 case AMDGPU::VReg_192RegClassID:
2405 case AMDGPU::AReg_192RegClassID:
2406 case AMDGPU::VReg_192_Align2RegClassID:
2407 case AMDGPU::AReg_192_Align2RegClassID:
2408 case AMDGPU::AV_192RegClassID:
2409 case AMDGPU::AV_192_Align2RegClassID:
2411 case AMDGPU::SGPR_224RegClassID:
2412 case AMDGPU::SReg_224RegClassID:
2413 case AMDGPU::VReg_224RegClassID:
2414 case AMDGPU::AReg_224RegClassID:
2415 case AMDGPU::VReg_224_Align2RegClassID:
2416 case AMDGPU::AReg_224_Align2RegClassID:
2417 case AMDGPU::AV_224RegClassID:
2418 case AMDGPU::AV_224_Align2RegClassID:
2420 case AMDGPU::SGPR_256RegClassID:
2421 case AMDGPU::SReg_256RegClassID:
2422 case AMDGPU::VReg_256RegClassID:
2423 case AMDGPU::AReg_256RegClassID:
2424 case AMDGPU::VReg_256_Align2RegClassID:
2425 case AMDGPU::AReg_256_Align2RegClassID:
2426 case AMDGPU::AV_256RegClassID:
2427 case AMDGPU::AV_256_Align2RegClassID:
2429 case AMDGPU::SGPR_288RegClassID:
2430 case AMDGPU::SReg_288RegClassID:
2431 case AMDGPU::VReg_288RegClassID:
2432 case AMDGPU::AReg_288RegClassID:
2433 case AMDGPU::VReg_288_Align2RegClassID:
2434 case AMDGPU::AReg_288_Align2RegClassID:
2435 case AMDGPU::AV_288RegClassID:
2436 case AMDGPU::AV_288_Align2RegClassID:
2438 case AMDGPU::SGPR_320RegClassID:
2439 case AMDGPU::SReg_320RegClassID:
2440 case AMDGPU::VReg_320RegClassID:
2441 case AMDGPU::AReg_320RegClassID:
2442 case AMDGPU::VReg_320_Align2RegClassID:
2443 case AMDGPU::AReg_320_Align2RegClassID:
2444 case AMDGPU::AV_320RegClassID:
2445 case AMDGPU::AV_320_Align2RegClassID:
2447 case AMDGPU::SGPR_352RegClassID:
2448 case AMDGPU::SReg_352RegClassID:
2449 case AMDGPU::VReg_352RegClassID:
2450 case AMDGPU::AReg_352RegClassID:
2451 case AMDGPU::VReg_352_Align2RegClassID:
2452 case AMDGPU::AReg_352_Align2RegClassID:
2453 case AMDGPU::AV_352RegClassID:
2454 case AMDGPU::AV_352_Align2RegClassID:
2456 case AMDGPU::SGPR_384RegClassID:
2457 case AMDGPU::SReg_384RegClassID:
2458 case AMDGPU::VReg_384RegClassID:
2459 case AMDGPU::AReg_384RegClassID:
2460 case AMDGPU::VReg_384_Align2RegClassID:
2461 case AMDGPU::AReg_384_Align2RegClassID:
2462 case AMDGPU::AV_384RegClassID:
2463 case AMDGPU::AV_384_Align2RegClassID:
2465 case AMDGPU::SGPR_512RegClassID:
2466 case AMDGPU::SReg_512RegClassID:
2467 case AMDGPU::VReg_512RegClassID:
2468 case AMDGPU::AReg_512RegClassID:
2469 case AMDGPU::VReg_512_Align2RegClassID:
2470 case AMDGPU::AReg_512_Align2RegClassID:
2471 case AMDGPU::AV_512RegClassID:
2472 case AMDGPU::AV_512_Align2RegClassID:
2474 case AMDGPU::SGPR_1024RegClassID:
2475 case AMDGPU::SReg_1024RegClassID:
2476 case AMDGPU::VReg_1024RegClassID:
2477 case AMDGPU::AReg_1024RegClassID:
2478 case AMDGPU::VReg_1024_Align2RegClassID:
2479 case AMDGPU::AReg_1024_Align2RegClassID:
2480 case AMDGPU::AV_1024RegClassID:
2481 case AMDGPU::AV_1024_Align2RegClassID:
2495 unsigned RCID =
Desc.operands()[OpNo].RegClass;
2504 return (Val == llvm::bit_cast<uint64_t>(0.0)) ||
2505 (Val == llvm::bit_cast<uint64_t>(1.0)) ||
2506 (Val == llvm::bit_cast<uint64_t>(-1.0)) ||
2507 (Val == llvm::bit_cast<uint64_t>(0.5)) ||
2508 (Val == llvm::bit_cast<uint64_t>(-0.5)) ||
2509 (Val == llvm::bit_cast<uint64_t>(2.0)) ||
2510 (Val == llvm::bit_cast<uint64_t>(-2.0)) ||
2511 (Val == llvm::bit_cast<uint64_t>(4.0)) ||
2512 (Val == llvm::bit_cast<uint64_t>(-4.0)) ||
2513 (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
2530 return (Val == llvm::bit_cast<uint32_t>(0.0f)) ||
2531 (Val == llvm::bit_cast<uint32_t>(1.0f)) ||
2532 (Val == llvm::bit_cast<uint32_t>(-1.0f)) ||
2533 (Val == llvm::bit_cast<uint32_t>(0.5f)) ||
2534 (Val == llvm::bit_cast<uint32_t>(-0.5f)) ||
2535 (Val == llvm::bit_cast<uint32_t>(2.0f)) ||
2536 (Val == llvm::bit_cast<uint32_t>(-2.0f)) ||
2537 (Val == llvm::bit_cast<uint32_t>(4.0f)) ||
2538 (Val == llvm::bit_cast<uint32_t>(-4.0f)) ||
2539 (Val == 0x3e22f983 && HasInv2Pi);
2548 return Val == 0x3F00 ||
2569 return Val == 0x3C00 ||
2596 return 192 + std::abs(
Signed);
2601 case 0x3800:
return 240;
2602 case 0xB800:
return 241;
2603 case 0x3C00:
return 242;
2604 case 0xBC00:
return 243;
2605 case 0x4000:
return 244;
2606 case 0xC000:
return 245;
2607 case 0x4400:
return 246;
2608 case 0xC400:
return 247;
2609 case 0x3118:
return 248;
2616 case 0x3F000000:
return 240;
2617 case 0xBF000000:
return 241;
2618 case 0x3F800000:
return 242;
2619 case 0xBF800000:
return 243;
2620 case 0x40000000:
return 244;
2621 case 0xC0000000:
return 245;
2622 case 0x40800000:
return 246;
2623 case 0xC0800000:
return 247;
2624 case 0x3E22F983:
return 248;
2647 return 192 + std::abs(
Signed);
2651 case 0x3F00:
return 240;
2652 case 0xBF00:
return 241;
2653 case 0x3F80:
return 242;
2654 case 0xBF80:
return 243;
2655 case 0x4000:
return 244;
2656 case 0xC000:
return 245;
2657 case 0x4080:
return 246;
2658 case 0xC080:
return 247;
2659 case 0x3E22:
return 248;
2664 return std::nullopt;
2710 return !(Val & 0xffffffffu);
2712 return isUInt<32>(Val) || isInt<32>(Val);
2736 return A->hasAttribute(Attribute::InReg) ||
2737 A->hasAttribute(Attribute::ByVal);
2740 return A->hasAttribute(Attribute::InReg);
2779 int64_t EncodedOffset) {
2781 return isUInt<23>(EncodedOffset);
2784 : isUInt<8>(EncodedOffset);
2788 int64_t EncodedOffset,
2791 return isInt<24>(EncodedOffset);
2795 isInt<21>(EncodedOffset);
2799 return (ByteOffset & 3) == 0;
2808 return ByteOffset >> 2;
2812 int64_t ByteOffset,
bool IsBuffer) {
2814 return isInt<24>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2820 return isInt<20>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2825 return std::nullopt;
2829 ? std::optional<int64_t>(EncodedOffset)
2834 int64_t ByteOffset) {
2836 return std::nullopt;
2839 return isUInt<32>(EncodedOffset) ? std::optional<int64_t>(EncodedOffset)
2854struct SourceOfDivergence {
2857const SourceOfDivergence *lookupSourceOfDivergence(
unsigned Intr);
2864#define GET_SourcesOfDivergence_IMPL
2865#define GET_UniformIntrinsics_IMPL
2866#define GET_Gfx9BufferFormat_IMPL
2867#define GET_Gfx10BufferFormat_IMPL
2868#define GET_Gfx11PlusBufferFormat_IMPL
2869#include "AMDGPUGenSearchableTables.inc"
2874 return lookupSourceOfDivergence(IntrID);
2878 return lookupAlwaysUniform(IntrID);
2882 uint8_t NumComponents,
2886 ? getGfx11PlusBufferFormatInfo(BitsPerComp, NumComponents,
2888 :
isGFX10(STI) ? getGfx10BufferFormatInfo(BitsPerComp,
2889 NumComponents, NumFormat)
2890 : getGfx9BufferFormatInfo(BitsPerComp,
2891 NumComponents, NumFormat);
2898 : getGfx9BufferFormatInfo(
Format);
2902 for (
auto OpName : { OpName::vdst, OpName::src0, OpName::src1,
2908 if (OpDesc.
operands()[
Idx].RegClass == AMDGPU::VReg_64RegClassID ||
2909 OpDesc.
operands()[
Idx].RegClass == AMDGPU::VReg_64_Align2RegClassID)
2931 OS <<
"Unsupported";
unsigned const MachineRegisterInfo * MRI
static llvm::cl::opt< unsigned > DefaultAMDHSACodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5), llvm::cl::desc("Set default AMDHSA Code Object Version (module flag " "or asm directive still take priority if present)"))
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
@ AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
This file contains the simple types necessary to represent the attributes associated with functions a...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
#define S_00B848_MEM_ORDERED(x)
#define S_00B848_WGP_MODE(x)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSramEccSupported() const
void setTargetIDFromFeaturesString(StringRef FS)
TargetIDSetting getXnackSetting() const
AMDGPUTargetID(const MCSubtargetInfo &STI)
bool isXnackSupported() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
std::string toString() const
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
unsigned getIndexOfDstInParsedOperands() const
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
unsigned getCompParsedSrcOperandsNum() const
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
CallingConv::ID getCallingConv() const
bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const
Determine whether the argument or parameter has the given attribute.
This class represents an Operation in the Expression.
constexpr bool test(unsigned I) const
unsigned getAddressSpace() const
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
const FeatureBitset & getFeatureBits() const
A Module instance is used to store all the information related to an LLVM module.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
std::string str() const
str - Get the contents as an std::string.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
Manages the enabling and disabling of subtarget specific features.
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Triple - Helper class for working with autoconf configuration names.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
@ LOCAL_ADDRESS
Address space for local memory.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
const CustomOperandVal DepCtrInfo[]
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
static constexpr ExpTgt ExpTgtInfo[]
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
@ ET_DUAL_SRC_BLEND_MAX_IDX
constexpr uint32_t VersionMajor
HSA metadata major version.
@ COMPLETION_ACTION_OFFSET
@ MULTIGRID_SYNC_ARG_OFFSET
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
static TargetIDSetting getTargetIDSettingFromFeatureString(StringRef FeatureString)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
static unsigned getGranulatedNumRegisterBlocks(unsigned NumRegs, unsigned Granule)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI)
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
StringRef getMsgOpName(int64_t MsgId, uint64_t Encoding, const MCSubtargetInfo &STI)
Map from an encoding to the symbolic name for a sendmsg operation.
static uint64_t getMsgIdMask(const MCSubtargetInfo &STI)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
SmallVector< unsigned > getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size)
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
static unsigned encodeStorecnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)
static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
bool isVOPCAsmOnly(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
const int OPR_ID_UNSUPPORTED
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isInlinableLiteralV2I16(uint32_t Literal)
int getMTBUFElements(unsigned Opc)
static int encodeCustomOperandVal(const CustomOperandVal &Op, int64_t InputVal)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
bool isInlinableLiteralV2BF16(uint32_t Literal)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV216(bool IsFloat, uint32_t Literal)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
bool isGFX12Plus(const MCSubtargetInfo &STI)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler)
CanBeVOPD getCanBeVOPD(unsigned Opc)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getStorecntBitMask(const IsaVersion &Version)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
const int OPR_VAL_INVALID
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
bool isGroupSegment(const GlobalValue *GV)
IsaVersion getIsaVersion(StringRef GPU)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
static unsigned getCombinedCountBitMask(const IsaVersion &Version, bool IsStore)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
unsigned getDefaultAMDHSACodeObjectVersion()
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
static bool isDwordAligned(uint64_t ByteOffset)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getSamplecntBitMask(const IsaVersion &Version)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
unsigned getKmcntBitMask(const IsaVersion &Version)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool getMUBUFTfe(unsigned Opc)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
bool isHi(unsigned Reg, const MCRegisterInfo &MRI)
unsigned getBvhcntBitMask(const IsaVersion &Version)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
static unsigned encodeLoadcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
@ OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_V2BF16
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_V2BF16
@ OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isNotGFX9Plus(const MCSubtargetInfo &STI)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI)
const int OPR_ID_DUPLICATE
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
static unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
bool getMUBUFIsBufferInv(unsigned Opc)
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
static int encodeCustomOperand(const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
bool getVOP2IsSingle(unsigned Opc)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned getLoadcntBitMask(const IsaVersion &Version)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool hasVOPD(const MCSubtargetInfo &STI)
static unsigned encodeDscnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned getDscntBitMask(const IsaVersion &Version)
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
@ AMDGPU_Gfx
Used for AMD graphics targets.
@ AMDGPU_CS_ChainPreserve
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
@ SPIR_KERNEL
Used for SPIR kernel functions.
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
@ ELFABIVERSION_AMDGPU_HSA_V4
@ ELFABIVERSION_AMDGPU_HSA_V5
@ ELFABIVERSION_AMDGPU_HSA_V6
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
@ AlwaysUniform
The result values are always uniform.
@ Default
The result values are uniform if and only if all operands are uniform.
AMD Kernel Code Object (amd_kernel_code_t).
Instruction set architecture version.
Represents the counter values to wait for in an s_waitcnt instruction.
Description of the encoding of one expression Op.