21#define GET_TARGET_REGBANK_IMPL
22#include "ARMGenRegisterBank.inc"
49 unsigned Start,
unsigned Length,
58 "Wrong mapping for GPR");
61 "Wrong mapping for SPR");
64 "Wrong mapping for DPR");
101 "Wrong value mapping for 3 GPR ops instruction");
104 "Wrong value mapping for 3 GPR ops instruction");
107 "Wrong value mapping for 3 GPR ops instruction");
111 "Wrong value mapping for 3 SPR ops instruction");
114 "Wrong value mapping for 3 SPR ops instruction");
117 "Wrong value mapping for 3 SPR ops instruction");
121 "Wrong value mapping for 3 DPR ops instruction");
124 "Wrong value mapping for 3 DPR ops instruction");
127 "Wrong value mapping for 3 DPR ops instruction");
141 static auto InitializeRegisterBankOnce = [&]() {
144 assert(&ARM::GPRRegBank == &RBGPR &&
"The order in RegBanks is messed up");
148 "Subclass not added?");
150 "Subclass not added?");
152 "Subclass not added?");
154 "Subclass not added?");
156 "Subclass not added?");
158 "Subclass not added?");
159 assert(RBGPR.
covers(*
TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
160 "Subclass not added?");
162 "GPRs should hold up to 32-bit");
170 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);
178 switch (RC.
getID()) {
180 case GPRwithAPSRRegClassID:
181 case GPRnoipRegClassID:
182 case GPRnopcRegClassID:
183 case GPRnoip_and_GPRnopcRegClassID:
185 case GPRspRegClassID:
186 case tcGPRRegClassID:
187 case tcGPRnotr12RegClassID:
189 case tGPREvenRegClassID:
190 case tGPROddRegClassID:
191 case tGPR_and_tGPREvenRegClassID:
192 case tGPR_and_tGPROddRegClassID:
193 case tGPREven_and_tcGPRRegClassID:
194 case tGPROdd_and_tcGPRRegClassID:
195 case tGPREven_and_tcGPRnotr12RegClassID:
198 case SPR_8RegClassID:
200 case DPR_8RegClassID:
213 auto Opc =
MI.getOpcode();
223 using namespace TargetOpcode;
227 unsigned NumOperands =
MI.getNumOperands();
235 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
270 LLT LargeTy =
MRI.getType(
MI.getOperand(1).getReg());
280 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
293 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
300 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
314 LLT ToTy =
MRI.getType(
MI.getOperand(0).getReg());
315 LLT FromTy =
MRI.getType(
MI.getOperand(1).getReg());
323 LLT ToTy =
MRI.getType(
MI.getOperand(0).getReg());
324 LLT FromTy =
MRI.getType(
MI.getOperand(1).getReg());
333 LLT ToTy =
MRI.getType(
MI.getOperand(0).getReg());
334 LLT FromTy =
MRI.getType(
MI.getOperand(1).getReg());
347 LLT ToTy =
MRI.getType(
MI.getOperand(0).getReg());
348 LLT FromTy =
MRI.getType(
MI.getOperand(1).getReg());
360 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
374 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
376 LLT Ty2 =
MRI.getType(
MI.getOperand(1).getReg());
388 LLT Ty2 =
MRI.getType(
MI.getOperand(2).getReg());
398 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
400 LLT Ty1 =
MRI.getType(
MI.getOperand(2).getReg());
401 LLT Ty2 =
MRI.getType(
MI.getOperand(3).getReg());
405 "Mismatched operand sizes for G_FCMP");
408 assert((
Size == 32 ||
Size == 64) &&
"Unsupported size for G_FCMP");
414 FPRValueMapping, FPRValueMapping});
417 case G_MERGE_VALUES: {
420 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
421 LLT Ty1 =
MRI.getType(
MI.getOperand(1).getReg());
422 LLT Ty2 =
MRI.getType(
MI.getOperand(2).getReg());
432 case G_UNMERGE_VALUES: {
435 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
436 LLT Ty1 =
MRI.getType(
MI.getOperand(1).getReg());
437 LLT Ty2 =
MRI.getType(
MI.getOperand(2).getReg());
458 unsigned Size =
MRI.getType(MaybeReg.
getReg()).getSizeInBits();
480 for (
unsigned i = 0; i < NumOperands; i++) {
481 for (
const auto &Mapping : OperandsMapping[i]) {
483 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
485 "Trying to use floating point register bank on target without vfp");
unsigned const MachineRegisterInfo * MRI
This file declares the targeting of the RegisterBankInfo class for ARM.
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getID() const
Get the identifier of this register bank.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const RegisterBankInfo::PartialMapping PartMappings[]
static void checkPartialMappings()
static void checkValueMappings()
const RegisterBankInfo::ValueMapping ValueMappings[]
static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM, const RegisterBankInfo::PartialMapping *BreakDown)
static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM, unsigned Start, unsigned Length, unsigned RegBankID)
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Helper struct that represents how a value is partially mapped into a register.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
const RegisterBank * RegBank
Register bank where the partial value lives.
unsigned Length
Length of this mapping in bits.
Helper struct that represents how a value is mapped through different register banks.
unsigned NumBreakDowns
Number of partial mapping to break down this value.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
The llvm::once_flag structure.