15#ifndef LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTORIMPL_H
16#define LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTORIMPL_H
44template <
class TgtExecutor,
class PredicateBitset,
class ComplexMatcherMemFn,
45 class CustomRendererFn>
53 const PredicateBitset &AvailableFeatures,
62 bool NoFPException = !State.
MIs[0]->getDesc().mayRaiseFPException();
66 enum RejectAction { RejectAndGiveUp, RejectAndResume };
67 auto handleReject = [&]() -> RejectAction {
69 dbgs() << CurrentIdx <<
": Rejected\n");
70 if (OnFailResumeAt.
empty())
71 return RejectAndGiveUp;
74 dbgs() << CurrentIdx <<
": Resume at " << CurrentIdx <<
" ("
75 << OnFailResumeAt.
size() <<
" try-blocks remain)\n");
76 return RejectAndResume;
79 const auto propagateFlags = [&]() {
80 for (
auto MIB : OutMIs) {
84 if (NoFPException && MIB->mayRaiseFPException())
88 MIB.setMIFlags(MIBFlags);
96 const auto getTypeFromIdx = [&](int64_t
Idx) ->
LLT {
102 const auto readULEB = [&]() {
111 const auto readS8 = [&]() {
return (int8_t)MatchTable[CurrentIdx++]; };
113 const auto readU16 = [&]() {
114 auto V = readBytesAs<uint16_t>(MatchTable + CurrentIdx);
119 const auto readU32 = [&]() {
120 auto V = readBytesAs<uint32_t>(MatchTable + CurrentIdx);
125 const auto readU64 = [&]() {
126 auto V = readBytesAs<uint64_t>(MatchTable + CurrentIdx);
138 MI->eraseFromParent();
142 assert(CurrentIdx != ~0u &&
"Invalid MatchTable index");
143 uint8_t MatcherOpcode = MatchTable[CurrentIdx++];
144 switch (MatcherOpcode) {
147 dbgs() << CurrentIdx <<
": Begin try-block\n");
160 assert(NewInsnID != 0 &&
"Refusing to modify MIs[0]");
165 dbgs() << CurrentIdx <<
": Not a register\n");
166 if (handleReject() == RejectAndGiveUp)
172 dbgs() << CurrentIdx <<
": Is a physical register\n");
173 if (handleReject() == RejectAndGiveUp)
184 if ((
size_t)NewInsnID < State.
MIs.
size())
185 State.
MIs[NewInsnID] = NewMI;
188 "Expected to store MIs in order");
192 dbgs() << CurrentIdx <<
": MIs[" << NewInsnID
193 <<
"] = GIM_RecordInsn(" << InsnID <<
", " << OpIdx
199 uint16_t ExpectedBitsetID = readU16();
202 <<
": GIM_CheckFeatures(ExpectedBitsetID="
203 << ExpectedBitsetID <<
")\n");
204 if ((AvailableFeatures & ExecInfo.
FeatureBitsets[ExpectedBitsetID]) !=
206 if (handleReject() == RejectAndGiveUp)
217 Expected1 = readU16();
219 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
220 unsigned Opcode = State.
MIs[InsnID]->getOpcode();
223 dbgs() << CurrentIdx <<
": GIM_CheckOpcode(MIs[" << InsnID
224 <<
"], ExpectedOpcode=" << Expected0;
226 <<
" || " << Expected1;
227 dbgs() <<
") // Got=" << Opcode <<
"\n";);
229 if (Opcode != Expected0 && Opcode != Expected1) {
230 if (handleReject() == RejectAndGiveUp)
241 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
242 const int64_t Opcode = State.
MIs[InsnID]->getOpcode();
245 dbgs() << CurrentIdx <<
": GIM_SwitchOpcode(MIs[" << InsnID <<
"], ["
246 << LowerBound <<
", " << UpperBound <<
"), Default=" <<
Default
247 <<
", JumpTable...) // Got=" << Opcode <<
"\n";
249 if (Opcode < LowerBound || UpperBound <= Opcode) {
253 const auto EntryIdx = (Opcode - LowerBound);
256 readBytesAs<uint32_t>(MatchTable + CurrentIdx + (EntryIdx * 4));
272 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
276 dbgs() << CurrentIdx <<
": GIM_SwitchType(MIs[" << InsnID
277 <<
"]->getOperand(" << OpIdx <<
"), [" << LowerBound <<
", "
278 << UpperBound <<
"), Default=" <<
Default
279 <<
", JumpTable...) // Got=";
281 dbgs() <<
"Not a VReg\n";
290 const auto TyI = ExecInfo.
TypeIDMap.find(Ty);
295 const int64_t
TypeID = TyI->second;
300 const auto NumEntry = (
TypeID - LowerBound);
303 readBytesAs<uint32_t>(MatchTable + CurrentIdx + (NumEntry * 4));
316 dbgs() << CurrentIdx <<
": GIM_CheckNumOperands(MIs["
317 << InsnID <<
"], Expected=" <<
Expected <<
")\n");
318 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
319 if (State.
MIs[InsnID]->getNumOperands() !=
Expected) {
320 if (handleReject() == RejectAndGiveUp)
332 dbgs() << CurrentIdx <<
": GIM_CheckImmPredicate(MIs["
333 << InsnID <<
"]->getOperand(" << OpIdx
334 <<
"), Predicate=" << Predicate <<
")\n");
335 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
336 assert((State.
MIs[InsnID]->getOperand(OpIdx).isImm() ||
337 State.
MIs[InsnID]->getOperand(OpIdx).isCImm()) &&
338 "Expected immediate operand");
341 if (State.
MIs[InsnID]->getOperand(OpIdx).isCImm())
342 Value = State.
MIs[InsnID]->getOperand(OpIdx).getCImm()->getSExtValue();
343 else if (State.
MIs[InsnID]->getOperand(OpIdx).isImm())
344 Value = State.
MIs[InsnID]->getOperand(OpIdx).getImm();
349 if (handleReject() == RejectAndGiveUp)
358 << CurrentIdx <<
": GIM_CheckAPIntImmPredicate(MIs["
359 << InsnID <<
"], Predicate=" << Predicate <<
")\n");
360 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
361 assert(State.
MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
362 "Expected G_CONSTANT");
364 if (!State.
MIs[InsnID]->getOperand(1).isCImm())
368 State.
MIs[InsnID]->getOperand(1).getCImm()->getValue();
370 if (handleReject() == RejectAndGiveUp)
379 << CurrentIdx <<
": GIM_CheckAPFloatImmPredicate(MIs["
380 << InsnID <<
"], Predicate=" << Predicate <<
")\n");
381 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
382 assert(State.
MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
383 "Expected G_FCONSTANT");
384 assert(State.
MIs[InsnID]->getOperand(1).isFPImm() &&
385 "Expected FPImm operand");
388 State.
MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
391 if (handleReject() == RejectAndGiveUp)
401 <<
": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs["
402 << InsnID <<
"])\n");
403 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
406 assert((
MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
407 MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) &&
408 "Expected G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC");
412 if (handleReject() == RejectAndGiveUp)
417 if (handleReject() == RejectAndGiveUp)
431 <<
": GIM_CheckSimplePredicate(Predicate="
432 << Predicate <<
")\n");
435 if (handleReject() == RejectAndGiveUp)
445 << CurrentIdx <<
": GIM_CheckCxxPredicate(MIs["
446 << InsnID <<
"], Predicate=" << Predicate <<
")\n");
447 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
451 if (handleReject() == RejectAndGiveUp)
459 dbgs() << CurrentIdx <<
": GIM_CheckHasNoUse(MIs["
463 assert(
MI &&
"Used insn before defined");
464 assert(
MI->getNumDefs() > 0 &&
"No defs");
465 const Register Res =
MI->getOperand(0).getReg();
467 if (!
MRI.use_nodbg_empty(Res)) {
468 if (handleReject() == RejectAndGiveUp)
478 dbgs() << CurrentIdx <<
": GIM_CheckAtomicOrdering(MIs["
479 << InsnID <<
"], " << (
uint64_t)Ordering <<
")\n");
480 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
481 if (!State.
MIs[InsnID]->hasOneMemOperand())
482 if (handleReject() == RejectAndGiveUp)
485 for (
const auto &MMO : State.
MIs[InsnID]->memoperands())
486 if (MMO->getMergedOrdering() != Ordering)
487 if (handleReject() == RejectAndGiveUp)
496 <<
": GIM_CheckAtomicOrderingOrStrongerThan(MIs["
497 << InsnID <<
"], " << (
uint64_t)Ordering <<
")\n");
498 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
499 if (!State.
MIs[InsnID]->hasOneMemOperand())
500 if (handleReject() == RejectAndGiveUp)
503 for (
const auto &MMO : State.
MIs[InsnID]->memoperands())
505 if (handleReject() == RejectAndGiveUp)
514 <<
": GIM_CheckAtomicOrderingWeakerThan(MIs["
515 << InsnID <<
"], " << (
uint64_t)Ordering <<
")\n");
516 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
517 if (!State.
MIs[InsnID]->hasOneMemOperand())
518 if (handleReject() == RejectAndGiveUp)
521 for (
const auto &MMO : State.
MIs[InsnID]->memoperands())
523 if (handleReject() == RejectAndGiveUp)
531 const uint64_t NumAddrSpace = MatchTable[CurrentIdx++];
533 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
534 if (handleReject() == RejectAndGiveUp)
541 const uint64_t LastIdx = CurrentIdx + NumAddrSpace;
544 *(State.
MIs[InsnID]->memoperands_begin() + MMOIdx);
548 for (
unsigned I = 0;
I != NumAddrSpace; ++
I) {
551 dbgs() <<
"addrspace(" << MMOAddrSpace <<
") vs "
552 << AddrSpace <<
'\n');
554 if (AddrSpace == MMOAddrSpace) {
560 CurrentIdx = LastIdx;
561 if (!
Success && handleReject() == RejectAndGiveUp)
570 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
572 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
573 if (handleReject() == RejectAndGiveUp)
579 *(State.
MIs[InsnID]->memoperands_begin() + MMOIdx);
581 dbgs() << CurrentIdx <<
": GIM_CheckMemoryAlignment"
582 <<
"(MIs[" << InsnID <<
"]->memoperands() + "
583 << MMOIdx <<
")->getAlignment() >= " <<
MinAlign
596 dbgs() << CurrentIdx <<
": GIM_CheckMemorySizeEqual(MIs["
597 << InsnID <<
"]->memoperands() + " << MMOIdx
598 <<
", Size=" <<
Size <<
")\n");
599 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
601 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
602 if (handleReject() == RejectAndGiveUp)
608 *(State.
MIs[InsnID]->memoperands_begin() + MMOIdx);
611 <<
" bytes vs " <<
Size
614 if (handleReject() == RejectAndGiveUp)
627 TgtExecutor::getName(),
628 dbgs() << CurrentIdx <<
": GIM_CheckMemorySize"
633 <<
"LLT(MIs[" << InsnID <<
"]->memoperands() + " << MMOIdx
634 <<
", OpIdx=" << OpIdx <<
")\n");
635 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
640 dbgs() << CurrentIdx <<
": Not a register\n");
641 if (handleReject() == RejectAndGiveUp)
646 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
647 if (handleReject() == RejectAndGiveUp)
653 *(State.
MIs[InsnID]->memoperands_begin() + MMOIdx);
658 if (handleReject() == RejectAndGiveUp)
662 if (handleReject() == RejectAndGiveUp)
666 if (handleReject() == RejectAndGiveUp)
677 dbgs() << CurrentIdx <<
": GIM_CheckType(MIs[" << InsnID
678 <<
"]->getOperand(" << OpIdx
679 <<
"), TypeID=" <<
TypeID <<
")\n");
680 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
683 if (handleReject() == RejectAndGiveUp)
694 dbgs() << CurrentIdx <<
": GIM_CheckPointerToAny(MIs["
695 << InsnID <<
"]->getOperand(" << OpIdx
696 <<
"), SizeInBits=" << SizeInBits <<
")\n");
697 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
702 if (SizeInBits == 0) {
708 assert(SizeInBits != 0 &&
"Pointer size must be known");
712 if (handleReject() == RejectAndGiveUp)
714 }
else if (handleReject() == RejectAndGiveUp)
725 dbgs() << CurrentIdx <<
": GIM_RecordNamedOperand(MIs["
726 << InsnID <<
"]->getOperand(" << OpIdx
727 <<
"), StoreIdx=" << StoreIdx <<
")\n");
728 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
736 int TypeIdx = readS8();
739 dbgs() << CurrentIdx <<
": GIM_RecordRegType(MIs["
740 << InsnID <<
"]->getOperand(" << OpIdx
741 <<
"), TypeIdx=" << TypeIdx <<
")\n");
742 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
743 assert(TypeIdx < 0 &&
"Temp types always have negative indexes!");
745 TypeIdx = 1 - TypeIdx;
746 const auto &
Op = State.
MIs[InsnID]->getOperand(OpIdx);
760 dbgs() << CurrentIdx <<
": GIM_CheckRegBankForClass(MIs["
761 << InsnID <<
"]->getOperand(" << OpIdx
762 <<
"), RCEnum=" << RCEnum <<
")\n");
763 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
769 if (handleReject() == RejectAndGiveUp)
779 uint16_t ComplexPredicateID = readU16();
781 dbgs() << CurrentIdx <<
": State.Renderers[" << RendererID
782 <<
"] = GIM_CheckComplexPattern(MIs[" << InsnID
783 <<
"]->getOperand(" << OpIdx
784 <<
"), ComplexPredicateID=" << ComplexPredicateID
786 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
790 State.
MIs[InsnID]->getOperand(OpIdx));
793 else if (handleReject() == RejectAndGiveUp)
806 dbgs() << CurrentIdx <<
": GIM_CheckConstantInt(MIs["
807 << InsnID <<
"]->getOperand(" << OpIdx
808 <<
"), Value=" <<
Value <<
")\n");
809 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
817 if (handleReject() == RejectAndGiveUp)
824 if (handleReject() == RejectAndGiveUp)
827 }
else if (handleReject() == RejectAndGiveUp)
836 int64_t
Value = readU64();
838 dbgs() << CurrentIdx <<
": GIM_CheckLiteralInt(MIs["
839 << InsnID <<
"]->getOperand(" << OpIdx
840 <<
"), Value=" <<
Value <<
")\n");
841 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
849 if (handleReject() == RejectAndGiveUp)
860 dbgs() << CurrentIdx <<
": GIM_CheckIntrinsicID(MIs["
861 << InsnID <<
"]->getOperand(" << OpIdx
862 <<
"), Value=" <<
Value <<
")\n");
863 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
866 if (handleReject() == RejectAndGiveUp)
875 dbgs() << CurrentIdx <<
": GIM_CheckCmpPredicate(MIs["
876 << InsnID <<
"]->getOperand(" << OpIdx
877 <<
"), Value=" <<
Value <<
")\n");
878 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
881 if (handleReject() == RejectAndGiveUp)
889 dbgs() << CurrentIdx <<
": GIM_CheckIsMBB(MIs[" << InsnID
890 <<
"]->getOperand(" << OpIdx <<
"))\n");
891 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
892 if (!State.
MIs[InsnID]->getOperand(OpIdx).isMBB()) {
893 if (handleReject() == RejectAndGiveUp)
902 dbgs() << CurrentIdx <<
": GIM_CheckIsImm(MIs[" << InsnID
903 <<
"]->getOperand(" << OpIdx <<
"))\n");
904 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
905 if (!State.
MIs[InsnID]->getOperand(OpIdx).isImm()) {
906 if (handleReject() == RejectAndGiveUp)
912 uint64_t NumInsn = MatchTable[CurrentIdx++];
914 dbgs() << CurrentIdx <<
": GIM_CheckIsSafeToFold(N = "
915 << NumInsn <<
")\n");
917 for (
unsigned K = 1,
E = NumInsn + 1; K <
E; ++K) {
919 if (handleReject() == RejectAndGiveUp)
932 dbgs() << CurrentIdx <<
": GIM_CheckIsSameOperand(MIs["
933 << InsnID <<
"][" << OpIdx <<
"], MIs["
934 << OtherInsnID <<
"][" << OtherOpIdx <<
"])\n");
935 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
936 assert(State.
MIs[OtherInsnID] !=
nullptr &&
"Used insn before defined");
942 if (
Op.isReg() && OtherOp.
isReg()) {
949 if (!
Op.isIdenticalTo(OtherOp)) {
950 if (handleReject() == RejectAndGiveUp)
962 dbgs() << CurrentIdx <<
": GIM_CheckCanReplaceReg(MIs["
963 << OldInsnID <<
"][" << OldOpIdx <<
"] = MIs["
964 << NewInsnID <<
"][" << NewOpIdx <<
"])\n");
966 Register Old = State.
MIs[OldInsnID]->getOperand(OldOpIdx).getReg();
967 Register New = State.
MIs[NewInsnID]->getOperand(NewOpIdx).getReg();
969 if (handleReject() == RejectAndGiveUp)
979 dbgs() << CurrentIdx <<
": GIM_MIFlags(MIs[" << InsnID
980 <<
"], " << Flags <<
")\n");
981 if ((State.
MIs[InsnID]->getFlags() & Flags) != Flags) {
982 if (handleReject() == RejectAndGiveUp)
992 dbgs() << CurrentIdx <<
": GIM_MIFlagsNot(MIs[" << InsnID
993 <<
"], " << Flags <<
")\n");
994 if ((State.
MIs[InsnID]->getFlags() & Flags)) {
995 if (handleReject() == RejectAndGiveUp)
1002 dbgs() << CurrentIdx <<
": GIM_Reject\n");
1003 if (handleReject() == RejectAndGiveUp)
1010 if (NewInsnID >= OutMIs.
size())
1011 OutMIs.
resize(NewInsnID + 1);
1017 OutMIs[NewInsnID]->setDesc(
TII.get(NewOpcode));
1021 dbgs() << CurrentIdx <<
": GIR_MutateOpcode(OutMIs["
1022 << NewInsnID <<
"], MIs[" << OldInsnID <<
"], "
1023 << NewOpcode <<
")\n");
1031 if (NewInsnID >= OutMIs.
size())
1032 OutMIs.
resize(NewInsnID + 1);
1034 OutMIs[NewInsnID] = Builder.
buildInstr(Opcode);
1036 dbgs() << CurrentIdx <<
": GIR_BuildMI(OutMIs["
1037 << NewInsnID <<
"], " << Opcode <<
")\n");
1046 dbgs() << CurrentIdx <<
": GIR_BuildConstant(TempReg["
1047 << TempRegID <<
"], Imm=" << Imm <<
")\n");
1058 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
1059 OutMIs[NewInsnID].add(State.
MIs[OldInsnID]->getOperand(OpIdx));
1062 << CurrentIdx <<
": GIR_Copy(OutMIs[" << NewInsnID
1063 <<
"], MIs[" << OldInsnID <<
"], " << OpIdx <<
")\n");
1072 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
1075 OutMIs[NewInsnID].addReg(ZeroReg);
1077 OutMIs[NewInsnID].add(MO);
1079 dbgs() << CurrentIdx <<
": GIR_CopyOrAddZeroReg(OutMIs["
1080 << NewInsnID <<
"], MIs[" << OldInsnID <<
"], "
1081 << OpIdx <<
", " << ZeroReg <<
")\n");
1090 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
1091 OutMIs[NewInsnID].addReg(State.
MIs[OldInsnID]->getOperand(OpIdx).getReg(),
1094 dbgs() << CurrentIdx <<
": GIR_CopySubReg(OutMIs["
1095 << NewInsnID <<
"], MIs[" << OldInsnID <<
"], "
1096 << OpIdx <<
", " << SubRegIdx <<
")\n");
1104 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1106 OutMIs[InsnID].addDef(RegNum, Flags);
1108 dbgs() << CurrentIdx <<
": GIR_AddImplicitDef(OutMIs["
1109 << InsnID <<
"], " << RegNum <<
")\n");
1116 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1119 dbgs() << CurrentIdx <<
": GIR_AddImplicitUse(OutMIs["
1120 << InsnID <<
"], " << RegNum <<
")\n");
1128 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1129 OutMIs[InsnID].addReg(RegNum, RegFlags);
1132 << CurrentIdx <<
": GIR_AddRegister(OutMIs[" << InsnID
1133 <<
"], " << RegNum <<
", " << RegFlags <<
")\n");
1139 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1142 dbgs() << CurrentIdx <<
": GIR_AddIntrinsicID(OutMIs["
1143 << InsnID <<
"], " <<
Value <<
")\n");
1150 dbgs() << CurrentIdx <<
": GIR_SetImplicitDefDead(OutMIs["
1151 << InsnID <<
"], OpIdx=" << OpIdx <<
")\n");
1153 assert(
MI &&
"Modifying undefined instruction");
1154 MI->getOperand(
MI->getNumExplicitOperands() + OpIdx).setIsDead();
1162 dbgs() << CurrentIdx <<
": GIR_SetMIFlags(OutMIs["
1163 << InsnID <<
"], " << Flags <<
")\n");
1165 MI->setFlags(
MI->getFlags() | Flags);
1173 dbgs() << CurrentIdx <<
": GIR_UnsetMIFlags(OutMIs["
1174 << InsnID <<
"], " << Flags <<
")\n");
1176 MI->setFlags(
MI->getFlags() & ~Flags);
1184 dbgs() << CurrentIdx <<
": GIR_CopyMIFlags(OutMIs["
1185 << InsnID <<
"], MIs[" << OldInsnID <<
"])\n");
1187 MI->setFlags(
MI->getFlags() | State.
MIs[OldInsnID]->getFlags());
1197 TempRegFlags = readU16();
1202 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1204 OutMIs[InsnID].addReg(State.
TempRegisters[TempRegID], TempRegFlags,
1207 TgtExecutor::getName(),
1208 dbgs() << CurrentIdx <<
": GIR_AddTempRegister(OutMIs[" << InsnID
1209 <<
"], TempRegisters[" << TempRegID <<
"]";
1211 dbgs() <<
", " << TempRegFlags <<
")\n");
1217 const bool IsAdd8 = (MatcherOpcode ==
GIR_AddImm8);
1219 uint64_t Imm = IsAdd8 ? (int64_t)readS8() : readU64();
1220 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1221 OutMIs[InsnID].addImm(Imm);
1223 dbgs() << CurrentIdx <<
": GIR_AddImm(OutMIs[" << InsnID
1224 <<
"], " << Imm <<
")\n");
1232 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1236 OutMIs[InsnID].addCImm(
1239 dbgs() << CurrentIdx <<
": GIR_AddCImm(OutMIs[" << InsnID
1240 <<
"], TypeID=" <<
TypeID <<
", Imm=" << Imm
1248 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1249 for (
const auto &RenderOpFn : State.
Renderers[RendererID])
1250 RenderOpFn(OutMIs[InsnID]);
1252 dbgs() << CurrentIdx <<
": GIR_ComplexRenderer(OutMIs["
1253 << InsnID <<
"], " << RendererID <<
")\n");
1260 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1261 State.
Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
1263 dbgs() << CurrentIdx
1264 <<
": GIR_ComplexSubOperandRenderer(OutMIs["
1265 << InsnID <<
"], " << RendererID <<
", "
1266 << RenderOpID <<
")\n");
1275 assert(
MI &&
"Attempted to add to undefined instruction");
1277 MI->getOperand(
MI->getNumOperands() - 1).setSubReg(SubRegIdx);
1279 dbgs() << CurrentIdx
1280 <<
": GIR_ComplexSubOperandSubRegRenderer(OutMIs["
1281 << InsnID <<
"], " << RendererID <<
", "
1282 << RenderOpID <<
", " << SubRegIdx <<
")\n");
1289 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
1290 assert(State.
MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
1291 "Expected G_CONSTANT");
1292 if (State.
MIs[OldInsnID]->getOperand(1).isCImm()) {
1293 OutMIs[NewInsnID].addImm(
1294 State.
MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
1295 }
else if (State.
MIs[OldInsnID]->getOperand(1).isImm())
1296 OutMIs[NewInsnID].add(State.
MIs[OldInsnID]->getOperand(1));
1300 dbgs() << CurrentIdx <<
": GIR_CopyConstantAsSImm(OutMIs["
1301 << NewInsnID <<
"], MIs[" << OldInsnID <<
"])\n");
1309 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
1310 assert(State.
MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
1311 "Expected G_FCONSTANT");
1312 if (State.
MIs[OldInsnID]->getOperand(1).isFPImm())
1313 OutMIs[NewInsnID].addFPImm(
1314 State.
MIs[OldInsnID]->getOperand(1).getFPImm());
1319 << CurrentIdx <<
": GIR_CopyFPConstantAsFPImm(OutMIs["
1320 << NewInsnID <<
"], MIs[" << OldInsnID <<
"])\n");
1328 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1330 dbgs() << CurrentIdx <<
": GIR_CustomRenderer(OutMIs["
1331 << InsnID <<
"], MIs[" << OldInsnID <<
"], "
1332 << RendererFnID <<
")\n");
1334 OutMIs[InsnID], *State.
MIs[OldInsnID],
1341 dbgs() << CurrentIdx <<
": GIR_CustomAction(FnID=" << FnID
1352 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1355 dbgs() << CurrentIdx
1356 <<
": GIR_CustomOperandRenderer(OutMIs[" << InsnID
1357 <<
"], MIs[" << OldInsnID <<
"]->getOperand("
1358 << OpIdx <<
"), " << RendererFnID <<
")\n");
1360 OutMIs[InsnID], *State.
MIs[OldInsnID], OpIdx);
1367 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1375 dbgs() << CurrentIdx <<
": GIR_ConstrainOperandRC(OutMIs["
1376 << InsnID <<
"], " << OpIdx <<
", " << RCEnum
1386 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1390 dbgs() << CurrentIdx
1391 <<
": GIR_ConstrainSelectedInstOperands(OutMIs["
1392 << InsnID <<
"])\n");
1397 uint64_t NumInsn = MatchTable[CurrentIdx++];
1398 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1401 dbgs() << CurrentIdx <<
": GIR_MergeMemOperands(OutMIs["
1403 for (
unsigned K = 0; K < NumInsn; ++K) {
1406 dbgs() <<
", MIs[" << NextID <<
"]");
1407 for (
const auto &MMO : State.
MIs[NextID]->memoperands())
1408 OutMIs[InsnID].addMemOperand(MMO);
1416 assert(
MI &&
"Attempted to erase an undefined instruction");
1418 dbgs() << CurrentIdx <<
": GIR_EraseFromParent(MIs["
1419 << InsnID <<
"])\n");
1426 << CurrentIdx <<
": GIR_EraseRootFromParent_Done\n");
1427 eraseImpl(State.
MIs[0]);
1436 MRI.createGenericVirtualRegister(getTypeFromIdx(
TypeID));
1438 dbgs() << CurrentIdx <<
": TempRegs[" << TempRegID
1439 <<
"] = GIR_MakeTempReg(" <<
TypeID <<
")\n");
1449 dbgs() << CurrentIdx <<
": GIR_ReplaceReg(MIs["
1450 << OldInsnID <<
"][" << OldOpIdx <<
"] = MIs["
1451 << NewInsnID <<
"][" << NewOpIdx <<
"])\n");
1453 Register Old = State.
MIs[OldInsnID]->getOperand(OldOpIdx).getReg();
1454 Register New = State.
MIs[NewInsnID]->getOperand(NewOpIdx).getReg();
1457 MRI.replaceRegWith(Old, New);
1468 dbgs() << CurrentIdx <<
": GIR_ReplaceRegWithTempReg(MIs["
1469 << OldInsnID <<
"][" << OldOpIdx <<
"] = TempRegs["
1470 << TempRegID <<
"])\n");
1472 Register Old = State.
MIs[OldInsnID]->getOperand(OldOpIdx).getReg();
1476 MRI.replaceRegWith(Old, New);
1487 <<
": GIR_Coverage("
1494 dbgs() << CurrentIdx <<
": GIR_Done\n");
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
This contains common code to allow clients to notify changes to machine instr.
const HexagonInstrInfo * TII
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
Class for arbitrary precision integers.
void setCovered(uint64_t RuleID)
bool equalsInt(uint64_t V) const
A helper method that can be used to determine if the constant contained within is equal to a constant...
This class represents an Operation in the Expression.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Tagged union holding either a T or a Error.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
virtual bool testSimplePredicate(unsigned) const
bool executeMatchTable(TgtExecutor &Exec, MatcherState &State, const ExecInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ExecInfo, MachineIRBuilder &Builder, const uint8_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage *CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const MatcherState &State) const
virtual bool testImmPredicate_I64(unsigned, int64_t) const
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
static LLVM_ATTRIBUTE_ALWAYS_INLINE uint64_t fastDecodeULEB128(const uint8_t *LLVM_ATTRIBUTE_RESTRICT MatchTable, uint64_t &CurrentIdx)
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI, bool Splat=false) const
virtual void runCustomAction(unsigned, const MatcherState &State, NewMIVector &OutMIs) const
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
CodeGenCoverage * CoverageInfo
Abstract class that contains various methods for clients to notify about changes.
virtual void changingInstr(MachineInstr &MI)=0
This instruction is about to be mutated in some way.
void finishedChangingAllUsesOfReg()
All instructions reported as changing by changingAllUsesOfReg() have finished being changed.
virtual void changedInstr(MachineInstr &MI)=0
This instruction was mutated in some way.
virtual void erasingInstr(MachineInstr &MI)=0
An instruction is about to be erased.
void changingAllUsesOfReg(const MachineRegisterInfo &MRI, Register Reg)
All the instructions using the given register are being changed.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
constexpr unsigned getScalarSizeInBits() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr unsigned getAddressSpace() const
This is an important class for using LLVM in a threaded context.
TypeSize getValue() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
GISelChangeObserver * getObserver()
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Representation of each machine instruction.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
unsigned getAddrSpace() const
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
LocationSize getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
unsigned getPredicate() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
This is an optimization pass for GlobalISel generic memory operations.
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
@ GICXXCustomAction_Invalid
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
@ GIR_AddIntrinsicID
Adds an intrinsic ID to the specified instruction.
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
@ GIR_ReplaceRegWithTempReg
Replaces all references to a register with a temporary register.
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
@ GIM_RootCheckType
GIM_CheckType but InsnID is omitted and defaults to zero.
@ GIM_RootCheckRegBankForClass
GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
@ GIR_Done
A successful emission.
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
@ GIR_RootConstrainSelectedInstOperands
GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to zero.
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
@ GIR_AddCImm
Add an CImm to the specified instruction.
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
@ GIM_CheckHasNoUse
Check if there's no use of the first result.
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
@ GIR_EraseFromParent
Erase from parent.
@ GIR_CustomAction
Calls a C++ function to perform an action when a match is complete.
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
@ GIR_CopySubReg
Copy an operand to the specified instruction.
@ GIR_MutateOpcode
Mutate an instruction.
@ GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckAtomicOrderingOrStrongerThan
@ GIR_AddRegister
Add an register to the specified instruction.
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
@ GIM_CheckIsSafeToFold
Checks if the matched instructions numbered [1, 1+N) can be folded into the root (inst 0).
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
@ GIR_ReplaceReg
Replaces all references to a register from an instruction with another register from another instruct...
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
@ GIR_AddSimpleTempRegister
Add a temporary register to the specified instruction without setting any flags.
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
@ GIR_Copy
Copy an operand to the specified instruction.
@ GIR_AddImm
Add an immediate to the specified instruction.
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
@ GIM_MIFlags
Check that a matched instruction has, or doesn't have a MIFlag.
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
@ GIR_AddImm8
Add signed 8 bit immediate to the specified instruction.
@ GIM_CheckIsSameOperandIgnoreCopies
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
@ GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
@ GIM_CheckMemorySizeLessThanLLT
@ GIM_RecordRegType
Records an operand's register type into the set of temporary types.
@ GIR_EraseRootFromParent_Done
Combines both a GIR_EraseFromParent 0 + GIR_Done.
@ GIR_CopyMIFlags
Copy the MIFlags of a matched instruction into an output instruction.
@ GIR_BuildMI
Build a new instruction.
@ GIM_RecordInsn
Record the specified instruction.
@ GIM_CheckIsImm
Check the specified operand is an Imm.
@ GIR_BuildRootMI
GIR_BuildMI but InsnID is omitted and defaults to zero.
@ GIM_CheckFeatures
Check the feature bits Feature(2) - Expected features.
@ GIM_CheckCanReplaceReg
Check we can replace all uses of a register with another.
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
@ GIM_CheckType
Check the type for the specified operand.
@ GIM_CheckConstantInt8
Check the operand is a specific 8-bit signed integer.
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
@ GIR_SetImplicitDefDead
Marks the implicit def of a register as dead.
@ GIR_BuildConstant
Builds a constant and stores its result in a TempReg.
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
@ GIR_Coverage
Increment the rule coverage counter.
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
@ GIM_CheckAtomicOrderingWeakerThan
@ GIR_SetMIFlags
Set or unset a MIFlag on an instruction.
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
@ GIM_CheckConstantInt
Check the operand is a specific integer.
@ GIR_RootToRootCopy
GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
@ GIR_ComplexSubOperandSubRegRenderer
Render subregisters of suboperands of complex operands to the specified instruction.
@ GIM_RecordInsnIgnoreCopies
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
@ GIM_CheckSimplePredicate
Check a trivial predicate which takes no arguments.
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isAtLeastOrStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
AtomicOrdering
Atomic ordering for LLVM's memory model.
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
@ Default
The result values are uniform if and only if all operands are uniform.
bool isStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
Returns true if ao is stronger than other as defined by the AtomicOrdering lattice,...
const CustomRendererFn * CustomRenderers
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
const ComplexMatcherMemFn * ComplexPredicates
const PredicateBitset * FeatureBitsets
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
SmallVector< LLT, 4 > RecordedTypes
Types extracted from an instruction's operand.
DenseMap< unsigned, unsigned > TempRegisters
std::vector< ComplexRendererFns::value_type > Renderers