18#include "llvm/Config/llvm-config.h"
40#include <mach/host_info.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
45#include <sys/sysctl.h>
48#include <sys/systemcfg.h>
50#if defined(__sun__) && defined(__svr4__)
54#define DEBUG_TYPE "host-detection"
64static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC = Text.getError()) {
70 <<
"/proc/cpuinfo: " << EC.message() <<
"\n";
73 return std::move(*Text);
80 const char *
generic =
"generic";
94 while (CIP < CPUInfoEnd && CPUStart ==
nullptr) {
95 if (CIP < CPUInfoEnd && *CIP ==
'\n')
98 if (CIP < CPUInfoEnd && *CIP ==
'c') {
100 if (CIP < CPUInfoEnd && *CIP ==
'p') {
102 if (CIP < CPUInfoEnd && *CIP ==
'u') {
104 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
107 if (CIP < CPUInfoEnd && *CIP ==
':') {
109 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
112 if (CIP < CPUInfoEnd) {
114 while (CIP < CPUInfoEnd && (*CIP !=
' ' && *CIP !=
'\t' &&
115 *CIP !=
',' && *CIP !=
'\n'))
117 CPULen = CIP - CPUStart;
124 if (CPUStart ==
nullptr)
125 while (CIP < CPUInfoEnd && *CIP !=
'\n')
129 if (CPUStart ==
nullptr)
133 .
Case(
"604e",
"604e")
135 .
Case(
"7400",
"7400")
136 .
Case(
"7410",
"7400")
137 .
Case(
"7447",
"7400")
138 .
Case(
"7455",
"7450")
140 .
Case(
"POWER4",
"970")
141 .
Case(
"PPC970FX",
"970")
142 .
Case(
"PPC970MP",
"970")
144 .
Case(
"POWER5",
"g5")
146 .
Case(
"POWER6",
"pwr6")
147 .
Case(
"POWER7",
"pwr7")
148 .
Case(
"POWER8",
"pwr8")
149 .
Case(
"POWER8E",
"pwr8")
150 .
Case(
"POWER8NVL",
"pwr8")
151 .
Case(
"POWER9",
"pwr9")
152 .
Case(
"POWER10",
"pwr10")
166 ProcCpuinfoContent.
split(Lines,
"\n");
172 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
174 Implementer = Lines[
I].substr(15).ltrim(
"\t :");
176 Hardware = Lines[
I].substr(8).ltrim(
"\t :");
178 Part = Lines[
I].substr(8).ltrim(
"\t :");
181 if (Implementer ==
"0x41") {
194 .
Case(
"0x926",
"arm926ej-s")
195 .
Case(
"0xb02",
"mpcore")
196 .
Case(
"0xb36",
"arm1136j-s")
197 .
Case(
"0xb56",
"arm1156t2-s")
198 .
Case(
"0xb76",
"arm1176jz-s")
199 .
Case(
"0xc05",
"cortex-a5")
200 .
Case(
"0xc07",
"cortex-a7")
201 .
Case(
"0xc08",
"cortex-a8")
202 .
Case(
"0xc09",
"cortex-a9")
203 .
Case(
"0xc0f",
"cortex-a15")
204 .
Case(
"0xc0e",
"cortex-a17")
205 .
Case(
"0xc20",
"cortex-m0")
206 .
Case(
"0xc23",
"cortex-m3")
207 .
Case(
"0xc24",
"cortex-m4")
208 .
Case(
"0xc27",
"cortex-m7")
209 .
Case(
"0xd20",
"cortex-m23")
210 .
Case(
"0xd21",
"cortex-m33")
211 .
Case(
"0xd24",
"cortex-m52")
212 .
Case(
"0xd22",
"cortex-m55")
213 .
Case(
"0xd23",
"cortex-m85")
214 .
Case(
"0xc18",
"cortex-r8")
215 .
Case(
"0xd13",
"cortex-r52")
216 .
Case(
"0xd15",
"cortex-r82")
217 .
Case(
"0xd14",
"cortex-r82ae")
218 .
Case(
"0xd02",
"cortex-a34")
219 .
Case(
"0xd04",
"cortex-a35")
220 .
Case(
"0xd03",
"cortex-a53")
221 .
Case(
"0xd05",
"cortex-a55")
222 .
Case(
"0xd46",
"cortex-a510")
223 .
Case(
"0xd80",
"cortex-a520")
224 .
Case(
"0xd88",
"cortex-a520ae")
225 .
Case(
"0xd07",
"cortex-a57")
226 .
Case(
"0xd06",
"cortex-a65")
227 .
Case(
"0xd43",
"cortex-a65ae")
228 .
Case(
"0xd08",
"cortex-a72")
229 .
Case(
"0xd09",
"cortex-a73")
230 .
Case(
"0xd0a",
"cortex-a75")
231 .
Case(
"0xd0b",
"cortex-a76")
232 .
Case(
"0xd0e",
"cortex-a76ae")
233 .
Case(
"0xd0d",
"cortex-a77")
234 .
Case(
"0xd41",
"cortex-a78")
235 .
Case(
"0xd42",
"cortex-a78ae")
236 .
Case(
"0xd4b",
"cortex-a78c")
237 .
Case(
"0xd47",
"cortex-a710")
238 .
Case(
"0xd4d",
"cortex-a715")
239 .
Case(
"0xd81",
"cortex-a720")
240 .
Case(
"0xd89",
"cortex-a720ae")
241 .
Case(
"0xd44",
"cortex-x1")
242 .
Case(
"0xd4c",
"cortex-x1c")
243 .
Case(
"0xd48",
"cortex-x2")
244 .
Case(
"0xd4e",
"cortex-x3")
245 .
Case(
"0xd82",
"cortex-x4")
246 .
Case(
"0xd4a",
"neoverse-e1")
247 .
Case(
"0xd0c",
"neoverse-n1")
248 .
Case(
"0xd49",
"neoverse-n2")
249 .
Case(
"0xd8e",
"neoverse-n3")
250 .
Case(
"0xd40",
"neoverse-v1")
251 .
Case(
"0xd4f",
"neoverse-v2")
252 .
Case(
"0xd84",
"neoverse-v3")
253 .
Case(
"0xd83",
"neoverse-v3ae")
257 if (Implementer ==
"0x42" || Implementer ==
"0x43") {
259 .
Case(
"0x516",
"thunderx2t99")
260 .
Case(
"0x0516",
"thunderx2t99")
261 .
Case(
"0xaf",
"thunderx2t99")
262 .
Case(
"0x0af",
"thunderx2t99")
263 .
Case(
"0xa1",
"thunderxt88")
264 .
Case(
"0x0a1",
"thunderxt88")
268 if (Implementer ==
"0x46") {
270 .
Case(
"0x001",
"a64fx")
274 if (Implementer ==
"0x4e") {
276 .
Case(
"0x004",
"carmel")
280 if (Implementer ==
"0x48")
285 .
Case(
"0xd01",
"tsv110")
288 if (Implementer ==
"0x51")
293 .
Case(
"0x06f",
"krait")
294 .
Case(
"0x201",
"kryo")
295 .
Case(
"0x205",
"kryo")
296 .
Case(
"0x211",
"kryo")
297 .
Case(
"0x800",
"cortex-a73")
298 .
Case(
"0x801",
"cortex-a73")
299 .
Case(
"0x802",
"cortex-a75")
300 .
Case(
"0x803",
"cortex-a75")
301 .
Case(
"0x804",
"cortex-a76")
302 .
Case(
"0x805",
"cortex-a76")
303 .
Case(
"0xc00",
"falkor")
304 .
Case(
"0xc01",
"saphira")
306 if (Implementer ==
"0x53") {
309 unsigned Variant = 0, Part = 0;
314 if (
I.consume_front(
"CPU variant"))
315 I.ltrim(
"\t :").getAsInteger(0, Variant);
320 if (
I.consume_front(
"CPU part"))
321 I.ltrim(
"\t :").getAsInteger(0, Part);
323 unsigned Exynos = (Variant << 12) | Part;
335 if (Implementer ==
"0x6d") {
338 .
Case(
"0xd49",
"neoverse-n2")
342 if (Implementer ==
"0xc0") {
344 .
Case(
"0xac3",
"ampere1")
345 .
Case(
"0xac4",
"ampere1a")
346 .
Case(
"0xac5",
"ampere1b")
354StringRef getCPUNameFromS390Model(
unsigned int Id,
bool HaveVectorSupport) {
374 return HaveVectorSupport?
"z13" :
"zEC12";
377 return HaveVectorSupport?
"z14" :
"zEC12";
380 return HaveVectorSupport?
"z15" :
"zEC12";
384 return HaveVectorSupport?
"z16" :
"zEC12";
395 ProcCpuinfoContent.
split(Lines,
"\n");
399 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I)
401 size_t Pos = Lines[
I].find(
':');
403 Lines[
I].drop_front(Pos + 1).split(CPUFeatures,
' ');
411 bool HaveVectorSupport =
false;
412 for (
unsigned I = 0, E = CPUFeatures.size();
I != E; ++
I) {
413 if (CPUFeatures[
I] ==
"vx")
414 HaveVectorSupport =
true;
418 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
420 size_t Pos = Lines[
I].find(
"machine = ");
422 Pos +=
sizeof(
"machine = ") - 1;
424 if (!Lines[
I].drop_front(Pos).getAsInteger(10, Id))
425 return getCPUNameFromS390Model(Id, HaveVectorSupport);
437 ProcCpuinfoContent.
split(Lines,
"\n");
441 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
443 UArch = Lines[
I].substr(5).ltrim(
"\t :");
449 .
Case(
"sifive,u74-mc",
"sifive-u74")
450 .
Case(
"sifive,bullet0",
"sifive-u74")
455#if !defined(__linux__) || !defined(__x86_64__)
458 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
460 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
462 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
464 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
466 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
468 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
470 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
472 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
474 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
476 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
478 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
480 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
482 struct bpf_prog_load_attr {
498 int fd = syscall(321 , 5 , &attr,
506 memset(&attr, 0,
sizeof(attr));
511 fd = syscall(321 , 5 , &attr,
sizeof(attr));
520#if defined(__i386__) || defined(_M_IX86) || \
521 defined(__x86_64__) || defined(_M_X64)
530static bool isCpuIdSupported() {
531#if defined(__GNUC__) || defined(__clang__)
533 int __cpuid_supported;
536 " movl %%eax,%%ecx\n"
537 " xorl $0x00200000,%%eax\n"
543 " cmpl %%eax,%%ecx\n"
547 :
"=r"(__cpuid_supported)
550 if (!__cpuid_supported)
560static bool getX86CpuIDAndInfo(
unsigned value,
unsigned *rEAX,
unsigned *rEBX,
561 unsigned *rECX,
unsigned *rEDX) {
562#if defined(__GNUC__) || defined(__clang__)
563#if defined(__x86_64__)
566 __asm__(
"movq\t%%rbx, %%rsi\n\t"
568 "xchgq\t%%rbx, %%rsi\n\t"
569 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
572#elif defined(__i386__)
573 __asm__(
"movl\t%%ebx, %%esi\n\t"
575 "xchgl\t%%ebx, %%esi\n\t"
576 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
582#elif defined(_MSC_VER)
585 __cpuid(registers,
value);
586 *rEAX = registers[0];
587 *rEBX = registers[1];
588 *rECX = registers[2];
589 *rEDX = registers[3];
601VendorSignatures getVendorSignature(
unsigned *MaxLeaf) {
602 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
603 if (MaxLeaf ==
nullptr)
608 if (!isCpuIdSupported())
609 return VendorSignatures::UNKNOWN;
611 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
612 return VendorSignatures::UNKNOWN;
615 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
616 return VendorSignatures::GENUINE_INTEL;
619 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
620 return VendorSignatures::AUTHENTIC_AMD;
622 return VendorSignatures::UNKNOWN;
635static bool getX86CpuIDAndInfoEx(
unsigned value,
unsigned subleaf,
636 unsigned *rEAX,
unsigned *rEBX,
unsigned *rECX,
638#if defined(__GNUC__) || defined(__clang__)
639#if defined(__x86_64__)
642 __asm__(
"movq\t%%rbx, %%rsi\n\t"
644 "xchgq\t%%rbx, %%rsi\n\t"
645 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
646 :
"a"(
value),
"c"(subleaf));
648#elif defined(__i386__)
649 __asm__(
"movl\t%%ebx, %%esi\n\t"
651 "xchgl\t%%ebx, %%esi\n\t"
652 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
653 :
"a"(
value),
"c"(subleaf));
658#elif defined(_MSC_VER)
660 __cpuidex(registers,
value, subleaf);
661 *rEAX = registers[0];
662 *rEBX = registers[1];
663 *rECX = registers[2];
664 *rEDX = registers[3];
672static bool getX86XCR0(
unsigned *rEAX,
unsigned *rEDX) {
673#if defined(__GNUC__) || defined(__clang__)
677 __asm__(
".byte 0x0f, 0x01, 0xd0" :
"=a"(*rEAX),
"=d"(*rEDX) :
"c"(0));
679#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
680 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
689static void detectX86FamilyModel(
unsigned EAX,
unsigned *Family,
691 *Family = (
EAX >> 8) & 0xf;
693 if (*Family == 6 || *Family == 0xf) {
696 *Family += (
EAX >> 20) & 0xff;
703getIntelProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
704 const unsigned *Features,
705 unsigned *
Type,
unsigned *Subtype) {
706 auto testFeature = [&](
unsigned F) {
707 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
720 if (testFeature(X86::FEATURE_MMX)) {
736 *
Type = X86::INTEL_CORE2;
745 *
Type = X86::INTEL_CORE2;
754 *
Type = X86::INTEL_COREI7;
755 *Subtype = X86::INTEL_COREI7_NEHALEM;
762 *
Type = X86::INTEL_COREI7;
763 *Subtype = X86::INTEL_COREI7_WESTMERE;
769 *
Type = X86::INTEL_COREI7;
770 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
775 *
Type = X86::INTEL_COREI7;
776 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
785 *
Type = X86::INTEL_COREI7;
786 *Subtype = X86::INTEL_COREI7_HASWELL;
795 *
Type = X86::INTEL_COREI7;
796 *Subtype = X86::INTEL_COREI7_BROADWELL;
807 *
Type = X86::INTEL_COREI7;
808 *Subtype = X86::INTEL_COREI7_SKYLAKE;
814 *
Type = X86::INTEL_COREI7;
815 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
820 *
Type = X86::INTEL_COREI7;
821 if (testFeature(X86::FEATURE_AVX512BF16)) {
823 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
824 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
826 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
828 CPU =
"skylake-avx512";
829 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
836 *
Type = X86::INTEL_COREI7;
837 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
843 CPU =
"icelake-client";
844 *
Type = X86::INTEL_COREI7;
845 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
852 *
Type = X86::INTEL_COREI7;
853 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
869 *
Type = X86::INTEL_COREI7;
870 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
876 *
Type = X86::INTEL_COREI7;
877 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
885 *
Type = X86::INTEL_COREI7;
886 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
892 *
Type = X86::INTEL_COREI7;
893 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
898 CPU =
"graniterapids";
899 *
Type = X86::INTEL_COREI7;
900 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
905 CPU =
"graniterapids-d";
906 *
Type = X86::INTEL_COREI7;
907 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
913 CPU =
"icelake-server";
914 *
Type = X86::INTEL_COREI7;
915 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
922 CPU =
"sapphirerapids";
923 *
Type = X86::INTEL_COREI7;
924 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
933 *
Type = X86::INTEL_BONNELL;
944 *
Type = X86::INTEL_SILVERMONT;
950 *
Type = X86::INTEL_GOLDMONT;
953 CPU =
"goldmont-plus";
954 *
Type = X86::INTEL_GOLDMONT_PLUS;
961 *
Type = X86::INTEL_TREMONT;
966 CPU =
"sierraforest";
967 *
Type = X86::INTEL_SIERRAFOREST;
973 *
Type = X86::INTEL_GRANDRIDGE;
978 CPU =
"clearwaterforest";
979 *
Type = X86::INTEL_CLEARWATERFOREST;
985 *
Type = X86::INTEL_KNL;
989 *
Type = X86::INTEL_KNM;
996 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
998 }
else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
999 CPU =
"icelake-client";
1000 }
else if (testFeature(X86::FEATURE_AVX512VBMI)) {
1002 }
else if (testFeature(X86::FEATURE_AVX512BF16)) {
1004 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
1005 CPU =
"cascadelake";
1006 }
else if (testFeature(X86::FEATURE_AVX512VL)) {
1007 CPU =
"skylake-avx512";
1008 }
else if (testFeature(X86::FEATURE_AVX512ER)) {
1010 }
else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
1011 if (testFeature(X86::FEATURE_SHA))
1015 }
else if (testFeature(X86::FEATURE_ADX)) {
1017 }
else if (testFeature(X86::FEATURE_AVX2)) {
1019 }
else if (testFeature(X86::FEATURE_AVX)) {
1020 CPU =
"sandybridge";
1021 }
else if (testFeature(X86::FEATURE_SSE4_2)) {
1022 if (testFeature(X86::FEATURE_MOVBE))
1026 }
else if (testFeature(X86::FEATURE_SSE4_1)) {
1028 }
else if (testFeature(X86::FEATURE_SSSE3)) {
1029 if (testFeature(X86::FEATURE_MOVBE))
1033 }
else if (testFeature(X86::FEATURE_64BIT)) {
1035 }
else if (testFeature(X86::FEATURE_SSE3)) {
1037 }
else if (testFeature(X86::FEATURE_SSE2)) {
1039 }
else if (testFeature(X86::FEATURE_SSE)) {
1041 }
else if (testFeature(X86::FEATURE_MMX)) {
1050 if (testFeature(X86::FEATURE_64BIT)) {
1054 if (testFeature(X86::FEATURE_SSE3)) {
1069getAMDProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
1070 const unsigned *Features,
1071 unsigned *
Type,
unsigned *Subtype) {
1072 auto testFeature = [&](
unsigned F) {
1073 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
1102 if (testFeature(X86::FEATURE_SSE)) {
1109 if (testFeature(X86::FEATURE_SSE3)) {
1117 *
Type = X86::AMDFAM10H;
1120 *Subtype = X86::AMDFAM10H_BARCELONA;
1123 *Subtype = X86::AMDFAM10H_SHANGHAI;
1126 *Subtype = X86::AMDFAM10H_ISTANBUL;
1132 *
Type = X86::AMD_BTVER1;
1136 *
Type = X86::AMDFAM15H;
1137 if (Model >= 0x60 && Model <= 0x7f) {
1139 *Subtype = X86::AMDFAM15H_BDVER4;
1142 if (Model >= 0x30 && Model <= 0x3f) {
1144 *Subtype = X86::AMDFAM15H_BDVER3;
1147 if ((Model >= 0x10 && Model <= 0x1f) ||
Model == 0x02) {
1149 *Subtype = X86::AMDFAM15H_BDVER2;
1152 if (Model <= 0x0f) {
1153 *Subtype = X86::AMDFAM15H_BDVER1;
1159 *
Type = X86::AMD_BTVER2;
1163 *
Type = X86::AMDFAM17H;
1164 if ((Model >= 0x30 && Model <= 0x3f) || (
Model == 0x47) ||
1165 (Model >= 0x60 && Model <= 0x67) || (
Model >= 0x68 &&
Model <= 0x6f) ||
1166 (Model >= 0x70 && Model <= 0x7f) || (
Model >= 0x84 &&
Model <= 0x87) ||
1167 (Model >= 0x90 && Model <= 0x97) || (
Model >= 0x98 &&
Model <= 0x9f) ||
1168 (Model >= 0xa0 && Model <= 0xaf)) {
1179 *Subtype = X86::AMDFAM17H_ZNVER2;
1182 if ((Model >= 0x10 && Model <= 0x1f) || (
Model >= 0x20 &&
Model <= 0x2f)) {
1186 *Subtype = X86::AMDFAM17H_ZNVER1;
1192 *
Type = X86::AMDFAM19H;
1193 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||
1194 (
Model >= 0x30 &&
Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||
1201 *Subtype = X86::AMDFAM19H_ZNVER3;
1204 if ((Model >= 0x10 && Model <= 0x1f) || (
Model >= 0x60 &&
Model <= 0x6f) ||
1205 (Model >= 0x70 && Model <= 0x77) || (
Model >= 0x78 &&
Model <= 0x7f) ||
1206 (Model >= 0xa0 && Model <= 0xaf)) {
1213 *Subtype = X86::AMDFAM19H_ZNVER4;
1224static void getAvailableFeatures(
unsigned ECX,
unsigned EDX,
unsigned MaxLeaf,
1225 unsigned *Features) {
1228 auto setFeature = [&](
unsigned F) {
1229 Features[
F / 32] |= 1U << (
F % 32);
1232 if ((EDX >> 15) & 1)
1233 setFeature(X86::FEATURE_CMOV);
1234 if ((EDX >> 23) & 1)
1235 setFeature(X86::FEATURE_MMX);
1236 if ((EDX >> 25) & 1)
1237 setFeature(X86::FEATURE_SSE);
1238 if ((EDX >> 26) & 1)
1239 setFeature(X86::FEATURE_SSE2);
1242 setFeature(X86::FEATURE_SSE3);
1244 setFeature(X86::FEATURE_PCLMUL);
1246 setFeature(X86::FEATURE_SSSE3);
1247 if ((ECX >> 12) & 1)
1248 setFeature(X86::FEATURE_FMA);
1249 if ((ECX >> 19) & 1)
1250 setFeature(X86::FEATURE_SSE4_1);
1251 if ((ECX >> 20) & 1) {
1252 setFeature(X86::FEATURE_SSE4_2);
1253 setFeature(X86::FEATURE_CRC32);
1255 if ((ECX >> 23) & 1)
1256 setFeature(X86::FEATURE_POPCNT);
1257 if ((ECX >> 25) & 1)
1258 setFeature(X86::FEATURE_AES);
1260 if ((ECX >> 22) & 1)
1261 setFeature(X86::FEATURE_MOVBE);
1266 const unsigned AVXBits = (1 << 27) | (1 << 28);
1267 bool HasAVX = ((
ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1268 ((
EAX & 0x6) == 0x6);
1269#if defined(__APPLE__)
1273 bool HasAVX512Save =
true;
1276 bool HasAVX512Save = HasAVX && ((
EAX & 0xe0) == 0xe0);
1280 setFeature(X86::FEATURE_AVX);
1283 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1285 if (HasLeaf7 && ((EBX >> 3) & 1))
1286 setFeature(X86::FEATURE_BMI);
1287 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1288 setFeature(X86::FEATURE_AVX2);
1289 if (HasLeaf7 && ((EBX >> 8) & 1))
1290 setFeature(X86::FEATURE_BMI2);
1291 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) {
1292 setFeature(X86::FEATURE_AVX512F);
1293 setFeature(X86::FEATURE_EVEX512);
1295 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1296 setFeature(X86::FEATURE_AVX512DQ);
1297 if (HasLeaf7 && ((EBX >> 19) & 1))
1298 setFeature(X86::FEATURE_ADX);
1299 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1300 setFeature(X86::FEATURE_AVX512IFMA);
1301 if (HasLeaf7 && ((EBX >> 23) & 1))
1302 setFeature(X86::FEATURE_CLFLUSHOPT);
1303 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1304 setFeature(X86::FEATURE_AVX512PF);
1305 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1306 setFeature(X86::FEATURE_AVX512ER);
1307 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1308 setFeature(X86::FEATURE_AVX512CD);
1309 if (HasLeaf7 && ((EBX >> 29) & 1))
1310 setFeature(X86::FEATURE_SHA);
1311 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1312 setFeature(X86::FEATURE_AVX512BW);
1313 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1314 setFeature(X86::FEATURE_AVX512VL);
1316 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1317 setFeature(X86::FEATURE_AVX512VBMI);
1318 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1319 setFeature(X86::FEATURE_AVX512VBMI2);
1320 if (HasLeaf7 && ((ECX >> 8) & 1))
1321 setFeature(X86::FEATURE_GFNI);
1322 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1323 setFeature(X86::FEATURE_VPCLMULQDQ);
1324 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1325 setFeature(X86::FEATURE_AVX512VNNI);
1326 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1327 setFeature(X86::FEATURE_AVX512BITALG);
1328 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1329 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1331 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1332 setFeature(X86::FEATURE_AVX5124VNNIW);
1333 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1334 setFeature(X86::FEATURE_AVX5124FMAPS);
1335 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1336 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1340 bool HasLeaf7Subleaf1 =
1341 HasLeaf7 &&
EAX >= 1 &&
1342 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1343 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1344 setFeature(X86::FEATURE_AVX512BF16);
1346 unsigned MaxExtLevel;
1347 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1349 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1350 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1351 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1352 setFeature(X86::FEATURE_SSE4_A);
1353 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1354 setFeature(X86::FEATURE_XOP);
1355 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1356 setFeature(X86::FEATURE_FMA4);
1358 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1359 setFeature(X86::FEATURE_64BIT);
1363 unsigned MaxLeaf = 0;
1365 if (Vendor == VendorSignatures::UNKNOWN)
1369 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1371 unsigned Family = 0,
Model = 0;
1373 detectX86FamilyModel(EAX, &Family, &Model);
1374 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1379 unsigned Subtype = 0;
1383 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1384 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1386 }
else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1387 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1397#elif defined(__APPLE__) && defined(__powerpc__)
1399 host_basic_info_data_t hostInfo;
1400 mach_msg_type_number_t infoCount;
1402 infoCount = HOST_BASIC_INFO_COUNT;
1403 mach_port_t hostPort = mach_host_self();
1404 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1406 mach_port_deallocate(mach_task_self(), hostPort);
1408 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1411 switch (hostInfo.cpu_subtype) {
1441#elif defined(__linux__) && defined(__powerpc__)
1445 return detail::getHostCPUNameForPowerPC(
Content);
1447#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1451 return detail::getHostCPUNameForARM(
Content);
1453#elif defined(__linux__) && defined(__s390x__)
1457 return detail::getHostCPUNameForS390x(
Content);
1459#elif defined(__MVS__)
1464 int *StartToCVTOffset =
reinterpret_cast<int *
>(0x10);
1467 int ReadValue = *StartToCVTOffset;
1469 ReadValue = (ReadValue & 0x7FFFFFFF);
1470 char *CVT =
reinterpret_cast<char *
>(ReadValue);
1475 Id = decodePackedBCD<uint16_t>(Id,
false);
1479 bool HaveVectorSupport = CVT[244] & 0x80;
1480 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1482#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1483#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1484#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1485#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1486#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1487#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1488#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1489#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1490#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1491#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1492#define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d
1493#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
1497 size_t Length =
sizeof(Family);
1498 sysctlbyname(
"hw.cpufamily", &Family, &
Length, NULL, 0);
1501 case CPUFAMILY_ARM_SWIFT:
1503 case CPUFAMILY_ARM_CYCLONE:
1505 case CPUFAMILY_ARM_TYPHOON:
1507 case CPUFAMILY_ARM_TWISTER:
1509 case CPUFAMILY_ARM_HURRICANE:
1511 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1513 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1515 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1517 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1519 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE:
1521 case CPUFAMILY_ARM_EVEREST_SAWTOOTH:
1530 switch (_system_configuration.implementation) {
1532 if (_system_configuration.version == PV_4_3)
1536 if (_system_configuration.version == PV_5)
1540 if (_system_configuration.version == PV_6_Compat)
1560#elif defined(__loongarch__)
1564 __asm__(
"cpucfg %[prid], $zero\n\t" : [prid]
"=r"(processor_id));
1566 switch (processor_id & 0xf000) {
1575#elif defined(__riscv)
1577#if defined(__linux__)
1580 return detail::getHostCPUNameForRISCV(
Content);
1582#if __riscv_xlen == 64
1583 return "generic-rv64";
1584#elif __riscv_xlen == 32
1585 return "generic-rv32";
1587#error "Unhandled value of __riscv_xlen"
1591#elif defined(__sparc__)
1592#if defined(__linux__)
1595 ProcCpuinfoContent.
split(Lines,
"\n");
1599 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I) {
1601 Cpu =
Lines[
I].substr(5).ltrim(
"\t :");
1633#if defined(__linux__)
1636 return detail::getHostCPUNameForSPARC(
Content);
1637#elif defined(__sun__) && defined(__svr4__)
1641 kstat_named_t *brand = NULL;
1645 ksp = kstat_lookup(kc,
const_cast<char *
>(
"cpu_info"), -1, NULL);
1646 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1647 ksp->ks_type == KSTAT_TYPE_NAMED)
1649 (kstat_named_t *)kstat_data_lookup(ksp,
const_cast<char *
>(
"brand"));
1650 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1651 buf = KSTAT_NAMED_STR_PTR(brand);
1656 .
Case(
"TMS390S10",
"supersparc")
1657 .
Case(
"TMS390Z50",
"supersparc")
1660 .
Case(
"MB86904",
"supersparc")
1661 .
Case(
"MB86907",
"supersparc")
1662 .
Case(
"RT623",
"hypersparc")
1663 .
Case(
"RT625",
"hypersparc")
1664 .
Case(
"RT626",
"hypersparc")
1665 .
Case(
"UltraSPARC-I",
"ultrasparc")
1666 .
Case(
"UltraSPARC-II",
"ultrasparc")
1667 .
Case(
"UltraSPARC-IIe",
"ultrasparc")
1668 .
Case(
"UltraSPARC-IIi",
"ultrasparc")
1669 .
Case(
"SPARC64-III",
"ultrasparc")
1670 .
Case(
"SPARC64-IV",
"ultrasparc")
1671 .
Case(
"UltraSPARC-III",
"ultrasparc3")
1672 .
Case(
"UltraSPARC-III+",
"ultrasparc3")
1673 .
Case(
"UltraSPARC-IIIi",
"ultrasparc3")
1674 .
Case(
"UltraSPARC-IIIi+",
"ultrasparc3")
1675 .
Case(
"UltraSPARC-IV",
"ultrasparc3")
1676 .
Case(
"UltraSPARC-IV+",
"ultrasparc3")
1677 .
Case(
"SPARC64-V",
"ultrasparc3")
1678 .
Case(
"SPARC64-VI",
"ultrasparc3")
1679 .
Case(
"SPARC64-VII",
"ultrasparc3")
1680 .
Case(
"UltraSPARC-T1",
"niagara")
1681 .
Case(
"UltraSPARC-T2",
"niagara2")
1682 .
Case(
"UltraSPARC-T2",
"niagara2")
1683 .
Case(
"UltraSPARC-T2+",
"niagara2")
1684 .
Case(
"SPARC-T3",
"niagara3")
1685 .
Case(
"SPARC-T4",
"niagara4")
1686 .
Case(
"SPARC-T5",
"niagara4")
1688 .
Case(
"SPARC-M7",
"niagara4" )
1689 .
Case(
"SPARC-S7",
"niagara4" )
1690 .
Case(
"SPARC-M8",
"niagara4" )
1713#if defined(__i386__) || defined(_M_IX86) || \
1714 defined(__x86_64__) || defined(_M_X64)
1719 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1722 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1724 Features[
"cx8"] = (
EDX >> 8) & 1;
1725 Features[
"cmov"] = (
EDX >> 15) & 1;
1726 Features[
"mmx"] = (
EDX >> 23) & 1;
1727 Features[
"fxsr"] = (
EDX >> 24) & 1;
1728 Features[
"sse"] = (
EDX >> 25) & 1;
1729 Features[
"sse2"] = (
EDX >> 26) & 1;
1731 Features[
"sse3"] = (
ECX >> 0) & 1;
1732 Features[
"pclmul"] = (
ECX >> 1) & 1;
1733 Features[
"ssse3"] = (
ECX >> 9) & 1;
1734 Features[
"cx16"] = (
ECX >> 13) & 1;
1735 Features[
"sse4.1"] = (
ECX >> 19) & 1;
1736 Features[
"sse4.2"] = (
ECX >> 20) & 1;
1737 Features[
"crc32"] = Features[
"sse4.2"];
1738 Features[
"movbe"] = (
ECX >> 22) & 1;
1739 Features[
"popcnt"] = (
ECX >> 23) & 1;
1740 Features[
"aes"] = (
ECX >> 25) & 1;
1741 Features[
"rdrnd"] = (
ECX >> 30) & 1;
1746 bool HasXSave = ((
ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1747 bool HasAVXSave = HasXSave && ((
ECX >> 28) & 1) && ((
EAX & 0x6) == 0x6);
1748#if defined(__APPLE__)
1752 bool HasAVX512Save =
true;
1755 bool HasAVX512Save = HasAVXSave && ((
EAX & 0xe0) == 0xe0);
1758 const unsigned AMXBits = (1 << 17) | (1 << 18);
1759 bool HasAMXSave = HasXSave && ((
EAX & AMXBits) == AMXBits);
1761 Features[
"avx"] = HasAVXSave;
1762 Features[
"fma"] = ((
ECX >> 12) & 1) && HasAVXSave;
1764 Features[
"xsave"] = ((
ECX >> 26) & 1) && HasAVXSave;
1765 Features[
"f16c"] = ((
ECX >> 29) & 1) && HasAVXSave;
1767 unsigned MaxExtLevel;
1768 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1770 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1771 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1772 Features[
"sahf"] = HasExtLeaf1 && ((
ECX >> 0) & 1);
1773 Features[
"lzcnt"] = HasExtLeaf1 && ((
ECX >> 5) & 1);
1774 Features[
"sse4a"] = HasExtLeaf1 && ((
ECX >> 6) & 1);
1775 Features[
"prfchw"] = HasExtLeaf1 && ((
ECX >> 8) & 1);
1776 Features[
"xop"] = HasExtLeaf1 && ((
ECX >> 11) & 1) && HasAVXSave;
1777 Features[
"lwp"] = HasExtLeaf1 && ((
ECX >> 15) & 1);
1778 Features[
"fma4"] = HasExtLeaf1 && ((
ECX >> 16) & 1) && HasAVXSave;
1779 Features[
"tbm"] = HasExtLeaf1 && ((
ECX >> 21) & 1);
1780 Features[
"mwaitx"] = HasExtLeaf1 && ((
ECX >> 29) & 1);
1782 Features[
"64bit"] = HasExtLeaf1 && ((
EDX >> 29) & 1);
1786 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1787 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1788 Features[
"clzero"] = HasExtLeaf8 && ((
EBX >> 0) & 1);
1789 Features[
"rdpru"] = HasExtLeaf8 && ((
EBX >> 4) & 1);
1790 Features[
"wbnoinvd"] = HasExtLeaf8 && ((
EBX >> 9) & 1);
1793 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1795 Features[
"fsgsbase"] = HasLeaf7 && ((
EBX >> 0) & 1);
1796 Features[
"sgx"] = HasLeaf7 && ((
EBX >> 2) & 1);
1797 Features[
"bmi"] = HasLeaf7 && ((
EBX >> 3) & 1);
1799 Features[
"avx2"] = HasLeaf7 && ((
EBX >> 5) & 1) && HasAVXSave;
1800 Features[
"bmi2"] = HasLeaf7 && ((
EBX >> 8) & 1);
1801 Features[
"invpcid"] = HasLeaf7 && ((
EBX >> 10) & 1);
1802 Features[
"rtm"] = HasLeaf7 && ((
EBX >> 11) & 1);
1804 Features[
"avx512f"] = HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save;
1805 Features[
"evex512"] = Features[
"avx512f"];
1806 Features[
"avx512dq"] = HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save;
1807 Features[
"rdseed"] = HasLeaf7 && ((
EBX >> 18) & 1);
1808 Features[
"adx"] = HasLeaf7 && ((
EBX >> 19) & 1);
1809 Features[
"avx512ifma"] = HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save;
1810 Features[
"clflushopt"] = HasLeaf7 && ((
EBX >> 23) & 1);
1811 Features[
"clwb"] = HasLeaf7 && ((
EBX >> 24) & 1);
1812 Features[
"avx512pf"] = HasLeaf7 && ((
EBX >> 26) & 1) && HasAVX512Save;
1813 Features[
"avx512er"] = HasLeaf7 && ((
EBX >> 27) & 1) && HasAVX512Save;
1814 Features[
"avx512cd"] = HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save;
1815 Features[
"sha"] = HasLeaf7 && ((
EBX >> 29) & 1);
1816 Features[
"avx512bw"] = HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save;
1817 Features[
"avx512vl"] = HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save;
1819 Features[
"prefetchwt1"] = HasLeaf7 && ((
ECX >> 0) & 1);
1820 Features[
"avx512vbmi"] = HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save;
1821 Features[
"pku"] = HasLeaf7 && ((
ECX >> 4) & 1);
1822 Features[
"waitpkg"] = HasLeaf7 && ((
ECX >> 5) & 1);
1823 Features[
"avx512vbmi2"] = HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save;
1824 Features[
"shstk"] = HasLeaf7 && ((
ECX >> 7) & 1);
1825 Features[
"gfni"] = HasLeaf7 && ((
ECX >> 8) & 1);
1826 Features[
"vaes"] = HasLeaf7 && ((
ECX >> 9) & 1) && HasAVXSave;
1827 Features[
"vpclmulqdq"] = HasLeaf7 && ((
ECX >> 10) & 1) && HasAVXSave;
1828 Features[
"avx512vnni"] = HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save;
1829 Features[
"avx512bitalg"] = HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save;
1830 Features[
"avx512vpopcntdq"] = HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save;
1831 Features[
"rdpid"] = HasLeaf7 && ((
ECX >> 22) & 1);
1832 Features[
"kl"] = HasLeaf7 && ((
ECX >> 23) & 1);
1833 Features[
"cldemote"] = HasLeaf7 && ((
ECX >> 25) & 1);
1834 Features[
"movdiri"] = HasLeaf7 && ((
ECX >> 27) & 1);
1835 Features[
"movdir64b"] = HasLeaf7 && ((
ECX >> 28) & 1);
1836 Features[
"enqcmd"] = HasLeaf7 && ((
ECX >> 29) & 1);
1838 Features[
"uintr"] = HasLeaf7 && ((
EDX >> 5) & 1);
1839 Features[
"avx512vp2intersect"] =
1840 HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save;
1841 Features[
"serialize"] = HasLeaf7 && ((
EDX >> 14) & 1);
1842 Features[
"tsxldtrk"] = HasLeaf7 && ((
EDX >> 16) & 1);
1853 Features[
"pconfig"] = HasLeaf7 && ((
EDX >> 18) & 1);
1854 Features[
"amx-bf16"] = HasLeaf7 && ((
EDX >> 22) & 1) && HasAMXSave;
1855 Features[
"avx512fp16"] = HasLeaf7 && ((
EDX >> 23) & 1) && HasAVX512Save;
1856 Features[
"amx-tile"] = HasLeaf7 && ((
EDX >> 24) & 1) && HasAMXSave;
1857 Features[
"amx-int8"] = HasLeaf7 && ((
EDX >> 25) & 1) && HasAMXSave;
1860 bool HasLeaf7Subleaf1 =
1861 HasLeaf7 &&
EAX >= 1 &&
1862 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1863 Features[
"sha512"] = HasLeaf7Subleaf1 && ((
EAX >> 0) & 1);
1864 Features[
"sm3"] = HasLeaf7Subleaf1 && ((
EAX >> 1) & 1);
1865 Features[
"sm4"] = HasLeaf7Subleaf1 && ((
EAX >> 2) & 1);
1866 Features[
"raoint"] = HasLeaf7Subleaf1 && ((
EAX >> 3) & 1);
1867 Features[
"avxvnni"] = HasLeaf7Subleaf1 && ((
EAX >> 4) & 1) && HasAVXSave;
1868 Features[
"avx512bf16"] = HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save;
1869 Features[
"amx-fp16"] = HasLeaf7Subleaf1 && ((
EAX >> 21) & 1) && HasAMXSave;
1870 Features[
"cmpccxadd"] = HasLeaf7Subleaf1 && ((
EAX >> 7) & 1);
1871 Features[
"hreset"] = HasLeaf7Subleaf1 && ((
EAX >> 22) & 1);
1872 Features[
"avxifma"] = HasLeaf7Subleaf1 && ((
EAX >> 23) & 1) && HasAVXSave;
1873 Features[
"avxvnniint8"] = HasLeaf7Subleaf1 && ((
EDX >> 4) & 1) && HasAVXSave;
1874 Features[
"avxneconvert"] = HasLeaf7Subleaf1 && ((
EDX >> 5) & 1) && HasAVXSave;
1875 Features[
"amx-complex"] = HasLeaf7Subleaf1 && ((
EDX >> 8) & 1) && HasAMXSave;
1876 Features[
"avxvnniint16"] = HasLeaf7Subleaf1 && ((
EDX >> 10) & 1) && HasAVXSave;
1877 Features[
"prefetchi"] = HasLeaf7Subleaf1 && ((
EDX >> 14) & 1);
1878 Features[
"usermsr"] = HasLeaf7Subleaf1 && ((
EDX >> 15) & 1);
1879 Features[
"avx10.1-256"] = HasLeaf7Subleaf1 && ((
EDX >> 19) & 1);
1880 bool HasAPXF = HasLeaf7Subleaf1 && ((
EDX >> 21) & 1);
1881 Features[
"egpr"] = HasAPXF;
1882 Features[
"push2pop2"] = HasAPXF;
1883 Features[
"ppx"] = HasAPXF;
1884 Features[
"ndd"] = HasAPXF;
1885 Features[
"ccmp"] = HasAPXF;
1886 Features[
"cf"] = HasAPXF;
1888 bool HasLeafD = MaxLevel >= 0xd &&
1889 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1892 Features[
"xsaveopt"] = HasLeafD && ((
EAX >> 0) & 1) && HasAVXSave;
1893 Features[
"xsavec"] = HasLeafD && ((
EAX >> 1) & 1) && HasAVXSave;
1894 Features[
"xsaves"] = HasLeafD && ((
EAX >> 3) & 1) && HasAVXSave;
1896 bool HasLeaf14 = MaxLevel >= 0x14 &&
1897 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1899 Features[
"ptwrite"] = HasLeaf14 && ((
EBX >> 4) & 1);
1902 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1903 Features[
"widekl"] = HasLeaf7 && HasLeaf19 && ((
EBX >> 2) & 1);
1906 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
1907 Features[
"avx10.1-512"] =
1908 Features[
"avx10.1-256"] && HasLeaf24 && ((
EBX >> 18) & 1);
1912#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1919 P->getBuffer().split(Lines,
"\n");
1924 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I)
1926 Lines[
I].split(CPUFeatures,
' ');
1930#if defined(__aarch64__)
1932 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1938#if defined(__aarch64__)
1939 .
Case(
"asimd",
"neon")
1940 .
Case(
"fp",
"fp-armv8")
1941 .
Case(
"crc32",
"crc")
1942 .
Case(
"atomics",
"lse")
1944 .
Case(
"sve2",
"sve2")
1946 .
Case(
"half",
"fp16")
1947 .
Case(
"neon",
"neon")
1948 .
Case(
"vfpv3",
"vfp3")
1949 .
Case(
"vfpv3d16",
"vfp3d16")
1950 .
Case(
"vfpv4",
"vfp4")
1951 .
Case(
"idiva",
"hwdiv-arm")
1952 .
Case(
"idivt",
"hwdiv")
1956#if defined(__aarch64__)
1959 if (CPUFeatures[
I] ==
"aes")
1961 else if (CPUFeatures[
I] ==
"pmull")
1962 crypto |= CAP_PMULL;
1963 else if (CPUFeatures[
I] ==
"sha1")
1965 else if (CPUFeatures[
I] ==
"sha2")
1969 if (LLVMFeatureStr !=
"")
1970 Features[LLVMFeatureStr] =
true;
1973#if defined(__aarch64__)
1975 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1976 Features[
"crypto"] =
true;
1981#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1983 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1984 Features[
"neon"] =
true;
1985 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1986 Features[
"crc"] =
true;
1987 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1988 Features[
"crypto"] =
true;
1992#elif defined(__linux__) && defined(__loongarch__)
1993#include <sys/auxv.h>
1995 unsigned long hwcap = getauxval(AT_HWCAP);
1996 bool HasFPU = hwcap & (1UL << 3);
1998 __asm__(
"cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2]
"+r"(cpucfg2));
2000 Features[
"f"] = HasFPU && (cpucfg2 & (1U << 1));
2001 Features[
"d"] = HasFPU && (cpucfg2 & (1U << 2));
2003 Features[
"lsx"] = hwcap & (1UL << 4);
2004 Features[
"lasx"] = hwcap & (1UL << 5);
2005 Features[
"lvz"] = hwcap & (1UL << 9);
2018 T.setArchName(
"arm");
2019#elif defined(__arm64e__)
2021 T.setArchName(
"arm64e");
2022#elif defined(__aarch64__)
2024 T.setArchName(
"arm64");
2025#elif defined(__x86_64h__)
2027 T.setArchName(
"x86_64h");
2028#elif defined(__x86_64__)
2030 T.setArchName(
"x86_64");
2031#elif defined(__i386__)
2033 T.setArchName(
"i386");
2034#elif defined(__powerpc__)
2036 T.setArchName(
"powerpc");
2038# error "Unimplemented host arch fixup"
2045 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
2051 PT = withHostArch(PT);
2063#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
2065 if (CPU ==
"generic")
2068 <<
" Host CPU: " << CPU <<
'\n';
This file defines the StringMap class.
#define LLVM_ATTRIBUTE_UNUSED
Given that RA is a live value
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Represents either an error or a value T.
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr bool empty() const
empty - Check if the string is empty.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
static constexpr size_t npos
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & StartsWith(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
std::string normalize() const
Return the normalized form of this triple's string.
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
const std::string & str() const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
@ CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_602
Helper functions to extract CPU details from CPUID on x86.
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
StringRef getHostCPUNameForBPF()
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.