28#define DEBUG_TYPE "mccodeemitter"
32 LoongArchMCCodeEmitter(
const LoongArchMCCodeEmitter &) =
delete;
33 void operator=(
const LoongArchMCCodeEmitter &) =
delete;
39 : Ctx(ctx), MCII(MCII) {}
41 ~LoongArchMCCodeEmitter()
override {}
47 template <
unsigned Opc>
68 unsigned getImmOpValueSub1(
const MCInst &
MI,
unsigned OpNo,
78 unsigned getImmOpValueAsr(
const MCInst &
MI,
unsigned OpNo,
83 unsigned Res =
MI.getOperand(OpNo).getImm();
84 assert((Res & ((1U <<
N) - 1U)) == 0 &&
"lowest N bits are non-zero");
87 return getExprOpValue(
MI, MO, Fixups, STI);
102 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
105 return static_cast<unsigned>(MO.
getImm());
109 return getExprOpValue(
MI, MO, Fixups, STI);
113LoongArchMCCodeEmitter::getImmOpValueSub1(
const MCInst &
MI,
unsigned OpNo,
116 return MI.getOperand(OpNo).getImm() - 1;
123 assert(MO.
isExpr() &&
"getExprOpValue expects only expressions");
124 bool RelaxCandidate =
false;
125 bool EnableRelax = STI.
hasFeature(LoongArch::FeatureRelax);
279 cast<MCSymbolRefExpr>(Expr)->getKind() ==
281 switch (
MI.getOpcode()) {
288 case LoongArch::BLTU:
289 case LoongArch::BGEU:
292 case LoongArch::BEQZ:
293 case LoongArch::BNEZ:
294 case LoongArch::BCEQZ:
295 case LoongArch::BCNEZ:
306 "Unhandled expression!");
313 if (EnableRelax && RelaxCandidate) {
322template <
unsigned Opc>
323void LoongArchMCCodeEmitter::expandToVectorLDI(
326 int64_t
Imm =
MI.getOperand(1).getImm() & 0x3FF;
327 switch (
MI.getOpcode()) {
328 case LoongArch::PseudoVREPLI_B:
329 case LoongArch::PseudoXVREPLI_B:
331 case LoongArch::PseudoVREPLI_H:
332 case LoongArch::PseudoXVREPLI_H:
335 case LoongArch::PseudoVREPLI_W:
336 case LoongArch::PseudoXVREPLI_W:
339 case LoongArch::PseudoVREPLI_D:
340 case LoongArch::PseudoXVREPLI_D:
349void LoongArchMCCodeEmitter::encodeInstruction(
356 switch (
MI.getOpcode()) {
359 case LoongArch::PseudoVREPLI_B:
360 case LoongArch::PseudoVREPLI_H:
361 case LoongArch::PseudoVREPLI_W:
362 case LoongArch::PseudoVREPLI_D:
363 return expandToVectorLDI<LoongArch::VLDI>(
MI, CB, Fixups, STI);
364 case LoongArch::PseudoXVREPLI_B:
365 case LoongArch::PseudoXVREPLI_H:
366 case LoongArch::PseudoXVREPLI_W:
367 case LoongArch::PseudoXVREPLI_D:
368 return expandToVectorLDI<LoongArch::XVLDI>(
MI, CB, Fixups, STI);
384 return new LoongArchMCCodeEmitter(Ctx, MCII);
387#include "LoongArchGenMCCodeEmitter.inc"
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
VariantKind getKind() const
@ VK_LoongArch_PCALA_HI20
@ VK_LoongArch_TLS_LD_PC_HI20
@ VK_LoongArch_TLS_LE64_HI12
@ VK_LoongArch_TLS_LD_HI20
@ VK_LoongArch_TLS_DESC_CALL
@ VK_LoongArch_GOT64_HI12
@ VK_LoongArch_PCALA_LO12
@ VK_LoongArch_TLS_DESC64_HI12
@ VK_LoongArch_TLS_IE_HI20
@ VK_LoongArch_TLS_GD_HI20
@ VK_LoongArch_TLS_DESC_HI20
@ VK_LoongArch_ABS64_HI12
@ VK_LoongArch_TLS_LE_LO12
@ VK_LoongArch_TLS_IE64_HI12
@ VK_LoongArch_GOT_PC_HI20
@ VK_LoongArch_TLS_IE64_PC_LO20
@ VK_LoongArch_TLS_IE64_LO20
@ VK_LoongArch_TLS_IE_PC_LO12
@ VK_LoongArch_TLS_DESC_LD
@ VK_LoongArch_TLS_DESC64_PC_LO20
@ VK_LoongArch_TLS_DESC_LO12
@ VK_LoongArch_GOT64_PC_HI12
@ VK_LoongArch_TLS_IE_PC_HI20
@ VK_LoongArch_TLS_LE64_LO20
@ VK_LoongArch_PCALA64_LO20
@ VK_LoongArch_TLS_IE_LO12
@ VK_LoongArch_GOT_PC_LO12
@ VK_LoongArch_TLS_LE_HI20
@ VK_LoongArch_TLS_DESC_PC_LO12
@ VK_LoongArch_GOT64_LO20
@ VK_LoongArch_TLS_DESC64_LO20
@ VK_LoongArch_TLS_GD_PC_HI20
@ VK_LoongArch_TLS_DESC64_PC_HI12
@ VK_LoongArch_GOT64_PC_LO20
@ VK_LoongArch_PCALA64_HI12
@ VK_LoongArch_TLS_DESC_PC_HI20
@ VK_LoongArch_TLS_IE64_PC_HI12
@ VK_LoongArch_ABS64_LO20
bool getRelaxHint() const
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
@ Target
Target specific expression.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
MCInstBuilder & addOperand(const MCOperand &Op)
Add an operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_loongarch_tls_desc64_pc_lo20
@ fixup_loongarch_tls_ld_pc_hi20
@ fixup_loongarch_abs64_hi12
@ fixup_loongarch_tls_ie_lo12
@ fixup_loongarch_tls_le_lo12
@ fixup_loongarch_abs_hi20
@ fixup_loongarch_tls_ie_hi20
@ fixup_loongarch_pcala64_hi12
@ fixup_loongarch_tls_gd_hi20
@ fixup_loongarch_got64_hi12
@ fixup_loongarch_tls_desc64_hi12
@ fixup_loongarch_tls_ie_pc_lo12
@ fixup_loongarch_pcala_hi20
@ fixup_loongarch_abs_lo12
@ fixup_loongarch_invalid
@ fixup_loongarch_tls_desc64_lo20
@ fixup_loongarch_got64_pc_hi12
@ fixup_loongarch_abs64_lo20
@ fixup_loongarch_pcala64_lo20
@ fixup_loongarch_tls_desc_hi20
@ fixup_loongarch_tls_le64_hi12
@ fixup_loongarch_got64_lo20
@ fixup_loongarch_tls_le64_lo20
@ fixup_loongarch_got64_pc_lo20
@ fixup_loongarch_tls_desc_call
@ fixup_loongarch_got_pc_lo12
@ fixup_loongarch_tls_gd_pc_hi20
@ fixup_loongarch_tls_desc_ld
@ fixup_loongarch_tls_desc_lo12
@ fixup_loongarch_tls_desc64_pc_hi12
@ fixup_loongarch_tls_ld_hi20
@ fixup_loongarch_pcala_lo12
@ fixup_loongarch_got_lo12
@ fixup_loongarch_tls_desc_pc_hi20
@ fixup_loongarch_tls_ie64_pc_hi12
@ fixup_loongarch_got_pc_hi20
@ fixup_loongarch_tls_ie64_pc_lo20
@ fixup_loongarch_got_hi20
@ fixup_loongarch_tls_le_hi20
@ fixup_loongarch_tls_ie64_lo20
@ fixup_loongarch_tls_ie64_hi12
@ fixup_loongarch_tls_desc_pc_lo12
@ fixup_loongarch_tls_ie_pc_hi20
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createLoongArchMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Description of the encoding of one expression Op.