95 struct MachineVerifier {
96 MachineVerifier(
Pass *
pass,
const char *b) : PASS(
pass), Banner(
b) {}
101 : Banner(
b), LiveVars(LiveVars), LiveInts(LiveInts), LiveStks(LiveStks),
106 Pass *
const PASS =
nullptr;
115 unsigned foundErrors = 0;
118 bool isFunctionRegBankSelected =
false;
119 bool isFunctionSelected =
false;
120 bool isFunctionTracksDebugUserValues =
false;
130 BlockSet FunctionBlocks;
134 RegVector regsDefined, regsDead, regsKilled;
135 RegMaskVector regMasks;
140 void addRegWithSubRegs(RegVector &RV,
Register Reg) {
142 if (
Reg.isPhysical())
148 bool reachable =
false;
169 RegSet vregsRequired;
172 BlockSet Preds, Succs;
179 if (!
Reg.isVirtual())
181 if (regsLiveOut.count(Reg))
183 return vregsRequired.insert(Reg).second;
187 bool addRequired(
const RegSet &RS) {
188 bool Changed =
false;
190 Changed |= addRequired(Reg);
195 bool addRequired(
const RegMap &RM) {
196 bool Changed =
false;
197 for (
const auto &
I : RM)
198 Changed |= addRequired(
I.first);
204 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
212 return Reg.id() < regsReserved.
size() && regsReserved.
test(
Reg.id());
215 bool isAllocatable(
Register Reg)
const {
216 return Reg.id() <
TRI->getNumRegs() &&
TRI->isInAllocatableClass(Reg) &&
231 void visitMachineFunctionBefore();
247 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
250 void visitMachineFunctionAfter();
255 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum,
263 void report_context(
const VNInfo &VNI)
const;
264 void report_context(
SlotIndex Pos)
const;
265 void report_context(
MCPhysReg PhysReg)
const;
266 void report_context_liverange(
const LiveRange &LR)
const;
267 void report_context_lanemask(
LaneBitmask LaneMask)
const;
268 void report_context_vreg(
Register VReg)
const;
269 void report_context_vreg_regunit(
Register VRegOrUnit)
const;
280 Register VRegOrUnit,
bool SubRangeCheck =
false,
284 void calcRegsPassed();
287 void calcRegsRequired();
288 void verifyLiveVariables();
289 void verifyLiveIntervals();
293 void verifyLiveRangeSegment(
const LiveRange &,
299 void verifyStackFrame();
301 void verifySlotIndexes()
const;
308 const std::string Banner;
310 MachineVerifierPass(std::string banner = std::string())
329 MachineFunctionProperties::Property::FailsVerification))
332 unsigned FoundErrors = MachineVerifier(
this, Banner.c_str()).verify(MF);
341char MachineVerifierPass::ID = 0;
344 "Verify generated machine code",
false,
false)
347 return new MachineVerifierPass(Banner);
357 unsigned FoundErrors = MachineVerifier(
nullptr, Banner.c_str()).verify(MF);
365 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
366 if (AbortOnErrors && FoundErrors)
368 return FoundErrors == 0;
372 const char *Banner,
bool AbortOnErrors)
const {
374 unsigned FoundErrors =
375 MachineVerifier(Banner,
nullptr, LiveInts,
nullptr, Indexes).verify(MF);
376 if (AbortOnErrors && FoundErrors)
378 return FoundErrors == 0;
381void MachineVerifier::verifySlotIndexes()
const {
382 if (Indexes ==
nullptr)
400 MRI->getNumVirtRegs())
401 report(
"Function has NoVRegs property but there are VReg operands", &MF);
420 if (isFunctionFailedISel)
441 verifyProperties(MF);
443 visitMachineFunctionBefore();
445 visitMachineBasicBlockBefore(&
MBB);
449 bool InBundle =
false;
452 if (
MI.getParent() != &
MBB) {
453 report(
"Bad instruction parent pointer", &
MBB);
454 errs() <<
"Instruction: " <<
MI;
459 if (InBundle && !
MI.isBundledWithPred())
460 report(
"Missing BundledPred flag, "
461 "BundledSucc was set on predecessor",
463 if (!InBundle &&
MI.isBundledWithPred())
464 report(
"BundledPred flag is set, "
465 "but BundledSucc not set on predecessor",
469 if (!
MI.isInsideBundle()) {
471 visitMachineBundleAfter(CurBundle);
473 visitMachineBundleBefore(CurBundle);
474 }
else if (!CurBundle)
475 report(
"No bundle header", &
MI);
476 visitMachineInstrBefore(&
MI);
477 for (
unsigned I = 0, E =
MI.getNumOperands();
I != E; ++
I) {
479 if (
Op.getParent() != &
MI) {
482 report(
"Instruction has operand with wrong parent set", &
MI);
485 visitMachineOperand(&
Op,
I);
489 InBundle =
MI.isBundledWithSucc();
492 visitMachineBundleAfter(CurBundle);
494 report(
"BundledSucc flag set on last instruction in block", &
MBB.
back());
495 visitMachineBasicBlockAfter(&
MBB);
497 visitMachineFunctionAfter();
510void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
513 if (!foundErrors++) {
515 errs() <<
"# " << Banner <<
'\n';
516 if (LiveInts !=
nullptr)
521 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
522 <<
"- function: " << MF->
getName() <<
"\n";
536void MachineVerifier::report(
const char *msg,
const MachineInstr *
MI) {
538 report(msg,
MI->getParent());
539 errs() <<
"- instruction: ";
545void MachineVerifier::report(
const char *msg,
const MachineOperand *MO,
546 unsigned MONum,
LLT MOVRegType) {
549 errs() <<
"- operand " << MONum <<
": ";
555 report(
Msg.str().c_str(),
MI);
558void MachineVerifier::report_context(
SlotIndex Pos)
const {
559 errs() <<
"- at: " << Pos <<
'\n';
562void MachineVerifier::report_context(
const LiveInterval &LI)
const {
563 errs() <<
"- interval: " << LI <<
'\n';
568 report_context_liverange(LR);
569 report_context_vreg_regunit(VRegUnit);
571 report_context_lanemask(LaneMask);
575 errs() <<
"- segment: " << S <<
'\n';
578void MachineVerifier::report_context(
const VNInfo &VNI)
const {
579 errs() <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
582void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
583 errs() <<
"- liverange: " << LR <<
'\n';
586void MachineVerifier::report_context(
MCPhysReg PReg)
const {
590void MachineVerifier::report_context_vreg(
Register VReg)
const {
594void MachineVerifier::report_context_vreg_regunit(
Register VRegOrUnit)
const {
596 report_context_vreg(VRegOrUnit);
602void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
607 BBInfo &MInfo = MBBInfoMap[
MBB];
608 if (!MInfo.reachable) {
609 MInfo.reachable =
true;
615void MachineVerifier::visitMachineFunctionBefore() {
617 regsReserved =
MRI->reservedRegsFrozen() ?
MRI->getReservedRegs()
618 :
TRI->getReservedRegs(*MF);
621 markReachable(&MF->
front());
624 FunctionBlocks.clear();
625 for (
const auto &
MBB : *MF) {
626 FunctionBlocks.insert(&
MBB);
627 BBInfo &MInfo = MBBInfoMap[&
MBB];
631 report(
"MBB has duplicate entries in its predecessor list.", &
MBB);
635 report(
"MBB has duplicate entries in its successor list.", &
MBB);
639 MRI->verifyUseLists();
647 FirstTerminator =
nullptr;
648 FirstNonPHI =
nullptr;
650 if (!MF->getProperties().hasProperty(
655 if (isAllocatable(LI.PhysReg) && !
MBB->
isEHPad() &&
658 report(
"MBB has allocatable live-in, but isn't entry, landing-pad, or "
659 "inlineasm-br-indirect-target.",
661 report_context(LI.PhysReg);
668 report(
"ir-block-address-taken is associated with basic block not used by "
677 LandingPadSuccs.
insert(succ);
678 if (!FunctionBlocks.count(succ))
679 report(
"MBB has successor that isn't part of the function.",
MBB);
680 if (!MBBInfoMap[succ].Preds.count(
MBB)) {
681 report(
"Inconsistent CFG",
MBB);
682 errs() <<
"MBB is not in the predecessor list of the successor "
689 if (!FunctionBlocks.count(Pred))
690 report(
"MBB has predecessor that isn't part of the function.",
MBB);
691 if (!MBBInfoMap[Pred].Succs.count(
MBB)) {
692 report(
"Inconsistent CFG",
MBB);
693 errs() <<
"MBB is not in the successor list of the predecessor "
701 if (LandingPadSuccs.
size() > 1 &&
706 report(
"MBB has more than one landing pad successor",
MBB);
719 report(
"MBB exits via unconditional fall-through but ends with a "
720 "barrier instruction!",
MBB);
723 report(
"MBB exits via unconditional fall-through but has a condition!",
726 }
else if (
TBB && !FBB &&
Cond.empty()) {
729 report(
"MBB exits via unconditional branch but doesn't contain "
730 "any instructions!",
MBB);
732 report(
"MBB exits via unconditional branch but doesn't end with a "
733 "barrier instruction!",
MBB);
735 report(
"MBB exits via unconditional branch but the branch isn't a "
736 "terminator instruction!",
MBB);
738 }
else if (
TBB && !FBB && !
Cond.empty()) {
741 report(
"MBB exits via conditional branch/fall-through but doesn't "
742 "contain any instructions!",
MBB);
744 report(
"MBB exits via conditional branch/fall-through but ends with a "
745 "barrier instruction!",
MBB);
747 report(
"MBB exits via conditional branch/fall-through but the branch "
748 "isn't a terminator instruction!",
MBB);
750 }
else if (
TBB && FBB) {
754 report(
"MBB exits via conditional branch/branch but doesn't "
755 "contain any instructions!",
MBB);
757 report(
"MBB exits via conditional branch/branch but doesn't end with a "
758 "barrier instruction!",
MBB);
760 report(
"MBB exits via conditional branch/branch but the branch "
761 "isn't a terminator instruction!",
MBB);
764 report(
"MBB exits via conditional branch/branch but there's no "
768 report(
"analyzeBranch returned invalid data!",
MBB);
774 report(
"MBB exits via jump or conditional branch, but its target isn't a "
778 report(
"MBB exits via conditional branch, but its target isn't a CFG "
785 bool Fallthrough = !
TBB || (!
Cond.empty() && !FBB);
790 if (!
Cond.empty() && !FBB) {
793 report(
"MBB conditionally falls through out of function!",
MBB);
795 report(
"MBB exits via conditional branch/fall-through but the CFG "
796 "successors don't match the actual successors!",
803 if (SuccMBB ==
TBB || SuccMBB == FBB)
811 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
813 report(
"MBB has unexpected successors which are not branch targets, "
814 "fallthrough, EHPads, or inlineasm_br targets.",
820 if (
MRI->tracksLiveness()) {
823 report(
"MBB live-in list contains non-physical register",
MBB);
847void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *
MI) {
850 if (!(idx > lastIndex)) {
851 report(
"Instruction index out of order",
MI);
852 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
858 if (
MI->isTerminator()) {
859 if (!FirstTerminator)
860 FirstTerminator =
MI;
861 }
else if (FirstTerminator) {
864 if (FirstTerminator->
getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
865 report(
"Non-terminator instruction after the first terminator",
MI);
866 errs() <<
"First terminator was:\t" << *FirstTerminator;
875 if (
MI->getNumOperands() < 2) {
876 report(
"Too few operands on inline asm",
MI);
879 if (!
MI->getOperand(0).isSymbol())
880 report(
"Asm string must be an external symbol",
MI);
881 if (!
MI->getOperand(1).isImm())
882 report(
"Asm flags must be an immediate",
MI);
886 if (!isUInt<6>(
MI->getOperand(1).getImm()))
887 report(
"Unknown asm flags", &
MI->getOperand(1), 1);
893 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; OpNo += NumOps) {
899 NumOps = 1 +
F.getNumOperandRegisters();
902 if (OpNo >
MI->getNumOperands())
903 report(
"Missing operands in last group",
MI);
906 if (OpNo < MI->getNumOperands() &&
MI->getOperand(OpNo).isMetadata())
910 for (
unsigned e =
MI->getNumOperands(); OpNo < e; ++OpNo) {
913 report(
"Expected implicit register after groups", &MO, OpNo);
916 if (
MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
929 if (!IndirectTargetMBB) {
930 report(
"INLINEASM_BR indirect target does not exist", &MO, i);
935 report(
"INLINEASM_BR indirect target missing from successor list", &MO,
939 report(
"INLINEASM_BR indirect target predecessor list missing parent",
945bool MachineVerifier::verifyAllRegOpsScalar(
const MachineInstr &
MI,
950 const auto Reg = Op.getReg();
951 if (Reg.isPhysical())
953 return !MRI.getType(Reg).isScalar();
956 report(
"All register operands must have scalar types", &
MI);
963bool MachineVerifier::verifyVectorElementMatch(
LLT Ty0,
LLT Ty1,
966 report(
"operand types must be all-vector or all-scalar",
MI);
976 report(
"operand types must preserve number of vector elements",
MI);
983bool MachineVerifier::verifyGIntrinsicSideEffects(
const MachineInstr *
MI) {
984 auto Opcode =
MI->getOpcode();
985 bool NoSideEffects = Opcode == TargetOpcode::G_INTRINSIC ||
986 Opcode == TargetOpcode::G_INTRINSIC_CONVERGENT;
987 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
988 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
990 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
991 bool DeclHasSideEffects = !
Attrs.getMemoryEffects().doesNotAccessMemory();
992 if (NoSideEffects && DeclHasSideEffects) {
994 " used with intrinsic that accesses memory"),
998 if (!NoSideEffects && !DeclHasSideEffects) {
999 report(
Twine(
TII->getName(Opcode),
" used with readnone intrinsic"),
MI);
1007bool MachineVerifier::verifyGIntrinsicConvergence(
const MachineInstr *
MI) {
1008 auto Opcode =
MI->getOpcode();
1009 bool NotConvergent = Opcode == TargetOpcode::G_INTRINSIC ||
1010 Opcode == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
1011 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
1012 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1014 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
1015 bool DeclIsConvergent =
Attrs.hasFnAttr(Attribute::Convergent);
1016 if (NotConvergent && DeclIsConvergent) {
1017 report(
Twine(
TII->getName(Opcode),
" used with a convergent intrinsic"),
1021 if (!NotConvergent && !DeclIsConvergent) {
1023 Twine(
TII->getName(Opcode),
" used with a non-convergent intrinsic"),
1032void MachineVerifier::verifyPreISelGenericInstruction(
const MachineInstr *
MI) {
1033 if (isFunctionSelected)
1034 report(
"Unexpected generic instruction in a Selected function",
MI);
1037 unsigned NumOps =
MI->getNumOperands();
1040 if (
MI->isBranch() && !
MI->isIndirectBranch()) {
1041 bool HasMBB =
false;
1050 report(
"Branch instruction is missing a basic block operand or "
1051 "isIndirectBranch property",
1060 if (!MCID.
operands()[
I].isGenericType())
1064 size_t TypeIdx = MCID.
operands()[
I].getGenericTypeIndex();
1065 Types.resize(std::max(TypeIdx + 1,
Types.size()));
1069 report(
"generic instruction must use register operands",
MI);
1079 if (!Types[TypeIdx].
isValid())
1080 Types[TypeIdx] = OpTy;
1081 else if (Types[TypeIdx] != OpTy)
1082 report(
"Type mismatch in generic instruction", MO,
I, OpTy);
1085 report(
"Generic instruction is missing a virtual register type", MO,
I);
1090 for (
unsigned I = 0;
I <
MI->getNumOperands(); ++
I) {
1093 report(
"Generic instruction cannot have physical register", MO,
I);
1105 unsigned Opc =
MI->getOpcode();
1107 case TargetOpcode::G_ASSERT_SEXT:
1108 case TargetOpcode::G_ASSERT_ZEXT: {
1109 std::string OpcName =
1110 Opc == TargetOpcode::G_ASSERT_ZEXT ?
"G_ASSERT_ZEXT" :
"G_ASSERT_SEXT";
1111 if (!
MI->getOperand(2).isImm()) {
1112 report(
Twine(OpcName,
" expects an immediate operand #2"),
MI);
1118 LLT SrcTy =
MRI->getType(Src);
1119 int64_t
Imm =
MI->getOperand(2).getImm();
1121 report(
Twine(OpcName,
" size must be >= 1"),
MI);
1126 report(
Twine(OpcName,
" size must be less than source bit width"),
MI);
1134 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1135 report(
Twine(OpcName,
" cannot change register bank"),
MI);
1141 if (DstRC && DstRC !=
MRI->getRegClassOrNull(Src)) {
1143 Twine(OpcName,
" source and destination register classes must match"),
1151 case TargetOpcode::G_CONSTANT:
1152 case TargetOpcode::G_FCONSTANT: {
1153 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1155 report(
"Instruction cannot use a vector result type",
MI);
1157 if (
MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1158 if (!
MI->getOperand(1).isCImm()) {
1159 report(
"G_CONSTANT operand must be cimm",
MI);
1165 report(
"inconsistent constant size",
MI);
1167 if (!
MI->getOperand(1).isFPImm()) {
1168 report(
"G_FCONSTANT operand must be fpimm",
MI);
1175 report(
"inconsistent constant size",
MI);
1181 case TargetOpcode::G_LOAD:
1182 case TargetOpcode::G_STORE:
1183 case TargetOpcode::G_ZEXTLOAD:
1184 case TargetOpcode::G_SEXTLOAD: {
1185 LLT ValTy =
MRI->getType(
MI->getOperand(0).getReg());
1186 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1188 report(
"Generic memory instruction must access a pointer",
MI);
1192 if (!
MI->hasOneMemOperand()) {
1193 report(
"Generic instruction accessing memory must have one mem operand",
1197 if (
MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1198 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1201 report(
"Generic extload must have a narrower memory type",
MI);
1202 }
else if (
MI->getOpcode() == TargetOpcode::G_LOAD) {
1205 report(
"load memory size cannot exceed result size",
MI);
1206 }
else if (
MI->getOpcode() == TargetOpcode::G_STORE) {
1209 report(
"store memory size cannot exceed value size",
MI);
1213 if (Opc == TargetOpcode::G_STORE) {
1216 report(
"atomic store cannot use acquire ordering",
MI);
1221 report(
"atomic load cannot use release ordering",
MI);
1227 case TargetOpcode::G_PHI: {
1228 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1233 LLT Ty = MRI->getType(MO.getReg());
1234 if (!Ty.isValid() || (Ty != DstTy))
1238 report(
"Generic Instruction G_PHI has operands with incompatible/missing "
1243 case TargetOpcode::G_BITCAST: {
1244 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1245 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1250 report(
"bitcast cannot convert between pointers and other types",
MI);
1253 report(
"bitcast sizes must match",
MI);
1256 report(
"bitcast must change the type",
MI);
1260 case TargetOpcode::G_INTTOPTR:
1261 case TargetOpcode::G_PTRTOINT:
1262 case TargetOpcode::G_ADDRSPACE_CAST: {
1263 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1264 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1268 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1273 if (
MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1275 report(
"inttoptr result type must be a pointer",
MI);
1277 report(
"inttoptr source type must not be a pointer",
MI);
1278 }
else if (
MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1280 report(
"ptrtoint source type must be a pointer",
MI);
1282 report(
"ptrtoint result type must not be a pointer",
MI);
1284 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1286 report(
"addrspacecast types must be pointers",
MI);
1289 report(
"addrspacecast must convert different address spaces",
MI);
1295 case TargetOpcode::G_PTR_ADD: {
1296 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1297 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1298 LLT OffsetTy =
MRI->getType(
MI->getOperand(2).getReg());
1303 report(
"gep first operand must be a pointer",
MI);
1306 report(
"gep offset operand must not be a pointer",
MI);
1311 unsigned IndexSizeInBits =
DL.getIndexSize(AS) * 8;
1313 report(
"gep offset operand must match index size for address space",
1321 case TargetOpcode::G_PTRMASK: {
1322 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1323 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1324 LLT MaskTy =
MRI->getType(
MI->getOperand(2).getReg());
1329 report(
"ptrmask result type must be a pointer",
MI);
1332 report(
"ptrmask mask type must be an integer",
MI);
1334 verifyVectorElementMatch(DstTy, MaskTy,
MI);
1337 case TargetOpcode::G_SEXT:
1338 case TargetOpcode::G_ZEXT:
1339 case TargetOpcode::G_ANYEXT:
1340 case TargetOpcode::G_TRUNC:
1341 case TargetOpcode::G_FPEXT:
1342 case TargetOpcode::G_FPTRUNC: {
1349 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1350 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1355 report(
"Generic extend/truncate can not operate on pointers",
MI);
1357 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1361 switch (
MI->getOpcode()) {
1363 if (DstSize <= SrcSize)
1364 report(
"Generic extend has destination type no larger than source",
MI);
1366 case TargetOpcode::G_TRUNC:
1367 case TargetOpcode::G_FPTRUNC:
1368 if (DstSize >= SrcSize)
1369 report(
"Generic truncate has destination type no smaller than source",
1375 case TargetOpcode::G_SELECT: {
1376 LLT SelTy =
MRI->getType(
MI->getOperand(0).getReg());
1377 LLT CondTy =
MRI->getType(
MI->getOperand(1).getReg());
1383 verifyVectorElementMatch(SelTy, CondTy,
MI);
1386 case TargetOpcode::G_MERGE_VALUES: {
1391 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1392 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1394 report(
"G_MERGE_VALUES cannot operate on vectors",
MI);
1396 const unsigned NumOps =
MI->getNumOperands();
1398 report(
"G_MERGE_VALUES result size is inconsistent",
MI);
1400 for (
unsigned I = 2;
I != NumOps; ++
I) {
1401 if (
MRI->getType(
MI->getOperand(
I).getReg()) != SrcTy)
1402 report(
"G_MERGE_VALUES source types do not match",
MI);
1407 case TargetOpcode::G_UNMERGE_VALUES: {
1408 unsigned NumDsts =
MI->getNumOperands() - 1;
1409 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1410 for (
unsigned i = 1; i < NumDsts; ++i) {
1411 if (
MRI->getType(
MI->getOperand(i).getReg()) != DstTy) {
1412 report(
"G_UNMERGE_VALUES destination types do not match",
MI);
1417 LLT SrcTy =
MRI->getType(
MI->getOperand(NumDsts).getReg());
1423 report(
"G_UNMERGE_VALUES source operand does not match vector "
1424 "destination operands",
1431 report(
"G_UNMERGE_VALUES vector source operand does not match scalar "
1432 "destination operands",
1437 report(
"G_UNMERGE_VALUES scalar source operand does not match scalar "
1438 "destination operands",
1444 case TargetOpcode::G_BUILD_VECTOR: {
1447 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1448 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1450 report(
"G_BUILD_VECTOR must produce a vector from scalar operands",
MI);
1455 report(
"G_BUILD_VECTOR result element type must match source type",
MI);
1458 report(
"G_BUILD_VECTOR must have an operand for each elemement",
MI);
1461 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1462 report(
"G_BUILD_VECTOR source operand types are not homogeneous",
MI);
1466 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1469 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1470 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1472 report(
"G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1475 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1476 report(
"G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1479 report(
"G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1484 case TargetOpcode::G_CONCAT_VECTORS: {
1487 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1488 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1490 report(
"G_CONCAT_VECTOR requires vector source and destination operands",
1493 if (
MI->getNumOperands() < 3)
1494 report(
"G_CONCAT_VECTOR requires at least 2 source operands",
MI);
1497 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1498 report(
"G_CONCAT_VECTOR source operand types are not homogeneous",
MI);
1501 report(
"G_CONCAT_VECTOR num dest and source elements should match",
MI);
1504 case TargetOpcode::G_ICMP:
1505 case TargetOpcode::G_FCMP: {
1506 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1507 LLT SrcTy =
MRI->getType(
MI->getOperand(2).getReg());
1512 report(
"Generic vector icmp/fcmp must preserve number of lanes",
MI);
1516 case TargetOpcode::G_EXTRACT: {
1518 if (!
SrcOp.isReg()) {
1519 report(
"extract source must be a register",
MI);
1524 if (!OffsetOp.
isImm()) {
1525 report(
"extract offset must be a constant",
MI);
1529 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1531 if (SrcSize == DstSize)
1532 report(
"extract source must be larger than result",
MI);
1534 if (DstSize + OffsetOp.
getImm() > SrcSize)
1535 report(
"extract reads past end of register",
MI);
1538 case TargetOpcode::G_INSERT: {
1540 if (!
SrcOp.isReg()) {
1541 report(
"insert source must be a register",
MI);
1546 if (!OffsetOp.
isImm()) {
1547 report(
"insert offset must be a constant",
MI);
1551 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1554 if (DstSize <= SrcSize)
1555 report(
"inserted size must be smaller than total register",
MI);
1557 if (SrcSize + OffsetOp.
getImm() > DstSize)
1558 report(
"insert writes past end of register",
MI);
1562 case TargetOpcode::G_JUMP_TABLE: {
1563 if (!
MI->getOperand(1).isJTI())
1564 report(
"G_JUMP_TABLE source operand must be a jump table index",
MI);
1565 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1567 report(
"G_JUMP_TABLE dest operand must have a pointer type",
MI);
1570 case TargetOpcode::G_BRJT: {
1571 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1572 report(
"G_BRJT src operand 0 must be a pointer type",
MI);
1574 if (!
MI->getOperand(1).isJTI())
1575 report(
"G_BRJT src operand 1 must be a jump table index",
MI);
1577 const auto &IdxOp =
MI->getOperand(2);
1578 if (!IdxOp.isReg() ||
MRI->getType(IdxOp.getReg()).isPointer())
1579 report(
"G_BRJT src operand 2 must be a scalar reg type",
MI);
1582 case TargetOpcode::G_INTRINSIC:
1583 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
1584 case TargetOpcode::G_INTRINSIC_CONVERGENT:
1585 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: {
1590 report(
"G_INTRINSIC first src operand must be an intrinsic ID",
MI);
1594 if (!verifyGIntrinsicSideEffects(
MI))
1596 if (!verifyGIntrinsicConvergence(
MI))
1601 case TargetOpcode::G_SEXT_INREG: {
1602 if (!
MI->getOperand(2).isImm()) {
1603 report(
"G_SEXT_INREG expects an immediate operand #2",
MI);
1607 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1608 int64_t
Imm =
MI->getOperand(2).getImm();
1610 report(
"G_SEXT_INREG size must be >= 1",
MI);
1612 report(
"G_SEXT_INREG size must be less than source bit width",
MI);
1615 case TargetOpcode::G_BSWAP: {
1616 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1618 report(
"G_BSWAP size must be a multiple of 16 bits",
MI);
1621 case TargetOpcode::G_VSCALE: {
1622 if (!
MI->getOperand(1).isCImm()) {
1623 report(
"G_VSCALE operand must be cimm",
MI);
1626 if (
MI->getOperand(1).getCImm()->isZero()) {
1627 report(
"G_VSCALE immediate cannot be zero",
MI);
1632 case TargetOpcode::G_INSERT_SUBVECTOR: {
1634 if (!Src0Op.
isReg()) {
1635 report(
"G_INSERT_SUBVECTOR first source must be a register",
MI);
1640 if (!Src1Op.
isReg()) {
1641 report(
"G_INSERT_SUBVECTOR second source must be a register",
MI);
1646 if (!IndexOp.
isImm()) {
1647 report(
"G_INSERT_SUBVECTOR index must be an immediate",
MI);
1651 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1656 report(
"Destination type must be a vector",
MI);
1661 report(
"First source must be a vector",
MI);
1666 report(
"Second source must be a vector",
MI);
1670 if (DstTy != Src0Ty) {
1671 report(
"Destination type must match the first source vector type",
MI);
1676 report(
"Element type of source vectors must be the same",
MI);
1680 if (IndexOp.
getImm() != 0 &&
1682 report(
"Index must be a multiple of the second source vector's "
1683 "minimum vector length",
1689 case TargetOpcode::G_EXTRACT_SUBVECTOR: {
1691 if (!
SrcOp.isReg()) {
1692 report(
"G_EXTRACT_SUBVECTOR first source must be a register",
MI);
1697 if (!IndexOp.
isImm()) {
1698 report(
"G_EXTRACT_SUBVECTOR index must be an immediate",
MI);
1702 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1706 report(
"Destination type must be a vector",
MI);
1711 report(
"First source must be a vector",
MI);
1716 report(
"Element type of vectors must be the same",
MI);
1720 if (IndexOp.
getImm() != 0 &&
1722 report(
"Index must be a multiple of the source vector's minimum vector "
1730 case TargetOpcode::G_SHUFFLE_VECTOR: {
1733 report(
"Incorrect mask operand type for G_SHUFFLE_VECTOR",
MI);
1737 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1738 LLT Src0Ty =
MRI->getType(
MI->getOperand(1).getReg());
1739 LLT Src1Ty =
MRI->getType(
MI->getOperand(2).getReg());
1741 if (Src0Ty != Src1Ty)
1742 report(
"Source operands must be the same type",
MI);
1745 report(
"G_SHUFFLE_VECTOR cannot change element type",
MI);
1754 if (
static_cast<int>(MaskIdxes.
size()) != DstNumElts)
1755 report(
"Wrong result type for shufflemask",
MI);
1757 for (
int Idx : MaskIdxes) {
1761 if (
Idx >= 2 * SrcNumElts)
1762 report(
"Out of bounds shuffle index",
MI);
1768 case TargetOpcode::G_SPLAT_VECTOR: {
1769 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1770 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1773 report(
"Destination type must be a scalable vector",
MI);
1778 report(
"Source type must be a scalar",
MI);
1784 report(
"Element type of the destination must be the same size or smaller "
1785 "than the source type",
1792 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1793 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1794 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1795 LLT IdxTy =
MRI->getType(
MI->getOperand(2).getReg());
1798 report(
"Destination type must be a scalar or pointer",
MI);
1803 report(
"First source must be a vector",
MI);
1807 auto TLI = MF->getSubtarget().getTargetLowering();
1809 TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
1810 report(
"Index type must match VectorIdxTy",
MI);
1816 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1817 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1818 LLT VecTy =
MRI->getType(
MI->getOperand(1).getReg());
1819 LLT ScaTy =
MRI->getType(
MI->getOperand(2).getReg());
1820 LLT IdxTy =
MRI->getType(
MI->getOperand(3).getReg());
1823 report(
"Destination type must be a vector",
MI);
1827 if (VecTy != DstTy) {
1828 report(
"Destination type and vector type must match",
MI);
1833 report(
"Inserted element must be a scalar or pointer",
MI);
1837 auto TLI = MF->getSubtarget().getTargetLowering();
1839 TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
1840 report(
"Index type must match VectorIdxTy",
MI);
1846 case TargetOpcode::G_DYN_STACKALLOC: {
1852 report(
"dst operand 0 must be a pointer type",
MI);
1856 if (!AllocOp.
isReg() || !
MRI->getType(AllocOp.
getReg()).isScalar()) {
1857 report(
"src operand 1 must be a scalar reg type",
MI);
1861 if (!AlignOp.
isImm()) {
1862 report(
"src operand 2 must be an immediate type",
MI);
1867 case TargetOpcode::G_MEMCPY_INLINE:
1868 case TargetOpcode::G_MEMCPY:
1869 case TargetOpcode::G_MEMMOVE: {
1871 if (MMOs.
size() != 2) {
1872 report(
"memcpy/memmove must have 2 memory operands",
MI);
1878 report(
"wrong memory operand types",
MI);
1883 report(
"inconsistent memory operand sizes",
MI);
1885 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1886 LLT SrcPtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1889 report(
"memory instruction operand must be a pointer",
MI);
1894 report(
"inconsistent store address space",
MI);
1896 report(
"inconsistent load address space",
MI);
1898 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1899 if (!
MI->getOperand(3).isImm() || (
MI->getOperand(3).getImm() & ~1LL))
1900 report(
"'tail' flag (operand 3) must be an immediate 0 or 1",
MI);
1904 case TargetOpcode::G_BZERO:
1905 case TargetOpcode::G_MEMSET: {
1907 std::string
Name = Opc == TargetOpcode::G_MEMSET ?
"memset" :
"bzero";
1908 if (MMOs.
size() != 1) {
1909 report(
Twine(
Name,
" must have 1 memory operand"),
MI);
1914 report(
Twine(
Name,
" memory operand must be a store"),
MI);
1918 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1920 report(
Twine(
Name,
" operand must be a pointer"),
MI);
1925 report(
"inconsistent " +
Twine(
Name,
" address space"),
MI);
1927 if (!
MI->getOperand(
MI->getNumOperands() - 1).isImm() ||
1928 (
MI->getOperand(
MI->getNumOperands() - 1).getImm() & ~1LL))
1929 report(
"'tail' flag (last operand) must be an immediate 0 or 1",
MI);
1933 case TargetOpcode::G_UBSANTRAP: {
1935 if (!
MI->getOperand(0).isImm()) {
1936 report(
"Crash kind must be an immediate", &KindOp, 0);
1939 int64_t
Kind =
MI->getOperand(0).getImm();
1940 if (!isInt<8>(Kind))
1941 report(
"Crash kind must be 8 bit wide", &KindOp, 0);
1944 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1945 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1946 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1947 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1948 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1950 report(
"Vector reduction requires a scalar destination type",
MI);
1952 report(
"Sequential FADD/FMUL vector reduction requires a scalar 1st operand",
MI);
1954 report(
"Sequential FADD/FMUL vector reduction must have a vector 2nd operand",
MI);
1957 case TargetOpcode::G_VECREDUCE_FADD:
1958 case TargetOpcode::G_VECREDUCE_FMUL:
1959 case TargetOpcode::G_VECREDUCE_FMAX:
1960 case TargetOpcode::G_VECREDUCE_FMIN:
1961 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1962 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1963 case TargetOpcode::G_VECREDUCE_ADD:
1964 case TargetOpcode::G_VECREDUCE_MUL:
1965 case TargetOpcode::G_VECREDUCE_AND:
1966 case TargetOpcode::G_VECREDUCE_OR:
1967 case TargetOpcode::G_VECREDUCE_XOR:
1968 case TargetOpcode::G_VECREDUCE_SMAX:
1969 case TargetOpcode::G_VECREDUCE_SMIN:
1970 case TargetOpcode::G_VECREDUCE_UMAX:
1971 case TargetOpcode::G_VECREDUCE_UMIN: {
1972 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1974 report(
"Vector reduction requires a scalar destination type",
MI);
1978 case TargetOpcode::G_SBFX:
1979 case TargetOpcode::G_UBFX: {
1980 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1982 report(
"Bitfield extraction is not supported on vectors",
MI);
1987 case TargetOpcode::G_SHL:
1988 case TargetOpcode::G_LSHR:
1989 case TargetOpcode::G_ASHR:
1990 case TargetOpcode::G_ROTR:
1991 case TargetOpcode::G_ROTL: {
1992 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1993 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1995 report(
"Shifts and rotates require operands to be either all scalars or "
2002 case TargetOpcode::G_LLROUND:
2003 case TargetOpcode::G_LROUND: {
2004 verifyAllRegOpsScalar(*
MI, *
MRI);
2007 case TargetOpcode::G_IS_FPCLASS: {
2008 LLT DestTy =
MRI->getType(
MI->getOperand(0).getReg());
2011 report(
"Destination must be a scalar or vector of scalars",
MI);
2014 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
2017 report(
"Source must be a scalar or vector of scalars",
MI);
2020 if (!verifyVectorElementMatch(DestTy, SrcTy,
MI))
2023 if (!TestMO.
isImm()) {
2024 report(
"floating-point class set (operand 2) must be an immediate",
MI);
2029 report(
"Incorrect floating-point class set (operand 2)",
MI);
2034 case TargetOpcode::G_PREFETCH: {
2036 if (!AddrOp.
isReg() || !
MRI->getType(AddrOp.
getReg()).isPointer()) {
2037 report(
"addr operand must be a pointer", &AddrOp, 0);
2042 report(
"rw operand must be an immediate 0-1", &RWOp, 1);
2047 report(
"locality operand must be an immediate 0-3", &LocalityOp, 2);
2052 report(
"cache type operand must be an immediate 0-1", &CacheTypeOp, 3);
2057 case TargetOpcode::G_ASSERT_ALIGN: {
2058 if (
MI->getOperand(2).getImm() < 1)
2059 report(
"alignment immediate must be >= 1",
MI);
2062 case TargetOpcode::G_CONSTANT_POOL: {
2063 if (!
MI->getOperand(1).isCPI())
2064 report(
"Src operand 1 must be a constant pool index",
MI);
2065 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
2066 report(
"Dst operand 0 must be a pointer",
MI);
2074void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *
MI) {
2077 report(
"Too few operands",
MI);
2079 <<
MI->getNumOperands() <<
" given.\n";
2083 report(
"NoConvergent flag expected only on convergent instructions.",
MI);
2086 if (MF->getProperties().hasProperty(
2088 report(
"Found PHI instruction with NoPHIs property set",
MI);
2091 report(
"Found PHI instruction after non-PHI",
MI);
2092 }
else if (FirstNonPHI ==
nullptr)
2096 if (
MI->isInlineAsm())
2097 verifyInlineAsm(
MI);
2100 if (
TII->isUnspillableTerminator(
MI)) {
2101 if (!
MI->getOperand(0).isReg() || !
MI->getOperand(0).isDef())
2102 report(
"Unspillable Terminator does not define a reg",
MI);
2104 if (
Def.isVirtual() &&
2105 !MF->getProperties().hasProperty(
2107 std::distance(
MRI->use_nodbg_begin(Def),
MRI->use_nodbg_end()) > 1)
2108 report(
"Unspillable Terminator expected to have at most one use!",
MI);
2114 if (
MI->isDebugValue() &&
MI->getNumOperands() == 4)
2115 if (!
MI->getDebugLoc())
2116 report(
"Missing DebugLoc for debug instruction",
MI);
2120 if (
MI->isMetaInstruction() &&
MI->peekDebugInstrNum())
2121 report(
"Metadata instruction should not have a value tracking number",
MI);
2125 if (
Op->isLoad() && !
MI->mayLoad())
2126 report(
"Missing mayLoad flag",
MI);
2127 if (
Op->isStore() && !
MI->mayStore())
2128 report(
"Missing mayStore flag",
MI);
2135 if (
MI->isDebugOrPseudoInstr()) {
2137 report(
"Debug instruction has a slot index",
MI);
2138 }
else if (
MI->isInsideBundle()) {
2140 report(
"Instruction inside bundle has a slot index",
MI);
2143 report(
"Missing slot index",
MI);
2149 verifyPreISelGenericInstruction(
MI);
2158 switch (
MI->getOpcode()) {
2159 case TargetOpcode::COPY: {
2165 LLT DstTy =
MRI->getType(DstReg);
2166 LLT SrcTy =
MRI->getType(SrcReg);
2169 if (SrcTy != DstTy) {
2170 report(
"Copy Instruction is illegal with mismatching types",
MI);
2171 errs() <<
"Def = " << DstTy <<
", Src = " << SrcTy <<
"\n";
2186 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
2188 SrcSize =
TRI->getRegSizeInBits(*SrcRC);
2193 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
2195 DstSize =
TRI->getRegSizeInBits(*DstRC);
2213 if (!
DstOp.getSubReg() && !
SrcOp.getSubReg()) {
2214 report(
"Copy Instruction is illegal with mismatching sizes",
MI);
2215 errs() <<
"Def Size = " << DstSize <<
", Src Size = " << SrcSize
2221 case TargetOpcode::STATEPOINT: {
2223 if (!
MI->getOperand(SO.getIDPos()).isImm() ||
2224 !
MI->getOperand(SO.getNBytesPos()).isImm() ||
2225 !
MI->getOperand(SO.getNCallArgsPos()).isImm()) {
2226 report(
"meta operands to STATEPOINT not constant!",
MI);
2230 auto VerifyStackMapConstant = [&](
unsigned Offset) {
2231 if (
Offset >=
MI->getNumOperands()) {
2232 report(
"stack map constant to STATEPOINT is out of range!",
MI);
2235 if (!
MI->getOperand(
Offset - 1).isImm() ||
2236 MI->getOperand(
Offset - 1).getImm() != StackMaps::ConstantOp ||
2238 report(
"stack map constant to STATEPOINT not well formed!",
MI);
2240 VerifyStackMapConstant(SO.getCCIdx());
2241 VerifyStackMapConstant(SO.getFlagsIdx());
2242 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
2243 VerifyStackMapConstant(SO.getNumGCPtrIdx());
2244 VerifyStackMapConstant(SO.getNumAllocaIdx());
2245 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
2249 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
2250 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
2251 for (
unsigned Idx = 0;
Idx <
MI->getNumDefs();
Idx++) {
2253 if (!
MI->isRegTiedToUseOperand(
Idx, &UseOpIdx)) {
2254 report(
"STATEPOINT defs expected to be tied",
MI);
2257 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
2258 report(
"STATEPOINT def tied to non-gc operand",
MI);
2265 case TargetOpcode::INSERT_SUBREG: {
2266 unsigned InsertedSize;
2267 if (
unsigned SubIdx =
MI->getOperand(2).getSubReg())
2268 InsertedSize =
TRI->getSubRegIdxSize(SubIdx);
2270 InsertedSize =
TRI->getRegSizeInBits(
MI->getOperand(2).getReg(), *
MRI);
2271 unsigned SubRegSize =
TRI->getSubRegIdxSize(
MI->getOperand(3).getImm());
2272 if (SubRegSize < InsertedSize) {
2273 report(
"INSERT_SUBREG expected inserted value to have equal or lesser "
2274 "size than the subreg it was inserted into",
MI);
2278 case TargetOpcode::REG_SEQUENCE: {
2279 unsigned NumOps =
MI->getNumOperands();
2280 if (!(NumOps & 1)) {
2281 report(
"Invalid number of operands for REG_SEQUENCE",
MI);
2285 for (
unsigned I = 1;
I != NumOps;
I += 2) {
2290 report(
"Invalid register operand for REG_SEQUENCE", &RegOp,
I);
2292 if (!SubRegOp.
isImm() || SubRegOp.
getImm() == 0 ||
2293 SubRegOp.
getImm() >=
TRI->getNumSubRegIndices()) {
2294 report(
"Invalid subregister index operand for REG_SEQUENCE",
2299 Register DstReg =
MI->getOperand(0).getReg();
2301 report(
"REG_SEQUENCE does not support physical register results",
MI);
2303 if (
MI->getOperand(0).getSubReg())
2304 report(
"Invalid subreg result for REG_SEQUENCE",
MI);
2312MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
2316 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
2317 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
2320 if (MONum < NumDefs) {
2323 report(
"Explicit definition must be a register", MO, MONum);
2325 report(
"Explicit definition marked as use", MO, MONum);
2327 report(
"Explicit definition marked as implicit", MO, MONum);
2336 report(
"Explicit operand marked as def", MO, MONum);
2338 report(
"Explicit operand marked as implicit", MO, MONum);
2344 report(
"Expected a register operand.", MO, MONum);
2348 !
TII->isPCRelRegisterOperandLegal(*MO)))
2349 report(
"Expected a non-register operand.", MO, MONum);
2356 report(
"Tied use must be a register", MO, MONum);
2358 report(
"Operand should be tied", MO, MONum);
2359 else if (
unsigned(TiedTo) !=
MI->findTiedOperandIdx(MONum))
2360 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
2363 if (!MOTied.
isReg())
2364 report(
"Tied counterpart must be a register", &MOTied, TiedTo);
2367 report(
"Tied physical registers must match.", &MOTied, TiedTo);
2370 report(
"Explicit operand should not be tied", MO, MONum);
2371 }
else if (!
MI->isVariadic()) {
2374 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
2381 if (
MI->isDebugInstr() && MO->
isUse()) {
2383 report(
"Register operand must be marked debug", MO, MONum);
2385 report(
"Register operand must not be marked debug", MO, MONum);
2391 if (
MRI->tracksLiveness() && !
MI->isDebugInstr())
2392 checkLiveness(MO, MONum);
2396 report(
"Undef virtual register def operands require a subregister", MO, MONum);
2400 unsigned OtherIdx =
MI->findTiedOperandIdx(MONum);
2402 if (!OtherMO.
isReg())
2403 report(
"Must be tied to a register", MO, MONum);
2405 report(
"Missing tie flags on tied operand", MO, MONum);
2406 if (
MI->findTiedOperandIdx(OtherIdx) != MONum)
2407 report(
"Inconsistent tie links", MO, MONum);
2411 report(
"Explicit def tied to explicit use without tie constraint",
2415 report(
"Explicit def should be tied to implicit use", MO, MONum);
2428 if (MF->getProperties().hasProperty(
2430 MO->
isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2431 Reg !=
MI->getOperand(DefIdx).getReg())
2432 report(
"Two-address instruction operands must be identical", MO, MONum);
2437 if (
Reg.isPhysical()) {
2439 report(
"Illegal subregister index for physical register", MO, MONum);
2444 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2445 if (!DRC->contains(Reg)) {
2446 report(
"Illegal physical register for instruction", MO, MONum);
2448 <<
TRI->getRegClassName(DRC) <<
" register.\n";
2453 if (
MRI->isReserved(Reg)) {
2454 report(
"isRenamable set on reserved register", MO, MONum);
2471 report(
"Generic virtual register use cannot be undef", MO, MONum);
2478 if (isFunctionTracksDebugUserValues || !MO->
isUse() ||
2479 !
MI->isDebugValue() || !
MRI->def_empty(Reg)) {
2481 if (isFunctionSelected) {
2482 report(
"Generic virtual register invalid in a Selected function",
2488 LLT Ty =
MRI->getType(Reg);
2490 report(
"Generic virtual register must have a valid type", MO,
2499 if (!RegBank && isFunctionRegBankSelected) {
2500 report(
"Generic virtual register must have a bank in a "
2501 "RegBankSelected function",
2509 report(
"Register bank is too small for virtual register", MO,
2511 errs() <<
"Register bank " << RegBank->
getName() <<
" too small("
2519 report(
"Generic virtual register does not allow subregister index", MO,
2529 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2530 report(
"Virtual register does not match instruction constraint", MO,
2532 errs() <<
"Expect register class "
2533 <<
TRI->getRegClassName(
2534 TII->getRegClass(MCID, MONum,
TRI, *MF))
2535 <<
" but got nothing\n";
2543 TRI->getSubClassWithSubReg(RC, SubIdx);
2545 report(
"Invalid subregister index for virtual register", MO, MONum);
2546 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2547 <<
" does not support subreg index " << SubIdx <<
"\n";
2551 report(
"Invalid register class for subregister index", MO, MONum);
2552 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2553 <<
" does not fully support subreg index " << SubIdx <<
"\n";
2559 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2562 TRI->getLargestLegalSuperClass(RC, *MF);
2564 report(
"No largest legal super class exists.", MO, MONum);
2567 DRC =
TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2569 report(
"No matching super-reg register class.", MO, MONum);
2574 report(
"Illegal virtual register for instruction", MO, MONum);
2575 errs() <<
"Expected a " <<
TRI->getRegClassName(DRC)
2576 <<
" register, but got a " <<
TRI->getRegClassName(RC)
2591 report(
"PHI operand is not in the CFG", MO, MONum);
2602 bool loads =
MI->mayLoad();
2607 for (
auto *MMO :
MI->memoperands()) {
2609 if (PSV ==
nullptr)
continue;
2611 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2612 if (
Value ==
nullptr)
continue;
2613 if (
Value->getFrameIndex() != FI)
continue;
2622 report(
"Missing fixed stack memoperand.",
MI);
2624 if (loads && !LI.
liveAt(
Idx.getRegSlot(
true))) {
2625 report(
"Instruction loads from dead spill slot", MO, MONum);
2626 errs() <<
"Live stack: " << LI <<
'\n';
2629 report(
"Instruction stores to dead spill slot", MO, MONum);
2630 errs() <<
"Live stack: " << LI <<
'\n';
2636 if (MO->
getCFIIndex() >= MF->getFrameInstructions().size())
2637 report(
"CFI instruction has invalid index", MO, MONum);
2645void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
2656 report(
"No live segment at use", MO, MONum);
2657 report_context_liverange(LR);
2658 report_context_vreg_regunit(VRegOrUnit);
2659 report_context(UseIdx);
2662 report(
"Live range continues after kill flag", MO, MONum);
2663 report_context_liverange(LR);
2664 report_context_vreg_regunit(VRegOrUnit);
2666 report_context_lanemask(LaneMask);
2667 report_context(UseIdx);
2671void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
2686 if (((SubRangeCheck || MO->
getSubReg() == 0) && VNI->def != DefIdx) ||
2688 (VNI->def != DefIdx &&
2689 (!VNI->def.isEarlyClobber() || !DefIdx.
isRegister()))) {
2690 report(
"Inconsistent valno->def", MO, MONum);
2691 report_context_liverange(LR);
2692 report_context_vreg_regunit(VRegOrUnit);
2694 report_context_lanemask(LaneMask);
2695 report_context(*VNI);
2696 report_context(DefIdx);
2699 report(
"No live segment at def", MO, MONum);
2700 report_context_liverange(LR);
2701 report_context_vreg_regunit(VRegOrUnit);
2703 report_context_lanemask(LaneMask);
2704 report_context(DefIdx);
2716 if (SubRangeCheck || MO->
getSubReg() == 0) {
2717 report(
"Live range continues after dead def flag", MO, MONum);
2718 report_context_liverange(LR);
2719 report_context_vreg_regunit(VRegOrUnit);
2721 report_context_lanemask(LaneMask);
2727void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
2730 const unsigned SubRegIdx = MO->
getSubReg();
2733 if (LiveInts &&
Reg.isVirtual()) {
2738 report(
"Live interval for subreg operand has no subranges", MO, MONum);
2740 report(
"Virtual register has no live interval", MO, MONum);
2747 addRegWithSubRegs(regsKilled, Reg);
2752 if (LiveVars &&
Reg.isVirtual() && MO->
isKill() &&
2753 !
MI->isBundledWithPred()) {
2756 report(
"Kill missing from LiveVariables", MO, MONum);
2770 if (
Reg.isPhysical() && !isReserved(Reg)) {
2772 if (
MRI->isReservedRegUnit(Unit))
2775 checkLivenessAtUse(MO, MONum, UseIdx, *LR, Unit);
2779 if (
Reg.isVirtual()) {
2781 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2785 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2786 :
MRI->getMaxLaneMaskForVReg(Reg);
2789 if ((MOMask & SR.LaneMask).none())
2791 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2794 LiveInMask |= SR.LaneMask;
2797 if ((LiveInMask & MOMask).
none()) {
2798 report(
"No live subrange at use", MO, MONum);
2799 report_context(*LI);
2800 report_context(UseIdx);
2803 if (
MI->isPHI() && LiveInMask != MOMask) {
2804 report(
"Not all lanes of PHI source live at use", MO, MONum);
2805 report_context(*LI);
2806 report_context(UseIdx);
2813 if (!regsLive.count(Reg)) {
2814 if (
Reg.isPhysical()) {
2816 bool Bad = !isReserved(Reg);
2821 if (regsLive.count(
SubReg)) {
2833 if (!MOP.isReg() || !MOP.isImplicit())
2836 if (!MOP.getReg().isPhysical())
2844 report(
"Using an undefined physical register", MO, MONum);
2845 }
else if (
MRI->def_empty(Reg)) {
2846 report(
"Reading virtual register without a def", MO, MONum);
2848 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2852 if (MInfo.regsKilled.count(Reg))
2853 report(
"Using a killed virtual register", MO, MONum);
2854 else if (!
MI->isPHI())
2855 MInfo.vregsLiveIn.insert(std::make_pair(Reg,
MI));
2864 addRegWithSubRegs(regsDead, Reg);
2866 addRegWithSubRegs(regsDefined, Reg);
2869 if (
MRI->isSSA() &&
Reg.isVirtual() &&
2870 std::next(
MRI->def_begin(Reg)) !=
MRI->def_end())
2871 report(
"Multiple virtual register defs in SSA form", MO, MONum);
2878 if (
Reg.isVirtual()) {
2879 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2883 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2884 :
MRI->getMaxLaneMaskForVReg(Reg);
2886 if ((SR.LaneMask & MOMask).none())
2888 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg,
true, SR.LaneMask);
2900void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *
MI) {
2901 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2902 set_union(MInfo.regsKilled, regsKilled);
2903 set_subtract(regsLive, regsKilled); regsKilled.clear();
2905 while (!regMasks.empty()) {
2908 if (
Reg.isPhysical() &&
2910 regsDead.push_back(Reg);
2913 set_union(regsLive, regsDefined); regsDefined.clear();
2918 MBBInfoMap[
MBB].regsLiveOut = regsLive;
2923 if (!(stop > lastIndex)) {
2924 report(
"Block ends before last instruction index",
MBB);
2925 errs() <<
"Block ends at " << stop
2926 <<
" last instruction was at " << lastIndex <<
'\n';
2941 template <
typename RegSetT>
void add(
const RegSetT &FromRegSet) {
2943 filterAndAdd(FromRegSet, VRegsBuffer);
2948 template <
typename RegSetT>
2949 bool filterAndAdd(
const RegSetT &FromRegSet,
2951 unsigned SparseUniverse = Sparse.size();
2952 unsigned NewSparseUniverse = SparseUniverse;
2953 unsigned NewDenseSize =
Dense.size();
2954 size_t Begin = ToVRegs.
size();
2956 if (!
Reg.isVirtual())
2959 if (
Index < SparseUniverseMax) {
2960 if (
Index < SparseUniverse && Sparse.test(
Index))
2962 NewSparseUniverse = std::max(NewSparseUniverse,
Index + 1);
2977 Sparse.resize(NewSparseUniverse);
2978 Dense.reserve(NewDenseSize);
2979 for (
unsigned I = Begin;
I <
End; ++
I) {
2982 if (
Index < SparseUniverseMax)
2991 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
3011class FilteringVRegSet {
3018 template <
typename RegSetT>
void addToFilter(
const RegSetT &RS) {
3023 template <
typename RegSetT>
bool add(
const RegSetT &RS) {
3026 return Filter.filterAndAdd(RS, VRegs);
3031 size_t size()
const {
return VRegs.
size(); }
3038void MachineVerifier::calcRegsPassed() {
3045 FilteringVRegSet VRegs;
3046 BBInfo &
Info = MBBInfoMap[MB];
3049 VRegs.addToFilter(
Info.regsKilled);
3050 VRegs.addToFilter(
Info.regsLiveOut);
3052 const BBInfo &PredInfo = MBBInfoMap[Pred];
3053 if (!PredInfo.reachable)
3056 VRegs.add(PredInfo.regsLiveOut);
3057 VRegs.add(PredInfo.vregsPassed);
3059 Info.vregsPassed.reserve(VRegs.size());
3060 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
3067void MachineVerifier::calcRegsRequired() {
3070 for (
const auto &
MBB : *MF) {
3071 BBInfo &MInfo = MBBInfoMap[&
MBB];
3073 BBInfo &PInfo = MBBInfoMap[Pred];
3074 if (PInfo.addRequired(MInfo.vregsLiveIn))
3080 for (
unsigned i = 1, e =
MI.getNumOperands(); i != e; i += 2) {
3082 if (!
MI.getOperand(i).isReg() || !
MI.getOperand(i).readsReg())
3089 BBInfo &PInfo = MBBInfoMap[Pred];
3090 if (PInfo.addRequired(Reg))
3098 while (!todo.
empty()) {
3101 BBInfo &MInfo = MBBInfoMap[
MBB];
3105 BBInfo &SInfo = MBBInfoMap[Pred];
3106 if (SInfo.addRequired(MInfo.vregsRequired))
3115 BBInfo &MInfo = MBBInfoMap[&
MBB];
3125 report(
"Expected first PHI operand to be a register def", &MODef, 0);
3130 report(
"Unexpected flag on PHI operand", &MODef, 0);
3133 report(
"Expected first PHI operand to be a virtual register", &MODef, 0);
3135 for (
unsigned I = 1, E =
Phi.getNumOperands();
I != E;
I += 2) {
3138 report(
"Expected PHI operand to be a register", &MO0,
I);
3143 report(
"Unexpected flag on PHI operand", &MO0,
I);
3147 report(
"Expected PHI operand to be a basic block", &MO1,
I + 1);
3153 report(
"PHI input is not a predecessor block", &MO1,
I + 1);
3157 if (MInfo.reachable) {
3159 BBInfo &PrInfo = MBBInfoMap[&Pre];
3160 if (!MO0.
isUndef() && PrInfo.reachable &&
3161 !PrInfo.isLiveOut(MO0.
getReg()))
3162 report(
"PHI operand is not live-out from predecessor", &MO0,
I);
3167 if (MInfo.reachable) {
3169 if (!seen.
count(Pred)) {
3170 report(
"Missing PHI operand", &Phi);
3172 <<
" is a predecessor according to the CFG.\n";
3181 std::function<
void(
const Twine &Message)> FailureCB) {
3185 for (
const auto &
MBB : MF) {
3197void MachineVerifier::visitMachineFunctionAfter() {
3198 auto FailureCB = [
this](
const Twine &Message) {
3199 report(Message.str().c_str(), MF);
3212 for (
const auto &
MBB : *MF) {
3213 BBInfo &MInfo = MBBInfoMap[&
MBB];
3214 for (
Register VReg : MInfo.vregsRequired)
3215 if (MInfo.regsKilled.count(VReg)) {
3216 report(
"Virtual register killed in block, but needed live out.", &
MBB);
3218 <<
" is used after the block.\n";
3223 BBInfo &MInfo = MBBInfoMap[&MF->front()];
3224 for (
Register VReg : MInfo.vregsRequired) {
3225 report(
"Virtual register defs don't dominate all uses.", MF);
3226 report_context_vreg(VReg);
3231 verifyLiveVariables();
3233 verifyLiveIntervals();
3242 if (
MRI->tracksLiveness())
3243 for (
const auto &
MBB : *MF)
3247 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
3250 BBInfo &PInfo = MBBInfoMap[Pred];
3251 if (!PInfo.regsLiveOut.count(LiveInReg)) {
3252 report(
"Live in register not found to be live out from predecessor.",
3254 errs() <<
TRI->getName(LiveInReg)
3255 <<
" not found to be live out from "
3261 for (
auto CSInfo : MF->getCallSitesInfo())
3262 if (!CSInfo.first->isCall())
3263 report(
"Call site info referencing instruction that is not call", MF);
3267 if (MF->getFunction().getSubprogram()) {
3269 for (
const auto &
MBB : *MF) {
3270 for (
const auto &
MI :
MBB) {
3271 if (
auto Num =
MI.peekDebugInstrNum()) {
3274 report(
"Instruction has a duplicated value tracking number", &
MI);
3281void MachineVerifier::verifyLiveVariables() {
3282 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
3283 for (
unsigned I = 0, E =
MRI->getNumVirtRegs();
I != E; ++
I) {
3286 for (
const auto &
MBB : *MF) {
3287 BBInfo &MInfo = MBBInfoMap[&
MBB];
3290 if (MInfo.vregsRequired.count(Reg)) {
3292 report(
"LiveVariables: Block missing from AliveBlocks", &
MBB);
3294 <<
" must be live through the block.\n";
3298 report(
"LiveVariables: Block should not be in AliveBlocks", &
MBB);
3300 <<
" is not needed live through the block.\n";
3307void MachineVerifier::verifyLiveIntervals() {
3308 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
3309 for (
unsigned I = 0, E =
MRI->getNumVirtRegs();
I != E; ++
I) {
3313 if (
MRI->reg_nodbg_empty(Reg))
3317 report(
"Missing live interval for virtual register", MF);
3323 assert(Reg == LI.
reg() &&
"Invalid reg to interval mapping");
3324 verifyLiveInterval(LI);
3328 for (
unsigned i = 0, e =
TRI->getNumRegUnits(); i != e; ++i)
3330 verifyLiveRange(*LR, i);
3333void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
3342 report(
"Value not live at VNInfo def and not marked unused", MF);
3343 report_context(LR, Reg, LaneMask);
3344 report_context(*VNI);
3348 if (DefVNI != VNI) {
3349 report(
"Live segment at def has different VNInfo", MF);
3350 report_context(LR, Reg, LaneMask);
3351 report_context(*VNI);
3357 report(
"Invalid VNInfo definition index", MF);
3358 report_context(LR, Reg, LaneMask);
3359 report_context(*VNI);
3365 report(
"PHIDef VNInfo is not defined at MBB start",
MBB);
3366 report_context(LR, Reg, LaneMask);
3367 report_context(*VNI);
3375 report(
"No instruction at VNInfo def index",
MBB);
3376 report_context(LR, Reg, LaneMask);
3377 report_context(*VNI);
3382 bool hasDef =
false;
3383 bool isEarlyClobber =
false;
3385 if (!MOI->isReg() || !MOI->isDef())
3387 if (
Reg.isVirtual()) {
3388 if (MOI->getReg() != Reg)
3391 if (!MOI->getReg().isPhysical() || !
TRI->hasRegUnit(MOI->getReg(), Reg))
3394 if (LaneMask.
any() &&
3395 (
TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3398 if (MOI->isEarlyClobber())
3399 isEarlyClobber =
true;
3403 report(
"Defining instruction does not modify register",
MI);
3404 report_context(LR, Reg, LaneMask);
3405 report_context(*VNI);
3410 if (isEarlyClobber) {
3412 report(
"Early clobber def must be at an early-clobber slot",
MBB);
3413 report_context(LR, Reg, LaneMask);
3414 report_context(*VNI);
3417 report(
"Non-PHI, non-early clobber def must be at a register slot",
MBB);
3418 report_context(LR, Reg, LaneMask);
3419 report_context(*VNI);
3424void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
3430 assert(VNI &&
"Live segment has no valno");
3433 report(
"Foreign valno in live segment", MF);
3434 report_context(LR, Reg, LaneMask);
3436 report_context(*VNI);
3440 report(
"Live segment valno is marked unused", MF);
3441 report_context(LR, Reg, LaneMask);
3447 report(
"Bad start of live segment, no basic block", MF);
3448 report_context(LR, Reg, LaneMask);
3454 report(
"Live segment must begin at MBB entry or valno def",
MBB);
3455 report_context(LR, Reg, LaneMask);
3462 report(
"Bad end of live segment, no basic block", MF);
3463 report_context(LR, Reg, LaneMask);
3479 report(
"Live segment doesn't end at a valid instruction", EndMBB);
3480 report_context(LR, Reg, LaneMask);
3487 report(
"Live segment ends at B slot of an instruction", EndMBB);
3488 report_context(LR, Reg, LaneMask);
3496 report(
"Live segment ending at dead slot spans instructions", EndMBB);
3497 report_context(LR, Reg, LaneMask);
3506 if (MF->getProperties().hasProperty(
3509 if (
I + 1 == LR.
end() || (
I + 1)->start != S.
end) {
3510 report(
"Live segment ending at early clobber slot must be "
3511 "redefined by an EC def in the same instruction",
3513 report_context(LR, Reg, LaneMask);
3520 if (
Reg.isVirtual()) {
3523 bool hasRead =
false;
3524 bool hasSubRegDef =
false;
3525 bool hasDeadDef =
false;
3527 if (!MOI->isReg() || MOI->getReg() != Reg)
3529 unsigned Sub = MOI->getSubReg();
3534 hasSubRegDef =
true;
3543 if (LaneMask.
any() && (LaneMask & SLM).none())
3545 if (MOI->readsReg())
3552 if (LaneMask.
none() && !hasDeadDef) {
3554 "Instruction ending live segment on dead slot has no dead flag",
3556 report_context(LR, Reg, LaneMask);
3563 if (!
MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.
any() ||
3565 report(
"Instruction ending live segment doesn't read the register",
3567 report_context(LR, Reg, LaneMask);
3587 if (LaneMask.
any()) {
3595 if (!
Reg.isVirtual() && MFI->isEHPad()) {
3596 if (&*MFI == EndMBB)
3610 if (MFI->isEHPad()) {
3624 if (!PVNI && (LaneMask.
none() || !IsPHI)) {
3627 report(
"Register not marked live out of predecessor", Pred);
3628 report_context(LR, Reg, LaneMask);
3629 report_context(*VNI);
3637 if (!IsPHI && PVNI != VNI) {
3638 report(
"Different value live out of predecessor", Pred);
3639 report_context(LR, Reg, LaneMask);
3640 errs() <<
"Valno #" << PVNI->
id <<
" live out of "
3646 if (&*MFI == EndMBB)
3655 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3658 verifyLiveRangeSegment(LR,
I, Reg, LaneMask);
3661void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
3664 verifyLiveRange(LI, Reg);
3670 if ((Mask & SR.LaneMask).any()) {
3671 report(
"Lane masks of sub ranges overlap in live interval", MF);
3674 if ((SR.LaneMask & ~MaxMask).any()) {
3675 report(
"Subrange lanemask is invalid", MF);
3679 report(
"Subrange must not be empty", MF);
3680 report_context(SR, LI.
reg(), SR.LaneMask);
3682 Mask |= SR.LaneMask;
3683 verifyLiveRange(SR, LI.
reg(), SR.LaneMask);
3685 report(
"A Subrange is not covered by the main range", MF);
3693 unsigned NumComp = ConEQ.Classify(LI);
3695 report(
"Multiple connected components in live interval", MF);
3697 for (
unsigned comp = 0; comp != NumComp; ++comp) {
3698 errs() << comp <<
": valnos";
3700 if (comp == ConEQ.getEqClass(
I))
3701 errs() <<
' ' <<
I->id;
3713 struct StackStateOfBB {
3714 StackStateOfBB() =
default;
3715 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
3716 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3717 ExitIsSetup(ExitSetup) {}
3722 bool EntryIsSetup =
false;
3723 bool ExitIsSetup =
false;
3731void MachineVerifier::verifyStackFrame() {
3732 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
3733 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
3734 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3738 SPState.
resize(MF->getNumBlockIDs());
3745 DFI != DFE; ++DFI) {
3748 StackStateOfBB BBState;
3750 if (DFI.getPathLength() >= 2) {
3753 "DFS stack predecessor is already visited.\n");
3754 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
3755 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
3756 BBState.ExitValue = BBState.EntryValue;
3757 BBState.ExitIsSetup = BBState.EntryIsSetup;
3761 report(
"Call frame size on entry does not match value computed from "
3765 <<
" does not match value computed from predecessor "
3766 << -BBState.EntryValue <<
'\n';
3770 for (
const auto &
I : *
MBB) {
3771 if (
I.getOpcode() == FrameSetupOpcode) {
3772 if (BBState.ExitIsSetup)
3773 report(
"FrameSetup is after another FrameSetup", &
I);
3774 if (!
MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
3775 report(
"AdjustsStack not set in presence of a frame pseudo "
3776 "instruction.", &
I);
3777 BBState.ExitValue -=
TII->getFrameTotalSize(
I);
3778 BBState.ExitIsSetup =
true;
3781 if (
I.getOpcode() == FrameDestroyOpcode) {
3782 int Size =
TII->getFrameTotalSize(
I);
3783 if (!BBState.ExitIsSetup)
3784 report(
"FrameDestroy is not after a FrameSetup", &
I);
3785 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3787 if (BBState.ExitIsSetup && AbsSPAdj !=
Size) {
3788 report(
"FrameDestroy <n> is after FrameSetup <m>", &
I);
3789 errs() <<
"FrameDestroy <" <<
Size <<
"> is after FrameSetup <"
3790 << AbsSPAdj <<
">.\n";
3792 if (!
MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
3793 report(
"AdjustsStack not set in presence of a frame pseudo "
3794 "instruction.", &
I);
3795 BBState.ExitValue +=
Size;
3796 BBState.ExitIsSetup =
false;
3804 if (Reachable.
count(Pred) &&
3805 (SPState[Pred->
getNumber()].ExitValue != BBState.EntryValue ||
3806 SPState[Pred->
getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3807 report(
"The exit stack state of a predecessor is inconsistent.",
MBB);
3809 <<
" has exit state (" << SPState[Pred->
getNumber()].ExitValue
3810 <<
", " << SPState[Pred->
getNumber()].ExitIsSetup <<
"), while "
3812 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
3819 if (Reachable.
count(Succ) &&
3820 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3821 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3822 report(
"The entry stack state of a successor is inconsistent.",
MBB);
3824 <<
" has entry state (" << SPState[Succ->getNumber()].EntryValue
3825 <<
", " << SPState[Succ->getNumber()].EntryIsSetup <<
"), while "
3827 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
3833 if (BBState.ExitIsSetup)
3834 report(
"A return block ends with a FrameSetup.",
MBB);
3835 if (BBState.ExitValue)
3836 report(
"A return block ends with a nonzero stack adjustment.",
MBB);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
This file implements the BitVector class.
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
This file declares the MIR specialization of the GenericConvergenceVerifier template.
unsigned const TargetRegisterInfo * TRI
static void verifyConvergenceControl(const MachineFunction &MF, MachineDomTree &DT, std::function< void(const Twine &Message)> FailureCB)
modulo schedule Modulo Schedule test pass
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file describes how to lower LLVM code to machine code.
static unsigned getSize(unsigned Kind)
const fltSemantics & getSemantics() const
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool test(unsigned Idx) const
void clear()
clear - Removes all bits from the bitvector.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
Core dominator tree base class.
void recalculate(ParentType &Func)
recalculate - compute a dominator tree for the given function
Base class for user error types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
void initialize(raw_ostream *OS, function_ref< void(const Twine &Message)> FailureCB, const FunctionT &F)
void verify(const DominatorTreeT &DT)
void visit(const BlockT &BB)
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr unsigned getAddressSpace() const
constexpr bool isPointerOrPointerVector() const
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
bool liveAt(SlotIndex index) const
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
LiveInterval & getInterval(int Slot)
bool hasInterval(int Slot) const
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
TypeSize getValue() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool isConvergent() const
Return true if this instruction is convergent.
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isOptionalDef() const
Set if this operand is a optional def.
uint8_t OperandType
Information about the type of the operand.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
succ_iterator succ_begin()
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
pred_iterator pred_begin()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getCallFrameSize() const
Return the call frame size on entry to this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
BasicBlockListType::const_iterator const_iterator
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isReturn(QueryType Type=AnyInBundle) const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
LocationSize getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
const char * getName() const
Get a user friendly name of this register bank.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
constexpr bool isNonZero() const
static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< PhiNode * > Phi
NodeAddr< DefNode * > Def
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void initializeMachineVerifierPassPass(PassRegistry &)
void verifyMachineFunction(const std::string &Banner, const MachineFunction &MF)
auto reverse(ContainerTy &&C)
detail::ValueMatchesPoly< M > HasValue(M Matcher)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
Implement std::hash so that hash_code can be used in STL containers.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
Pair of physical register and lane mask.