46 RISCV::X1, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19,
47 RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24,
48 RISCV::X25, RISCV::X26, RISCV::X27};
70 if (!STI.hasForcedSWShadowStack() && STI.hasStdExtZicfiss()) {
77 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
78 int64_t SlotSize = STI.getXLen() / 8;
95 char DwarfSCSReg =
TRI->getDwarfRegNum(SCSPReg,
true);
96 assert(DwarfSCSReg < 32 &&
"SCS Register should be < 32 (X3).");
98 char Offset =
static_cast<char>(-SlotSize) & 0x7f;
99 const char CFIInst[] = {
100 dwarf::DW_CFA_val_expression,
103 static_cast<char>(
unsigned(dwarf::DW_OP_breg0 + DwarfSCSReg)),
108 nullptr,
StringRef(CFIInst,
sizeof(CFIInst))));
121 Register RAReg = STI.getRegisterInfo()->getRARegister();
130 if (!STI.hasForcedSWShadowStack() && STI.hasStdExtZicfiss()) {
137 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
138 int64_t SlotSize = STI.getXLen() / 8;
154 nullptr, STI.getRegisterInfo()->getDwarfRegNum(SCSPReg,
true)));
165 const std::vector<CalleeSavedInfo> &CSI) {
168 if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF))
171 Register MaxReg = RISCV::NoRegister;
175 if (CS.getFrameIdx() < 0)
176 MaxReg = std::max(MaxReg.
id(), CS.getReg().id());
178 if (MaxReg == RISCV::NoRegister)
184 case RISCV::X27:
return 12;
185 case RISCV::X26:
return 11;
186 case RISCV::X25:
return 10;
187 case RISCV::X24:
return 9;
188 case RISCV::X23:
return 8;
189 case RISCV::X22:
return 7;
190 case RISCV::X21:
return 6;
191 case RISCV::X20:
return 5;
192 case RISCV::X19:
return 4;
193 case RISCV::X18:
return 3;
194 case RISCV::X9:
return 2;
195 case RISCV::X8:
return 1;
196 case RISCV::X1:
return 0;
204 const std::vector<CalleeSavedInfo> &CSI) {
205 static const char *
const SpillLibCalls[] = {
224 return SpillLibCalls[LibCallID];
231 const std::vector<CalleeSavedInfo> &CSI) {
232 static const char *
const RestoreLibCalls[] = {
243 "__riscv_restore_10",
244 "__riscv_restore_11",
251 return RestoreLibCalls[LibCallID];
256static std::pair<unsigned, unsigned>
291 const std::vector<CalleeSavedInfo> &CSI) {
292 Register MaxPushPopReg = RISCV::NoRegister;
293 for (
auto &CS : CSI) {
295 MaxPushPopReg = std::max(MaxPushPopReg.
id(), CS.getReg().id());
298 if (MaxPushPopReg == RISCV::X26)
299 MaxPushPopReg = RISCV::X27;
300 return MaxPushPopReg;
327 TRI->hasStackRealignment(MF);
331void RISCVFrameLowering::determineFrameLayout(
MachineFunction &MF)
const {
342 FrameSize =
alignTo(FrameSize, StackAlign);
352 if (RVFI->getRVVStackSize() && (!
hasFP(MF) ||
TRI->hasStackRealignment(MF))) {
353 int ScalarLocalVarSize = FrameSize - RVFI->getCalleeSavedStackSize() -
354 RVFI->getVarArgsSaveSize();
355 if (
auto RVVPadding =
357 RVFI->setRVVPadding(RVVPadding);
378 const std::vector<CalleeSavedInfo> &CSI) {
382 for (
auto &CS : CSI) {
383 int FI = CS.getFrameIdx();
388 return NonLibcallCSI;
393 const std::vector<CalleeSavedInfo> &CSI) {
397 for (
auto &CS : CSI) {
398 int FI = CS.getFrameIdx();
411 assert(Amount != 0 &&
"Did not need to adjust stack pointer for RVV.");
419 const int64_t VLENB = *VLEN / 8;
421 "Reserve the stack by the multiple of one vector size.");
422 const int64_t NumOfVReg = Amount / 8;
423 const int64_t FixedOffset = NumOfVReg * VLENB;
424 if (!isInt<32>(FixedOffset)) {
426 "Frame size outside of the signed 32-bit range not supported");
440 int FixedOffset,
int ScalableOffset,
442 unsigned DwarfVLenB =
TRI.getDwarfRegNum(RISCV::VLENB,
true);
447 Expr.
push_back((uint8_t)dwarf::DW_OP_plus);
448 Comment << (FixedOffset < 0 ?
" - " :
" + ") << std::abs(FixedOffset);
451 Expr.
push_back((uint8_t)dwarf::DW_OP_consts);
454 Expr.
push_back((uint8_t)dwarf::DW_OP_bregx);
458 Expr.
push_back((uint8_t)dwarf::DW_OP_mul);
459 Expr.
push_back((uint8_t)dwarf::DW_OP_plus);
461 Comment << (ScalableOffset < 0 ?
" - " :
" + ") << std::abs(ScalableOffset)
469 assert(ScalableOffset != 0 &&
"Did not need to adjust CFA for RVV");
471 std::string CommentBuffer;
474 unsigned DwarfReg =
TRI.getDwarfRegNum(Reg,
true);
475 Expr.
push_back((uint8_t)(dwarf::DW_OP_breg0 + DwarfReg));
477 if (Reg == RISCV::X2)
487 DefCfaExpr.
push_back(dwarf::DW_CFA_def_cfa_expression);
498 assert(ScalableOffset != 0 &&
"Did not need to adjust CFA for RVV");
500 std::string CommentBuffer;
510 unsigned DwarfReg =
TRI.getDwarfRegNum(Reg,
true);
511 DefCfaExpr.
push_back(dwarf::DW_CFA_expression);
544 auto FirstFrameSetup =
MBBI;
552 determineFrameLayout(MF);
576 unsigned LibCallFrameSize =
578 RVFI->setLibCallStackSize(LibCallFrameSize);
584 uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
585 uint64_t RVVStackSize = RVFI->getRVVStackSize();
588 if (RealStackSize == 0 && !MFI.
adjustsStack() && RVVStackSize == 0)
595 MF.
getFunction(),
"Stack pointer required, but has been reserved."});
599 if (FirstSPAdjustAmount) {
600 StackSize = FirstSPAdjustAmount;
601 RealStackSize = FirstSPAdjustAmount;
604 if (RVFI->isPushable(MF) && FirstFrameSetup !=
MBB.
end() &&
605 FirstFrameSetup->getOpcode() == RISCV::CM_PUSH) {
611 FirstFrameSetup->getOperand(1).setImm(Spimm);
615 if (StackSize != 0) {
617 RI->adjustReg(
MBB,
MBBI,
DL, SPReg, SPReg,
641 for (
const auto &Entry : CSI) {
642 int FrameIdx = Entry.getFrameIdx();
650 nullptr, RI->getDwarfRegNum(Reg,
true),
Offset));
660 MF.
getFunction(),
"Frame pointer required, but has been reserved."});
664 RI->adjustReg(
MBB,
MBBI,
DL, FPReg, SPReg,
670 nullptr, RI->getDwarfRegNum(FPReg,
true), RVFI->getVarArgsSaveSize()));
677 if (FirstSPAdjustAmount) {
680 assert(SecondSPAdjustAmount > 0 &&
681 "SecondSPAdjustAmount should be greater than zero");
682 RI->adjustReg(
MBB,
MBBI,
DL, SPReg, SPReg,
699 adjustStackForRVV(MF,
MBB,
MBBI,
DL, -RVVStackSize,
717 if (RI->hasStackRealignment(MF)) {
721 if (isInt<12>(-(
int)MaxAlignment.
value())) {
727 unsigned ShiftAmount =
Log2(MaxAlignment);
789 auto LastFrameDestroy =
MBBI;
791 LastFrameDestroy = std::prev(
MBBI, CSI.
size());
794 uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
795 uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
796 uint64_t RVVStackSize = RVFI->getRVVStackSize();
810 assert(
hasFP(MF) &&
"frame pointer should not have been eliminated");
816 adjustStackForRVV(MF,
MBB, LastFrameDestroy,
DL, RVVStackSize,
821 if (FirstSPAdjustAmount) {
824 assert(SecondSPAdjustAmount > 0 &&
825 "SecondSPAdjustAmount should be greater than zero");
832 if (FirstSPAdjustAmount)
833 StackSize = FirstSPAdjustAmount;
835 if (RVFI->isPushable(MF) &&
MBBI !=
MBB.
end() &&
836 MBBI->getOpcode() == RISCV::CM_POP) {
842 MBBI->getOperand(1).setImm(Spimm);
847 if (StackSize != 0) {
874 "Unexpected stack ID for the frame object.");
886 MinCSFI = CSI[0].getFrameIdx();
887 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
890 if (FI >= MinCSFI && FI <= MaxCSFI) {
891 FrameReg = RISCV::X2;
893 if (FirstSPAdjustAmount)
938 FrameReg = RISCV::X2;
963 "Can't index across variable sized realign");
968 "Inconsistent stack layout");
1011 "Can't index across variable sized realign");
1013 RVFI->getRVVStackSize());
1021 RVFI->getCalleeSavedStackSize() -
1022 RVFI->getRVPushStackSize() -
1023 RVFI->getVarArgsSaveSize() + RVFI->getRVVPadding();
1036 SavedRegs.
set(RISCV::X1);
1037 SavedRegs.
set(RISCV::X8);
1044std::pair<int64_t, Align>
1045RISCVFrameLowering::assignRVVStackObjectOffsets(
MachineFunction &MF)
const {
1049 auto pushRVVObjects = [&](
int FIBegin,
int FIEnd) {
1050 for (
int I = FIBegin, E = FIEnd;
I != E; ++
I) {
1063 if (!RVVCSI.empty())
1064 pushRVVObjects(RVVCSI[0].getFrameIdx(),
1065 RVVCSI[RVVCSI.size() - 1].getFrameIdx() + 1);
1069 Align RVVStackAlign(16);
1072 if (!
ST.hasVInstructions()) {
1074 "Can't allocate scalable-vector objects without V instructions");
1075 return std::make_pair(0, RVVStackAlign);
1080 for (
int FI : ObjectsToAllocate) {
1091 RVVStackAlign = std::max(RVVStackAlign, ObjectAlign);
1099 StackSize += AlignmentPadding;
1100 for (
int FI : ObjectsToAllocate)
1104 return std::make_pair(StackSize, RVVStackAlign);
1110 static constexpr unsigned ScavSlotsNumRVVSpillScalableObject = 2;
1114 static constexpr unsigned ScavSlotsNumRVVSpillNonScalableObject = 1;
1118 static constexpr unsigned ScavSlotsADDIScalableObject = 1;
1120 static constexpr unsigned MaxScavSlotsNumKnown =
1121 std::max({ScavSlotsADDIScalableObject, ScavSlotsNumRVVSpillScalableObject,
1122 ScavSlotsNumRVVSpillNonScalableObject});
1124 unsigned MaxScavSlotsNum = 0;
1130 for (
auto &MO :
MI.operands()) {
1136 MaxScavSlotsNum = std::max(
1137 MaxScavSlotsNum, IsScalableVectorID
1138 ? ScavSlotsNumRVVSpillScalableObject
1139 : ScavSlotsNumRVVSpillNonScalableObject);
1140 }
else if (
MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) {
1142 std::max(MaxScavSlotsNum, ScavSlotsADDIScalableObject);
1145 if (MaxScavSlotsNum == MaxScavSlotsNumKnown)
1146 return MaxScavSlotsNumKnown;
1148 return MaxScavSlotsNum;
1172 unsigned FnSize = 0;
1173 for (
auto &
MBB : MF) {
1174 for (
auto &
MI :
MBB) {
1192 if (
MI.isConditionalBranch())
1193 FnSize +=
TII.getInstSizeInBytes(
MI);
1194 if (
MI.isConditionalBranch() ||
MI.isUnconditionalBranch()) {
1196 FnSize += 2 + 8 + 2 + 2;
1198 FnSize += 4 + 8 + 4 + 4;
1202 FnSize +=
TII.getInstSizeInBytes(
MI);
1217 int64_t RVVStackSize;
1218 Align RVVStackAlign;
1219 std::tie(RVVStackSize, RVVStackAlign) = assignRVVStackObjectOffsets(MF);
1221 RVFI->setRVVStackSize(RVVStackSize);
1222 RVFI->setRVVStackAlign(RVVStackAlign);
1231 unsigned ScavSlotsNum = 0;
1241 if (IsLargeFunction)
1242 ScavSlotsNum = std::max(ScavSlotsNum, 1u);
1249 for (
unsigned I = 0;
I < ScavSlotsNum;
I++) {
1251 RegInfo->getSpillAlign(*RC),
false);
1254 if (IsLargeFunction && RVFI->getBranchRelaxationScratchFrameIndex() == -1)
1255 RVFI->setBranchRelaxationScratchFrameIndex(FI);
1258 unsigned Size = RVFI->getReservedSpillsSize();
1260 int FrameIdx =
Info.getFrameIdx();
1266 RVFI->setCalleeSavedStackSize(
Size);
1291 int64_t Amount =
MI->getOperand(0).getImm();
1297 if (
MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
1330 if (RVFI->getReservedSpillsSize())
1335 if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
1365 auto CanCompress = [&](
uint64_t CompressLen) ->
bool {
1366 if (StackSize <= 2047 + CompressLen ||
1367 (StackSize > 2048 * 2 - StackAlign &&
1368 StackSize <= 2047 * 2 + CompressLen) ||
1369 StackSize > 2048 * 3 - StackAlign)
1377 const uint64_t ADDI16SPCompressLen = 496;
1378 if (
STI.
is64Bit() && CanCompress(ADDI16SPCompressLen))
1379 return ADDI16SPCompressLen;
1380 if (CanCompress(RVCompressLen))
1381 return RVCompressLen;
1383 return 2048 - StackAlign;
1391 { RISCV::X1, -1}, { RISCV::X8, -2},
1392 { RISCV::X9, -3}, { RISCV::X18, -4},
1393 { RISCV::X19, -5}, { RISCV::X20, -6},
1394 { RISCV::X21, -7}, { RISCV::X22, -8},
1395 { RISCV::X23, -9}, { RISCV::X24, -10},
1396 { RISCV::X25, -11}, { RISCV::X26, -12},
1397 { RISCV::X27, -13}};
1401 std::vector<CalleeSavedInfo> &CSI,
unsigned &MinCSFrameIndex,
1402 unsigned &MaxCSFrameIndex)
const {
1409 if (RVFI->isPushable(MF)) {
1412 if (MaxReg != RISCV::NoRegister) {
1414 RVFI->setRVPushRegs(PushedRegNum);
1418 RVFI->setRVPushRlist(RegEnc);
1425 for (
auto &CS : CSI) {
1426 unsigned Reg = CS.getReg();
1431 if (RVFI->useSaveRestoreLibCalls(MF) || RVFI->isPushable(MF)) {
1436 if (RVFI->isPushable(MF))
1437 Offset = -((FII->second + RVFI->getRVPushRegs() + 1) * (int64_t)
Size);
1443 CS.setFrameIdx(FrameIdx);
1455 if ((
unsigned)FrameIdx < MinCSFrameIndex)
1456 MinCSFrameIndex = FrameIdx;
1457 if ((
unsigned)FrameIdx > MaxCSFrameIndex)
1458 MaxCSFrameIndex = FrameIdx;
1459 CS.setFrameIdx(FrameIdx);
1463 if (RVFI->isPushable(MF)) {
1464 if (int64_t PushSize = RVFI->getRVPushStackSize())
1466 }
else if (
int LibCallRegs =
getLibCallID(MF, CSI) + 1) {
1467 int64_t LibCallFrameSize =
1485 DL =
MI->getDebugLoc();
1491 if (PushedRegNum > 0) {
1497 PushBuilder.
addImm((int64_t)RegEnc);
1500 for (
unsigned i = 0; i < PushedRegNum; i++)
1510 for (
auto &CS : CSI)
1518 auto storeRegToStackSlot = [&](
decltype(UnmanagedCSI) CSInfo) {
1519 for (
auto &CS : CSInfo) {
1527 storeRegToStackSlot(UnmanagedCSI);
1528 storeRegToStackSlot(RVVCSI);
1533void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
1551 FixedSize -= ScalarLocalVarSize;
1554 for (
auto &CS : RVVCSI) {
1556 int FI = CS.getFrameIdx();
1578 DL =
MI->getDebugLoc();
1589 auto loadRegFromStackSlot = [&](
decltype(UnmanagedCSI) CSInfo) {
1590 for (
auto &CS : CSInfo) {
1596 "loadRegFromStackSlot didn't insert any code!");
1599 loadRegFromStackSlot(RVVCSI);
1600 loadRegFromStackSlot(UnmanagedCSI);
1610 PopBuilder.
addImm(RegEnc);
1618 if (RestoreLibCall) {
1627 if (
MI !=
MBB.
end() &&
MI->getOpcode() == RISCV::PseudoRET) {
1628 NewMI->copyImplicitOps(*MF, *
MI);
1629 MI->eraseFromParent();
static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &Offset)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Analysis containing CSE Info
static Register getFPReg(const CSKYSubtarget &STI)
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
static uint64_t estimateFunctionSizeInBytes(const LoongArchInstrInfo *TII, const MachineFunction &MF)
unsigned const TargetRegisterInfo * TRI
static const char * getRestoreLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static const char * getSpillLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static bool hasRVVFrameObject(const MachineFunction &MF)
static std::pair< unsigned, unsigned > getPushPopEncodingAndNum(const Register MaxReg)
static const std::pair< MCPhysReg, int8_t > FixedCSRFIMap[]
static SmallVector< CalleeSavedInfo, 8 > getRVVCalleeSavedInfo(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static void appendScalableVectorExpression(const TargetRegisterInfo &TRI, SmallVectorImpl< char > &Expr, int FixedOffset, int ScalableOffset, llvm::raw_string_ostream &Comment)
static Align getABIStackAlignment(RISCVABI::ABI ABI)
static int getLibCallID(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static Register getSPReg(const RISCVSubtarget &STI)
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static SmallVector< CalleeSavedInfo, 8 > getUnmanagedCSI(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static Register getMaxPushPopReg(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static const MCPhysReg AllPopRegs[]
static unsigned getScavSlotsNumForRVV(MachineFunction &MF)
static MCCFIInstruction createDefCFAOffset(const TargetRegisterInfo &TRI, Register Reg, uint64_t FixedOffset, uint64_t ScalableOffset)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Diagnostic information for unsupported feature in backend.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasOptNone() const
Do not optimize this function (-O0).
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
MachineBasicBlock * getFallThrough(bool JumpToFallThrough=true)
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
succ_iterator succ_begin()
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
int getOffsetAdjustment() const
Return the correction for frame offsets.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isMaxCallFrameSizeComputed() const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
uint8_t getStackID(int ObjectIdx) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool hasBP(const MachineFunction &MF) const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI, unsigned &MinCSFrameIndex, unsigned &MaxCSFrameIndex) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
const RISCVSubtarget & STI
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool isSupportedStackID(TargetStackID::Value ID) const override
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
TargetStackID::Value getStackIDForScalableVectors() const override
Returns the StackID that scalable vectors should be associated with.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
RISCVFrameLowering(const RISCVSubtarget &STI)
uint64_t getStackSizeWithRVVPadding(const MachineFunction &MF) const
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool isPushable(const MachineFunction &MF) const
int getRVPushRlist() const
uint64_t getRVVPadding() const
unsigned getRVPushStackSize() const
unsigned getRVPushRegs() const
bool useSaveRestoreLibCalls(const MachineFunction &MF) const
unsigned getVarArgsSaveSize() const
unsigned getCalleeSavedStackSize() const
bool hasStdExtCOrZca() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructions() const
std::optional< unsigned > getRealVLen() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Wrapper class representing virtual and physical registers.
constexpr unsigned id() const
Represents a location in source code.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void append(StringRef RHS)
Append from a StringRef.
StringRef str() const
Explicit conversion to StringRef.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
int64_t getFixed() const
Returns the fixed component of the stack.
int64_t getScalable() const
Returns the scalable component of the stack.
static StackOffset get(int64_t Fixed, int64_t Scalable)
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
TargetInstrInfo - Interface to description of machine instruction set.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
bool isRVVSpill(const MachineInstr &MI)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
uint64_t offsetToAlignment(uint64_t Value, Align Alignment)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
unsigned Log2(Align A)
Returns the log2 of the alignment.
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const