22#define GET_TARGET_REGBANK_IMPL
23#include "RISCVGenRegisterBank.inc"
111 switch (RC.
getID()) {
114 case RISCV::GPRRegClassID:
115 case RISCV::GPRF16RegClassID:
116 case RISCV::GPRF32RegClassID:
117 case RISCV::GPRNoX0RegClassID:
118 case RISCV::GPRNoX0X2RegClassID:
119 case RISCV::GPRJALRRegClassID:
120 case RISCV::GPRJALRNonX7RegClassID:
121 case RISCV::GPRTCRegClassID:
122 case RISCV::GPRTCNonX7RegClassID:
123 case RISCV::GPRC_and_GPRTCRegClassID:
124 case RISCV::GPRCRegClassID:
125 case RISCV::GPRC_and_SR07RegClassID:
126 case RISCV::SR07RegClassID:
127 case RISCV::SPRegClassID:
128 case RISCV::GPRX0RegClassID:
130 case RISCV::FPR64RegClassID:
131 case RISCV::FPR16RegClassID:
132 case RISCV::FPR32RegClassID:
133 case RISCV::FPR64CRegClassID:
134 case RISCV::FPR32CRegClassID:
136 case RISCV::VMRegClassID:
137 case RISCV::VRRegClassID:
138 case RISCV::VRNoV0RegClassID:
139 case RISCV::VRM2RegClassID:
140 case RISCV::VRM2NoV0RegClassID:
141 case RISCV::VRM4RegClassID:
142 case RISCV::VRM4NoV0RegClassID:
143 case RISCV::VMV0RegClassID:
144 case RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID:
145 case RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID:
146 case RISCV::VRM8RegClassID:
147 case RISCV::VRM8NoV0RegClassID:
148 case RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClassID:
160bool RISCVRegisterBankInfo::hasFPConstraints(
168 if (
MI.getOpcode() != TargetOpcode::COPY)
177 switch (
MI.getOpcode()) {
178 case TargetOpcode::G_FPTOSI:
179 case TargetOpcode::G_FPTOUI:
180 case TargetOpcode::G_FCMP:
186 return hasFPConstraints(
MI,
MRI,
TRI);
192 switch (
MI.getOpcode()) {
193 case TargetOpcode::G_SITOFP:
194 case TargetOpcode::G_UITOFP:
200 return hasFPConstraints(
MI,
MRI,
TRI);
203bool RISCVRegisterBankInfo::anyUseOnlyUseFP(
207 MRI.use_nodbg_instructions(Def),
216 else if (
Size == 128)
218 else if (
Size == 256)
220 else if (
Size == 512)
230 const unsigned Opc =
MI.getOpcode();
246 assert((GPRSize == 32 || GPRSize == 64) &&
"Unexpected GPR size");
248 unsigned NumOperands =
MI.getNumOperands();
254 case TargetOpcode::G_ADD:
255 case TargetOpcode::G_SUB:
256 case TargetOpcode::G_SHL:
257 case TargetOpcode::G_ASHR:
258 case TargetOpcode::G_LSHR:
259 case TargetOpcode::G_AND:
260 case TargetOpcode::G_OR:
261 case TargetOpcode::G_XOR:
262 case TargetOpcode::G_MUL:
263 case TargetOpcode::G_SDIV:
264 case TargetOpcode::G_SREM:
265 case TargetOpcode::G_SMULH:
266 case TargetOpcode::G_SMAX:
267 case TargetOpcode::G_SMIN:
268 case TargetOpcode::G_UDIV:
269 case TargetOpcode::G_UREM:
270 case TargetOpcode::G_UMULH:
271 case TargetOpcode::G_UMAX:
272 case TargetOpcode::G_UMIN:
273 case TargetOpcode::G_PTR_ADD:
274 case TargetOpcode::G_PTRTOINT:
275 case TargetOpcode::G_INTTOPTR:
276 case TargetOpcode::G_FADD:
277 case TargetOpcode::G_FSUB:
278 case TargetOpcode::G_FMUL:
279 case TargetOpcode::G_FDIV:
280 case TargetOpcode::G_FABS:
281 case TargetOpcode::G_FNEG:
282 case TargetOpcode::G_FSQRT:
283 case TargetOpcode::G_FMAXNUM:
284 case TargetOpcode::G_FMINNUM: {
285 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
294 Mapping = GPRValueMapping;
298 for (
unsigned Idx = 1;
Idx != NumOperands; ++
Idx) {
299 LLT OpTy =
MRI.getType(
MI.getOperand(
Idx).getReg());
301 "Operand has incompatible type");
310 case TargetOpcode::G_SEXTLOAD:
311 case TargetOpcode::G_ZEXTLOAD:
314 case TargetOpcode::G_IMPLICIT_DEF: {
316 LLT DstTy =
MRI.getType(Dst);
318 auto Mapping = GPRValueMapping;
326 else if (anyUseOnlyUseFP(Dst,
MRI,
TRI))
337 case TargetOpcode::G_LOAD: {
338 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
339 OpdsMapping[0] = GPRValueMapping;
340 OpdsMapping[1] = GPRValueMapping;
351 if (anyUseOnlyUseFP(
MI.getOperand(0).getReg(),
MRI,
TRI))
360 case TargetOpcode::G_STORE: {
361 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
362 OpdsMapping[0] = GPRValueMapping;
363 OpdsMapping[1] = GPRValueMapping;
376 case TargetOpcode::G_SELECT: {
377 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
380 auto &Sel = cast<GSelect>(
MI);
381 LLT TestTy =
MRI.getType(Sel.getCondReg());
382 assert(TestTy.
isVector() &&
"Unexpected condition argument type");
383 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] =
405 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
407 return onlyUsesFP(UseMI, MRI, TRI);
434 OpdsMapping[1] = GPRValueMapping;
440 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
443 case TargetOpcode::G_FPTOSI:
444 case TargetOpcode::G_FPTOUI:
445 case RISCV::G_FCLASS: {
446 LLT Ty =
MRI.getType(
MI.getOperand(1).getReg());
447 OpdsMapping[0] = GPRValueMapping;
451 case TargetOpcode::G_SITOFP:
452 case TargetOpcode::G_UITOFP: {
453 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
455 OpdsMapping[1] = GPRValueMapping;
458 case TargetOpcode::G_FCMP: {
459 LLT Ty =
MRI.getType(
MI.getOperand(2).getReg());
462 assert((
Size == 32 ||
Size == 64) &&
"Unsupported size for G_FCMP");
464 OpdsMapping[0] = GPRValueMapping;
468 case TargetOpcode::G_MERGE_VALUES: {
470 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
474 OpdsMapping[1] = GPRValueMapping;
475 OpdsMapping[2] = GPRValueMapping;
479 case TargetOpcode::G_UNMERGE_VALUES: {
481 LLT Ty =
MRI.getType(
MI.getOperand(2).getReg());
484 OpdsMapping[0] = GPRValueMapping;
485 OpdsMapping[1] = GPRValueMapping;
492 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
493 auto &MO =
MI.getOperand(
Idx);
494 if (!MO.isReg() || !MO.getReg())
496 LLT Ty =
MRI.getType(MO.getReg());
506 OpdsMapping[
Idx] = GPRValueMapping;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
unsigned const TargetRegisterInfo * TRI
static const RegisterBankInfo::ValueMapping * getFPValueMapping(unsigned Size)
static const RegisterBankInfo::ValueMapping * getVRBValueMapping(unsigned Size)
This file declares the targeting of the RegisterBankInfo class for RISC-V.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr bool isValid() const
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
RISCVRegisterBankInfo(unsigned HwMode)
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override
Get a register bank that covers RC.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const RegisterBankInfo::PartialMapping PartMappings[]
const RegisterBankInfo::ValueMapping ValueMappings[]
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
Helper struct that represents how a value is partially mapped into a register.
Helper struct that represents how a value is mapped through different register banks.