24#include "llvm/IR/IntrinsicsSPIRV.h"
34 for (
unsigned WordIndex = 0; WordIndex < 4; ++WordIndex) {
35 unsigned StrIndex = i + WordIndex;
36 uint8_t CharToAdd = 0;
37 if (StrIndex < Str.size()) {
38 CharToAdd = Str[StrIndex];
40 Word |= (CharToAdd << (WordIndex * 8));
47 const size_t Len = Str.size() + 1;
48 return (Len % 4 == 0) ? Len : Len + (4 - (Len % 4));
53 for (
unsigned i = 0; i < PaddedLen; i += 4) {
61 for (
unsigned i = 0; i < PaddedLen; i += 4) {
68 std::vector<Value *> &Args) {
70 for (
unsigned i = 0; i < PaddedLen; i += 4) {
81 const auto Bitwidth = Imm.getBitWidth();
84 else if (Bitwidth <= 32) {
85 MIB.
addImm(Imm.getZExtValue());
90 }
else if (Bitwidth <= 64) {
91 uint64_t FullImm = Imm.getZExtValue();
92 uint32_t LowBits = FullImm & 0xffffffff;
93 uint32_t HighBits = (FullImm >> 32) & 0xffffffff;
109 const std::vector<uint32_t> &DecArgs,
113 for (
const auto &DecArg : DecArgs)
118 SPIRV::Decoration::Decoration Dec,
119 const std::vector<uint32_t> &DecArgs,
StringRef StrImm) {
120 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpDecorate)
127 SPIRV::Decoration::Decoration Dec,
128 const std::vector<uint32_t> &DecArgs,
StringRef StrImm) {
130 auto MIB =
BuildMI(
MBB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpDecorate))
140 case SPIRV::StorageClass::Function:
142 case SPIRV::StorageClass::CrossWorkgroup:
144 case SPIRV::StorageClass::UniformConstant:
146 case SPIRV::StorageClass::Workgroup:
148 case SPIRV::StorageClass::Generic:
150 case SPIRV::StorageClass::DeviceOnlyINTEL:
152 case SPIRV::StorageClass::HostOnlyINTEL:
154 case SPIRV::StorageClass::Input:
161SPIRV::StorageClass::StorageClass
165 return SPIRV::StorageClass::Function;
167 return SPIRV::StorageClass::CrossWorkgroup;
169 return SPIRV::StorageClass::UniformConstant;
171 return SPIRV::StorageClass::Workgroup;
173 return SPIRV::StorageClass::Generic;
175 return STI.
canUseExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes)
176 ? SPIRV::StorageClass::DeviceOnlyINTEL
177 : SPIRV::StorageClass::CrossWorkgroup;
179 return STI.
canUseExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes)
180 ? SPIRV::StorageClass::HostOnlyINTEL
181 : SPIRV::StorageClass::CrossWorkgroup;
183 return SPIRV::StorageClass::Input;
189SPIRV::MemorySemantics::MemorySemantics
192 case SPIRV::StorageClass::StorageBuffer:
193 case SPIRV::StorageClass::Uniform:
194 return SPIRV::MemorySemantics::UniformMemory;
195 case SPIRV::StorageClass::Workgroup:
196 return SPIRV::MemorySemantics::WorkgroupMemory;
197 case SPIRV::StorageClass::CrossWorkgroup:
198 return SPIRV::MemorySemantics::CrossWorkgroupMemory;
199 case SPIRV::StorageClass::AtomicCounter:
200 return SPIRV::MemorySemantics::AtomicCounterMemory;
201 case SPIRV::StorageClass::Image:
202 return SPIRV::MemorySemantics::ImageMemory;
204 return SPIRV::MemorySemantics::None;
211 return SPIRV::MemorySemantics::Acquire;
213 return SPIRV::MemorySemantics::Release;
215 return SPIRV::MemorySemantics::AcquireRelease;
217 return SPIRV::MemorySemantics::SequentiallyConsistent;
221 return SPIRV::MemorySemantics::None;
229 if (
auto *GI = dyn_cast<GIntrinsic>(ConstInstr)) {
230 if (GI->is(Intrinsic::spv_track_constant)) {
232 return MRI->getVRegDef(ConstReg);
234 }
else if (ConstInstr->
getOpcode() == SPIRV::ASSIGN_TYPE) {
236 return MRI->getVRegDef(ConstReg);
238 return MRI->getVRegDef(ConstReg);
243 assert(
MI &&
MI->getOpcode() == TargetOpcode::G_CONSTANT);
244 return MI->getOperand(1).getCImm()->getValue().getZExtValue();
248 if (
const auto *GI = dyn_cast<GIntrinsic>(&
MI))
249 return GI->is(IntrinsicID);
254 Type *ElementTy = cast<ValueAsMetadata>(
N->getOperand(
I))->getType();
261 return MangledName ==
"write_pipe_2" || MangledName ==
"read_pipe_2" ||
262 MangledName ==
"write_pipe_2_bl" || MangledName ==
"read_pipe_2_bl" ||
263 MangledName ==
"write_pipe_4" || MangledName ==
"read_pipe_4" ||
264 MangledName ==
"reserve_write_pipe" ||
265 MangledName ==
"reserve_read_pipe" ||
266 MangledName ==
"commit_write_pipe" ||
267 MangledName ==
"commit_read_pipe" ||
268 MangledName ==
"work_group_reserve_write_pipe" ||
269 MangledName ==
"work_group_reserve_read_pipe" ||
270 MangledName ==
"work_group_commit_write_pipe" ||
271 MangledName ==
"work_group_commit_read_pipe" ||
272 MangledName ==
"get_pipe_num_packets_ro" ||
273 MangledName ==
"get_pipe_max_packets_ro" ||
274 MangledName ==
"get_pipe_num_packets_wo" ||
275 MangledName ==
"get_pipe_max_packets_wo" ||
276 MangledName ==
"sub_group_reserve_write_pipe" ||
277 MangledName ==
"sub_group_reserve_read_pipe" ||
278 MangledName ==
"sub_group_commit_write_pipe" ||
279 MangledName ==
"sub_group_commit_read_pipe" ||
280 MangledName ==
"to_global" || MangledName ==
"to_local" ||
281 MangledName ==
"to_private";
285 return MangledName ==
"__enqueue_kernel_basic" ||
286 MangledName ==
"__enqueue_kernel_basic_events" ||
287 MangledName ==
"__enqueue_kernel_varargs" ||
288 MangledName ==
"__enqueue_kernel_events_varargs";
292 return MangledName ==
"__get_kernel_work_group_size_impl" ||
293 MangledName ==
"__get_kernel_sub_group_count_for_ndrange_impl" ||
294 MangledName ==
"__get_kernel_max_sub_group_size_for_ndrange_impl" ||
295 MangledName ==
"__get_kernel_preferred_work_group_size_multiple_impl";
299 if (!
Name.starts_with(
"__"))
304 Name ==
"__translate_sampler_initializer";
309 bool IsNonMangledSPIRV =
Name.starts_with(
"__spirv_");
310 bool IsNonMangledHLSL =
Name.starts_with(
"__hlsl_");
311 bool IsMangled =
Name.starts_with(
"_Z");
314 if (IsNonMangledOCL || IsNonMangledSPIRV || IsNonMangledHLSL || !IsMangled)
319 std::string Result = DemangledName;
328 size_t Start, Len = 0;
329 size_t DemangledNameLenStart = 2;
330 if (
Name.starts_with(
"_ZN")) {
332 size_t NameSpaceStart =
Name.find_first_not_of(
"rVKRO", 3);
334 if (
Name.substr(NameSpaceStart, 11) !=
"2cl7__spirv")
335 return std::string();
336 DemangledNameLenStart = NameSpaceStart + 11;
338 Start =
Name.find_first_not_of(
"0123456789", DemangledNameLenStart);
339 Name.substr(DemangledNameLenStart, Start - DemangledNameLenStart)
340 .getAsInteger(10, Len);
341 return Name.substr(Start, Len).str();
345 if (
Name.starts_with(
"opencl.") ||
Name.starts_with(
"ocl_") ||
346 Name.starts_with(
"spirv."))
352 if (
const TargetExtType *EType = dyn_cast<TargetExtType>(Ty))
366 if (
F.getFnAttribute(
"hlsl.shader").isValid())
373 TypeName.consume_front(
"atomic_");
374 if (TypeName.consume_front(
"void"))
376 else if (TypeName.consume_front(
"bool"))
378 else if (TypeName.consume_front(
"char") ||
379 TypeName.consume_front(
"unsigned char") ||
380 TypeName.consume_front(
"uchar"))
382 else if (TypeName.consume_front(
"short") ||
383 TypeName.consume_front(
"unsigned short") ||
384 TypeName.consume_front(
"ushort"))
386 else if (TypeName.consume_front(
"int") ||
387 TypeName.consume_front(
"unsigned int") ||
388 TypeName.consume_front(
"uint"))
390 else if (TypeName.consume_front(
"long") ||
391 TypeName.consume_front(
"unsigned long") ||
392 TypeName.consume_front(
"ulong"))
394 else if (TypeName.consume_front(
"half"))
396 else if (TypeName.consume_front(
"float"))
398 else if (TypeName.consume_front(
"double"))
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
This file declares the MachineIRBuilder class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
This is an important class for using LLVM in a threaded context.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
static MCOperand createImm(int64_t Val)
Helper class to build MachineInstr.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
const MachineOperand & getOperand(unsigned i) const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
bool canUseExtension(SPIRV::Extension::Extension E) const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
Class to represent target extensions types, which are generally unintrospectable from target-independ...
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getHalfTy(LLVMContext &C)
static Type * getDoubleTy(LLVMContext &C)
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
static Type * getVoidTy(LLVMContext &C)
static IntegerType * getInt16Ty(LLVMContext &C)
static IntegerType * getInt8Ty(LLVMContext &C)
static IntegerType * getInt32Ty(LLVMContext &C)
static IntegerType * getInt64Ty(LLVMContext &C)
static Type * getFloatTy(LLVMContext &C)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SPIR_KERNEL
Used for SPIR kernel functions.
This is an optimization pass for GlobalISel generic memory operations.
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
std::string getStringImm(const MachineInstr &MI, unsigned StartIndex)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static void finishBuildOpDecorate(MachineInstrBuilder &MIB, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
static uint32_t convertCharsToWord(const StringRef &Str, unsigned i)
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
std::string getOclOrSpirvBuiltinDemangledName(StringRef Name)
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
std::string getSPIRVStringOperand(const InstType &MI, unsigned StartIndex)
char * itaniumDemangle(std::string_view mangled_name, bool ParseParams=true)
Returns a non-NULL pointer to a NUL-terminated C style string that should be explicitly freed,...
bool isSpecialOpaqueType(const Type *Ty)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
static bool isNonMangledOCLBuiltin(StringRef Name)
bool isEntryPoint(const Function &F)
SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace, const SPIRVSubtarget &STI)
AtomicOrdering
Atomic ordering for LLVM's memory model.
Type * toTypedPointer(Type *Ty, LLVMContext &Ctx)
static bool isPipeOrAddressSpaceCastBI(const StringRef MangledName)
Type * parseBasicTypeName(StringRef &TypeName, LLVMContext &Ctx)
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
bool hasBuiltinTypePrefix(StringRef Name)
Type * getMDOperandAsType(const MDNode *N, unsigned I)
static size_t getPaddedLen(const StringRef &Str)
bool isSpvIntrinsic(const MachineInstr &MI, Intrinsic::ID IntrinsicID)
void addStringImm(const StringRef &Str, MCInst &Inst)
static bool isKernelQueryBI(const StringRef MangledName)
static bool isEnqueueKernelBI(const StringRef MangledName)
SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord)