99void SelectionDAG::DAGNodeDeletedListener::anchor() {}
100void SelectionDAG::DAGNodeInsertedListener::anchor() {}
102#define DEBUG_TYPE "selectiondag"
106 cl::desc(
"Gang up loads and stores generated by inlining of memcpy"));
109 cl::desc(
"Number limit for gluing ld/st of memcpy."),
125 return getValueAPF().bitwiseIsEqual(V);
148 N->getValueType(0).getVectorElementType().getSizeInBits();
149 if (
auto *Op0 = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
150 SplatVal = Op0->getAPIntValue().
trunc(EltSize);
153 if (
auto *Op0 = dyn_cast<ConstantFPSDNode>(
N->getOperand(0))) {
154 SplatVal = Op0->getValueAPF().bitcastToAPInt().
trunc(EltSize);
159 auto *BV = dyn_cast<BuildVectorSDNode>(
N);
164 unsigned SplatBitSize;
166 unsigned EltSize =
N->getValueType(0).getVectorElementType().getSizeInBits();
171 const bool IsBigEndian =
false;
172 return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs,
173 EltSize, IsBigEndian) &&
174 EltSize == SplatBitSize;
183 N =
N->getOperand(0).getNode();
192 unsigned i = 0, e =
N->getNumOperands();
195 while (i != e &&
N->getOperand(i).isUndef())
199 if (i == e)
return false;
210 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
212 if (CN->getAPIntValue().countr_one() < EltSize)
215 if (CFPN->getValueAPF().bitcastToAPInt().countr_one() < EltSize)
223 for (++i; i != e; ++i)
224 if (
N->getOperand(i) != NotZero && !
N->getOperand(i).isUndef())
232 N =
N->getOperand(0).getNode();
241 bool IsAllUndef =
true;
254 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
256 if (CN->getAPIntValue().countr_zero() < EltSize)
259 if (CFPN->getValueAPF().bitcastToAPInt().countr_zero() < EltSize)
286 if (!isa<ConstantSDNode>(
Op))
299 if (!isa<ConstantFPSDNode>(
Op))
307 assert(
N->getValueType(0).isVector() &&
"Expected a vector!");
309 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
310 if (EltSize <= NewEltSize)
314 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
319 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
329 if (!isa<ConstantSDNode>(
Op))
332 APInt C =
Op->getAsAPIntVal().trunc(EltSize);
333 if (
Signed &&
C.trunc(NewEltSize).sext(EltSize) !=
C)
335 if (!
Signed &&
C.trunc(NewEltSize).zext(EltSize) !=
C)
346 if (
N->getNumOperands() == 0)
352 return N->getOpcode() ==
ISD::FREEZE &&
N->getOperand(0).isUndef();
355template <
typename ConstNodeType>
357 std::function<
bool(ConstNodeType *)>
Match,
360 if (
auto *
C = dyn_cast<ConstNodeType>(
Op))
368 EVT SVT =
Op.getValueType().getScalarType();
370 if (AllowUndefs &&
Op.getOperand(i).isUndef()) {
376 auto *Cst = dyn_cast<ConstNodeType>(
Op.getOperand(i));
377 if (!Cst || Cst->getValueType(0) != SVT || !
Match(Cst))
383template bool ISD::matchUnaryPredicateImpl<ConstantSDNode>(
385template bool ISD::matchUnaryPredicateImpl<ConstantFPSDNode>(
391 bool AllowUndefs,
bool AllowTypeMismatch) {
392 if (!AllowTypeMismatch &&
LHS.getValueType() !=
RHS.getValueType())
396 if (
auto *LHSCst = dyn_cast<ConstantSDNode>(
LHS))
397 if (
auto *RHSCst = dyn_cast<ConstantSDNode>(
RHS))
398 return Match(LHSCst, RHSCst);
401 if (
LHS.getOpcode() !=
RHS.getOpcode() ||
406 EVT SVT =
LHS.getValueType().getScalarType();
407 for (
unsigned i = 0, e =
LHS.getNumOperands(); i != e; ++i) {
410 bool LHSUndef = AllowUndefs && LHSOp.
isUndef();
411 bool RHSUndef = AllowUndefs && RHSOp.
isUndef();
412 auto *LHSCst = dyn_cast<ConstantSDNode>(LHSOp);
413 auto *RHSCst = dyn_cast<ConstantSDNode>(RHSOp);
414 if ((!LHSCst && !LHSUndef) || (!RHSCst && !RHSUndef))
416 if (!AllowTypeMismatch && (LHSOp.
getValueType() != SVT ||
419 if (!
Match(LHSCst, RHSCst))
426 switch (VecReduceOpcode) {
431 case ISD::VP_REDUCE_FADD:
432 case ISD::VP_REDUCE_SEQ_FADD:
436 case ISD::VP_REDUCE_FMUL:
437 case ISD::VP_REDUCE_SEQ_FMUL:
440 case ISD::VP_REDUCE_ADD:
443 case ISD::VP_REDUCE_MUL:
446 case ISD::VP_REDUCE_AND:
449 case ISD::VP_REDUCE_OR:
452 case ISD::VP_REDUCE_XOR:
455 case ISD::VP_REDUCE_SMAX:
458 case ISD::VP_REDUCE_SMIN:
461 case ISD::VP_REDUCE_UMAX:
464 case ISD::VP_REDUCE_UMIN:
467 case ISD::VP_REDUCE_FMAX:
470 case ISD::VP_REDUCE_FMIN:
483#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) \
486#include "llvm/IR/VPIntrinsics.def"
494#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
495#define VP_PROPERTY_BINARYOP return true;
496#define END_REGISTER_VP_SDNODE(VPSD) break;
497#include "llvm/IR/VPIntrinsics.def"
506#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
507#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
508#define END_REGISTER_VP_SDNODE(VPSD) break;
509#include "llvm/IR/VPIntrinsics.def"
519#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, ...) \
522#include "llvm/IR/VPIntrinsics.def"
531#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS) \
534#include "llvm/IR/VPIntrinsics.def"
544#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) case ISD::VPOPC:
545#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) return ISD::SDOPC;
546#define END_REGISTER_VP_SDNODE(VPOPC) break;
547#include "llvm/IR/VPIntrinsics.def"
556#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) break;
557#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) case ISD::SDOPC:
558#define END_REGISTER_VP_SDNODE(VPOPC) return ISD::VPOPC;
559#include "llvm/IR/VPIntrinsics.def"
606 bool isIntegerLike) {
631 bool IsInteger =
Type.isInteger();
636 unsigned Op = Op1 | Op2;
652 bool IsInteger =
Type.isInteger();
687 ID.AddPointer(VTList.
VTs);
693 for (
const auto &
Op : Ops) {
694 ID.AddPointer(
Op.getNode());
695 ID.AddInteger(
Op.getResNo());
702 for (
const auto &
Op : Ops) {
703 ID.AddPointer(
Op.getNode());
704 ID.AddInteger(
Op.getResNo());
717 switch (
N->getOpcode()) {
726 ID.AddPointer(
C->getConstantIntValue());
727 ID.AddBoolean(
C->isOpaque());
732 ID.AddPointer(cast<ConstantFPSDNode>(
N)->getConstantFPValue());
748 ID.AddInteger(cast<RegisterSDNode>(
N)->
getReg());
751 ID.AddPointer(cast<RegisterMaskSDNode>(
N)->getRegMask());
754 ID.AddPointer(cast<SrcValueSDNode>(
N)->getValue());
758 ID.AddInteger(cast<FrameIndexSDNode>(
N)->getIndex());
762 if (cast<LifetimeSDNode>(
N)->hasOffset()) {
763 ID.AddInteger(cast<LifetimeSDNode>(
N)->
getSize());
768 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getGuid());
769 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getIndex());
770 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getAttributes());
774 ID.AddInteger(cast<JumpTableSDNode>(
N)->getIndex());
775 ID.AddInteger(cast<JumpTableSDNode>(
N)->getTargetFlags());
780 ID.AddInteger(CP->getAlign().value());
781 ID.AddInteger(CP->getOffset());
782 if (CP->isMachineConstantPoolEntry())
783 CP->getMachineCPVal()->addSelectionDAGCSEId(
ID);
785 ID.AddPointer(CP->getConstVal());
786 ID.AddInteger(CP->getTargetFlags());
798 ID.AddInteger(LD->getMemoryVT().getRawBits());
799 ID.AddInteger(LD->getRawSubclassData());
800 ID.AddInteger(LD->getPointerInfo().getAddrSpace());
801 ID.AddInteger(LD->getMemOperand()->getFlags());
806 ID.AddInteger(ST->getMemoryVT().getRawBits());
807 ID.AddInteger(ST->getRawSubclassData());
808 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
809 ID.AddInteger(ST->getMemOperand()->getFlags());
820 case ISD::VP_STORE: {
828 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: {
835 case ISD::EXPERIMENTAL_VP_STRIDED_STORE: {
842 case ISD::VP_GATHER: {
850 case ISD::VP_SCATTER: {
939 if (
auto *MN = dyn_cast<MemIntrinsicSDNode>(
N)) {
940 ID.AddInteger(MN->getRawSubclassData());
941 ID.AddInteger(MN->getPointerInfo().getAddrSpace());
942 ID.AddInteger(MN->getMemOperand()->getFlags());
943 ID.AddInteger(MN->getMemoryVT().getRawBits());
966 if (
N->getValueType(0) == MVT::Glue)
969 switch (
N->getOpcode()) {
977 for (
unsigned i = 1, e =
N->getNumValues(); i != e; ++i)
978 if (
N->getValueType(i) == MVT::Glue)
995 if (Node.use_empty())
1010 while (!DeadNodes.
empty()) {
1019 DUL->NodeDeleted(
N,
nullptr);
1022 RemoveNodeFromCSEMaps(
N);
1053 RemoveNodeFromCSEMaps(
N);
1057 DeleteNodeNotInCSEMaps(
N);
1060void SelectionDAG::DeleteNodeNotInCSEMaps(
SDNode *
N) {
1061 assert(
N->getIterator() != AllNodes.begin() &&
1062 "Cannot delete the entry node!");
1063 assert(
N->use_empty() &&
"Cannot delete a node that is not dead!");
1072 assert(!(V->isVariadic() && isParameter));
1074 ByvalParmDbgValues.push_back(V);
1076 DbgValues.push_back(V);
1077 for (
const SDNode *Node : V->getSDNodes())
1079 DbgValMap[Node].push_back(V);
1084 if (
I == DbgValMap.end())
1086 for (
auto &Val:
I->second)
1087 Val->setIsInvalidated();
1091void SelectionDAG::DeallocateNode(
SDNode *
N) {
1115 switch (
N->getOpcode()) {
1121 EVT VT =
N->getValueType(0);
1122 assert(
N->getNumValues() == 1 &&
"Too many results!");
1124 "Wrong return type!");
1125 assert(
N->getNumOperands() == 2 &&
"Wrong number of operands!");
1126 assert(
N->getOperand(0).getValueType() ==
N->getOperand(1).getValueType() &&
1127 "Mismatched operand types!");
1129 "Wrong operand type!");
1131 "Wrong return type size");
1135 assert(
N->getNumValues() == 1 &&
"Too many results!");
1136 assert(
N->getValueType(0).isVector() &&
"Wrong return type!");
1137 assert(
N->getNumOperands() ==
N->getValueType(0).getVectorNumElements() &&
1138 "Wrong number of operands!");
1139 EVT EltVT =
N->getValueType(0).getVectorElementType();
1141 assert((
Op.getValueType() == EltVT ||
1142 (EltVT.
isInteger() &&
Op.getValueType().isInteger() &&
1143 EltVT.
bitsLE(
Op.getValueType()))) &&
1144 "Wrong operand type!");
1145 assert(
Op.getValueType() ==
N->getOperand(0).getValueType() &&
1146 "Operands must all have the same type");
1158void SelectionDAG::InsertNode(
SDNode *
N) {
1159 AllNodes.push_back(
N);
1161 N->PersistentId = NextPersistentId++;
1164 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1165 DUL->NodeInserted(
N);
1172bool SelectionDAG::RemoveNodeFromCSEMaps(
SDNode *
N) {
1173 bool Erased =
false;
1174 switch (
N->getOpcode()) {
1177 assert(CondCodeNodes[cast<CondCodeSDNode>(
N)->
get()] &&
1178 "Cond code doesn't exist!");
1179 Erased = CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] !=
nullptr;
1180 CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] =
nullptr;
1183 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(
N)->getSymbol());
1187 Erased = TargetExternalSymbols.erase(std::pair<std::string, unsigned>(
1192 auto *MCSN = cast<MCSymbolSDNode>(
N);
1193 Erased = MCSymbols.erase(MCSN->getMCSymbol());
1197 EVT VT = cast<VTSDNode>(
N)->getVT();
1199 Erased = ExtendedValueTypeNodes.erase(VT);
1210 Erased = CSEMap.RemoveNode(
N);
1217 if (!Erased &&
N->getValueType(
N->getNumValues()-1) != MVT::Glue &&
1232SelectionDAG::AddModifiedNodeToCSEMaps(
SDNode *
N) {
1236 SDNode *Existing = CSEMap.GetOrInsertNode(
N);
1237 if (Existing !=
N) {
1244 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1245 DUL->NodeDeleted(
N, Existing);
1246 DeleteNodeNotInCSEMaps(
N);
1252 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1253 DUL->NodeUpdated(
N);
1271 Node->intersectFlagsWith(
N->getFlags());
1291 Node->intersectFlagsWith(
N->getFlags());
1309 Node->intersectFlagsWith(
N->getFlags());
1322 : TM(tm), OptLevel(OL), EntryNode(ISD::EntryToken, 0,
DebugLoc(),
1325 InsertNode(&EntryNode);
1336 SDAGISelPass = PassPtr;
1340 LibInfo = LibraryInfo;
1345 FnVarLocs = VarLocs;
1349 assert(!UpdateListeners &&
"Dangling registered DAGUpdateListeners");
1351 OperandRecycler.clear(OperandAllocator);
1360void SelectionDAG::allnodes_clear() {
1361 assert(&*AllNodes.begin() == &EntryNode);
1362 AllNodes.remove(AllNodes.begin());
1363 while (!AllNodes.empty())
1364 DeallocateNode(&AllNodes.front());
1366 NextPersistentId = 0;
1372 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1374 switch (
N->getOpcode()) {
1379 "debug location. Use another overload.");
1386 const SDLoc &
DL,
void *&InsertPos) {
1387 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1389 switch (
N->getOpcode()) {
1395 if (
N->getDebugLoc() !=
DL.getDebugLoc())
1402 if (
DL.getIROrder() &&
DL.getIROrder() <
N->getIROrder())
1403 N->setDebugLoc(
DL.getDebugLoc());
1412 OperandRecycler.clear(OperandAllocator);
1413 OperandAllocator.
Reset();
1416 ExtendedValueTypeNodes.clear();
1417 ExternalSymbols.clear();
1418 TargetExternalSymbols.clear();
1421 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
nullptr);
1422 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
nullptr);
1424 EntryNode.UseList =
nullptr;
1425 InsertNode(&EntryNode);
1431 return VT.
bitsGT(
Op.getValueType())
1437std::pair<SDValue, SDValue>
1441 "Strict no-op FP extend/round not allowed.");
1448 return std::pair<SDValue, SDValue>(Res,
SDValue(Res.
getNode(), 1));
1452 return VT.
bitsGT(
Op.getValueType()) ?
1458 return VT.
bitsGT(
Op.getValueType()) ?
1464 return VT.
bitsGT(
Op.getValueType()) ?
1472 auto Type =
Op.getValueType();
1476 auto Size =
Op.getValueSizeInBits();
1487 auto Type =
Op.getValueType();
1491 auto Size =
Op.getValueSizeInBits();
1502 auto Type =
Op.getValueType();
1506 auto Size =
Op.getValueSizeInBits();
1524 EVT OpVT =
Op.getValueType();
1526 "Cannot getZeroExtendInReg FP types");
1528 "getZeroExtendInReg type should be vector iff the operand "
1532 "Vector element counts must match in getZeroExtendInReg");
1570 return getNode(ISD::VP_XOR,
DL, VT, Val, TrueValue, Mask, EVL);
1581 return getNode(ISD::VP_ZERO_EXTEND,
DL, VT,
Op, Mask, EVL);
1583 return getNode(ISD::VP_TRUNCATE,
DL, VT,
Op, Mask, EVL);
1603 bool isT,
bool isO) {
1607 "getConstant with a uint64_t value that doesn't fit in the type!");
1612 bool isT,
bool isO) {
1613 return getConstant(*ConstantInt::get(*Context, Val),
DL, VT, isT, isO);
1617 EVT VT,
bool isT,
bool isO) {
1635 Elt = ConstantInt::get(*
getContext(), NewVal);
1654 "Can only handle an even split!");
1658 for (
unsigned i = 0; i != Parts; ++i)
1660 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1661 ViaEltVT, isT, isO));
1666 unsigned ViaVecNumElts = VT.
getSizeInBits() / ViaEltSizeInBits;
1677 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1678 ViaEltVT, isT, isO));
1683 std::reverse(EltParts.
begin(), EltParts.
end());
1702 "APInt size does not match type size!");
1711 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1716 N = newSDNode<ConstantSDNode>(isT, isO, Elt, VTs);
1717 CSEMap.InsertNode(
N, IP);
1734 const SDLoc &
DL,
bool LegalTypes) {
1741 const SDLoc &
DL,
bool LegalTypes) {
1757 EVT VT,
bool isTarget) {
1772 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1777 N = newSDNode<ConstantFPSDNode>(isTarget, &V, VTs);
1778 CSEMap.InsertNode(
N, IP);
1792 if (EltVT == MVT::f32)
1794 if (EltVT == MVT::f64)
1796 if (EltVT == MVT::f80 || EltVT == MVT::f128 || EltVT == MVT::ppcf128 ||
1797 EltVT == MVT::f16 || EltVT == MVT::bf16) {
1808 EVT VT, int64_t
Offset,
bool isTargetGA,
1809 unsigned TargetFlags) {
1810 assert((TargetFlags == 0 || isTargetGA) &&
1811 "Cannot set target flags on target-independent globals");
1829 ID.AddInteger(TargetFlags);
1831 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
1834 auto *
N = newSDNode<GlobalAddressSDNode>(
1835 Opc,
DL.getIROrder(),
DL.getDebugLoc(), GV, VTs,
Offset, TargetFlags);
1836 CSEMap.InsertNode(
N, IP);
1848 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1851 auto *
N = newSDNode<FrameIndexSDNode>(FI, VTs, isTarget);
1852 CSEMap.InsertNode(
N, IP);
1858 unsigned TargetFlags) {
1859 assert((TargetFlags == 0 || isTarget) &&
1860 "Cannot set target flags on target-independent jump tables");
1866 ID.AddInteger(TargetFlags);
1868 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1871 auto *
N = newSDNode<JumpTableSDNode>(JTI, VTs, isTarget, TargetFlags);
1872 CSEMap.InsertNode(
N, IP);
1886 bool isTarget,
unsigned TargetFlags) {
1887 assert((TargetFlags == 0 || isTarget) &&
1888 "Cannot set target flags on target-independent globals");
1897 ID.AddInteger(Alignment->value());
1900 ID.AddInteger(TargetFlags);
1902 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1905 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VTs,
Offset, *Alignment,
1907 CSEMap.InsertNode(
N, IP);
1916 bool isTarget,
unsigned TargetFlags) {
1917 assert((TargetFlags == 0 || isTarget) &&
1918 "Cannot set target flags on target-independent globals");
1925 ID.AddInteger(Alignment->value());
1927 C->addSelectionDAGCSEId(
ID);
1928 ID.AddInteger(TargetFlags);
1930 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1933 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VTs,
Offset, *Alignment,
1935 CSEMap.InsertNode(
N, IP);
1945 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1948 auto *
N = newSDNode<BasicBlockSDNode>(
MBB);
1949 CSEMap.InsertNode(
N, IP);
1956 ValueTypeNodes.size())
1963 N = newSDNode<VTSDNode>(VT);
1971 N = newSDNode<ExternalSymbolSDNode>(
false,
Sym, 0,
getVTList(VT));
1986 unsigned TargetFlags) {
1988 TargetExternalSymbols[std::pair<std::string, unsigned>(
Sym, TargetFlags)];
1990 N = newSDNode<ExternalSymbolSDNode>(
true,
Sym, TargetFlags,
getVTList(VT));
1996 if ((
unsigned)
Cond >= CondCodeNodes.size())
1997 CondCodeNodes.resize(
Cond+1);
1999 if (!CondCodeNodes[
Cond]) {
2000 auto *
N = newSDNode<CondCodeSDNode>(
Cond);
2001 CondCodeNodes[
Cond] =
N;
2011 "APInt size does not match type size!");
2029 if (EC.isScalable())
2042 const APInt &StepVal) {
2066 "Must have the same number of vector elements as mask elements!");
2068 "Invalid VECTOR_SHUFFLE");
2076 int NElts = Mask.size();
2078 [&](
int M) {
return M < (NElts * 2) && M >= -1; }) &&
2079 "Index out of range");
2087 for (
int i = 0; i != NElts; ++i)
2088 if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
2104 for (
int i = 0; i < NElts; ++i) {
2105 if (MaskVec[i] <
Offset || MaskVec[i] >= (
Offset + NElts))
2109 if (UndefElements[MaskVec[i] -
Offset]) {
2115 if (!UndefElements[i])
2119 if (
auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
2120 BlendSplat(N1BV, 0);
2121 if (
auto *N2BV = dyn_cast<BuildVectorSDNode>(N2))
2122 BlendSplat(N2BV, NElts);
2127 bool AllLHS =
true, AllRHS =
true;
2129 for (
int i = 0; i != NElts; ++i) {
2130 if (MaskVec[i] >= NElts) {
2135 }
else if (MaskVec[i] >= 0) {
2139 if (AllLHS && AllRHS)
2141 if (AllLHS && !N2Undef)
2154 bool Identity =
true, AllSame =
true;
2155 for (
int i = 0; i != NElts; ++i) {
2156 if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity =
false;
2157 if (MaskVec[i] != MaskVec[0]) AllSame =
false;
2159 if (Identity && NElts)
2169 V = V->getOperand(0);
2172 if (
auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
2192 if (AllSame && SameNumElts) {
2193 EVT BuildVT = BV->getValueType(0);
2210 for (
int i = 0; i != NElts; ++i)
2211 ID.AddInteger(MaskVec[i]);
2214 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2220 int *MaskAlloc = OperandAllocator.
Allocate<
int>(NElts);
2223 auto *
N = newSDNode<ShuffleVectorSDNode>(VTs, dl.
getIROrder(),
2225 createOperands(
N, Ops);
2227 CSEMap.InsertNode(
N, IP);
2248 ID.AddInteger(RegNo);
2250 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2253 auto *
N = newSDNode<RegisterSDNode>(RegNo, VTs);
2255 CSEMap.InsertNode(
N, IP);
2263 ID.AddPointer(RegMask);
2265 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2268 auto *
N = newSDNode<RegisterMaskSDNode>(RegMask);
2269 CSEMap.InsertNode(
N, IP);
2284 ID.AddPointer(Label);
2286 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2291 createOperands(
N, Ops);
2293 CSEMap.InsertNode(
N, IP);
2299 int64_t
Offset,
bool isTarget,
2300 unsigned TargetFlags) {
2308 ID.AddInteger(TargetFlags);
2310 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2313 auto *
N = newSDNode<BlockAddressSDNode>(Opc, VTs, BA,
Offset, TargetFlags);
2314 CSEMap.InsertNode(
N, IP);
2325 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2328 auto *
N = newSDNode<SrcValueSDNode>(V);
2329 CSEMap.InsertNode(
N, IP);
2340 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2343 auto *
N = newSDNode<MDNodeSDNode>(MD);
2344 CSEMap.InsertNode(
N, IP);
2350 if (VT == V.getValueType())
2357 unsigned SrcAS,
unsigned DestAS) {
2362 ID.AddInteger(SrcAS);
2363 ID.AddInteger(DestAS);
2366 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2370 VTs, SrcAS, DestAS);
2371 createOperands(
N, Ops);
2373 CSEMap.InsertNode(
N, IP);
2385 EVT OpTy =
Op.getValueType();
2387 if (OpTy == ShTy || OpTy.
isVector())
return Op;
2395 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2396 EVT VT = Node->getValueType(0);
2397 SDValue Tmp1 = Node->getOperand(0);
2398 SDValue Tmp2 = Node->getOperand(1);
2399 const MaybeAlign MA(Node->getConstantOperandVal(3));
2431 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2432 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2443 Align RedAlign = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2453 if (RedAlign > StackAlign) {
2456 unsigned NumIntermediates;
2458 NumIntermediates, RegisterVT);
2460 Align RedAlign2 = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2461 if (RedAlign2 < RedAlign)
2462 RedAlign = RedAlign2;
2477 false,
nullptr, StackID);
2492 "Don't know how to choose the maximum size when creating a stack "
2501 Align Align = std::max(
DL.getPrefTypeAlign(Ty1),
DL.getPrefTypeAlign(Ty2));
2509 auto GetUndefBooleanConstant = [&]() {
2548 return GetUndefBooleanConstant();
2553 return GetUndefBooleanConstant();
2562 const APInt &C2 = N2C->getAPIntValue();
2564 const APInt &C1 = N1C->getAPIntValue();
2571 auto *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2572 auto *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
2574 if (N1CFP && N2CFP) {
2579 return GetUndefBooleanConstant();
2584 return GetUndefBooleanConstant();
2590 return GetUndefBooleanConstant();
2595 return GetUndefBooleanConstant();
2600 return GetUndefBooleanConstant();
2606 return GetUndefBooleanConstant();
2635 return getSetCC(dl, VT, N2, N1, SwappedCond);
2636 }
else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
2651 return GetUndefBooleanConstant();
2662 unsigned BitWidth =
Op.getScalarValueSizeInBits();
2670 unsigned Depth)
const {
2678 const APInt &DemandedElts,
2679 unsigned Depth)
const {
2686 unsigned Depth )
const {
2692 unsigned Depth)
const {
2697 const APInt &DemandedElts,
2698 unsigned Depth)
const {
2699 EVT VT =
Op.getValueType();
2706 for (
unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx) {
2707 if (!DemandedElts[EltIdx])
2711 KnownZeroElements.
setBit(EltIdx);
2713 return KnownZeroElements;
2723 unsigned Opcode = V.getOpcode();
2724 EVT VT = V.getValueType();
2727 "scalable demanded bits are ignored");
2739 UndefElts = V.getOperand(0).isUndef()
2748 APInt UndefLHS, UndefRHS;
2753 UndefElts = UndefLHS | UndefRHS;
2783 for (
unsigned i = 0; i != NumElts; ++i) {
2789 if (!DemandedElts[i])
2791 if (Scl && Scl !=
Op)
2801 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(V)->getMask();
2802 for (
int i = 0; i != (int)NumElts; ++i) {
2808 if (!DemandedElts[i])
2810 if (M < (
int)NumElts)
2813 DemandedRHS.
setBit(M - NumElts);
2825 auto CheckSplatSrc = [&](
SDValue Src,
const APInt &SrcElts) {
2827 return (SrcElts.popcount() == 1) ||
2829 (SrcElts & SrcUndefs).
isZero());
2831 if (!DemandedLHS.
isZero())
2832 return CheckSplatSrc(V.getOperand(0), DemandedLHS);
2833 return CheckSplatSrc(V.getOperand(1), DemandedRHS);
2837 SDValue Src = V.getOperand(0);
2839 if (Src.getValueType().isScalableVector())
2842 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2855 SDValue Src = V.getOperand(0);
2857 if (Src.getValueType().isScalableVector())
2859 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2861 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts);
2863 UndefElts = UndefSrcElts.
trunc(NumElts);
2869 SDValue Src = V.getOperand(0);
2870 EVT SrcVT = Src.getValueType();
2880 if ((
BitWidth % SrcBitWidth) == 0) {
2882 unsigned Scale =
BitWidth / SrcBitWidth;
2884 APInt ScaledDemandedElts =
2886 for (
unsigned I = 0;
I != Scale; ++
I) {
2890 SubDemandedElts &= ScaledDemandedElts;
2894 if (!SubUndefElts.
isZero())
2908 EVT VT = V.getValueType();
2918 (AllowUndefs || !UndefElts);
2924 EVT VT = V.getValueType();
2925 unsigned Opcode = V.getOpcode();
2946 SplatIdx = (UndefElts & DemandedElts).
countr_one();
2960 auto *SVN = cast<ShuffleVectorSDNode>(V);
2961 if (!SVN->isSplat())
2963 int Idx = SVN->getSplatIndex();
2964 int NumElts = V.getValueType().getVectorNumElements();
2965 SplatIdx =
Idx % NumElts;
2966 return V.getOperand(
Idx / NumElts);
2982 if (LegalSVT.
bitsLT(SVT))
2993 const APInt &DemandedElts)
const {
2996 "Unknown shift node");
2997 unsigned BitWidth = V.getScalarValueSizeInBits();
3000 const APInt &ShAmt = SA->getAPIntValue();
3008 EVT VT = V.getValueType();
3019 "Unknown shift node");
3022 unsigned BitWidth = V.getScalarValueSizeInBits();
3023 auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
3026 const APInt *MinShAmt =
nullptr;
3027 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3028 if (!DemandedElts[i])
3030 auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
3034 const APInt &ShAmt = SA->getAPIntValue();
3037 if (MinShAmt && MinShAmt->
ule(ShAmt))
3045 EVT VT = V.getValueType();
3056 "Unknown shift node");
3059 unsigned BitWidth = V.getScalarValueSizeInBits();
3060 auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
3063 const APInt *MaxShAmt =
nullptr;
3064 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3065 if (!DemandedElts[i])
3067 auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
3071 const APInt &ShAmt = SA->getAPIntValue();
3074 if (MaxShAmt && MaxShAmt->
uge(ShAmt))
3082 EVT VT = V.getValueType();
3093 EVT VT =
Op.getValueType();
3108 unsigned Depth)
const {
3109 unsigned BitWidth =
Op.getScalarValueSizeInBits();
3113 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
3117 if (
auto *
C = dyn_cast<ConstantFPSDNode>(
Op)) {
3127 assert((!
Op.getValueType().isFixedLengthVector() ||
3128 NumElts ==
Op.getValueType().getVectorNumElements()) &&
3129 "Unexpected vector size");
3134 unsigned Opcode =
Op.getOpcode();
3142 "Expected SPLAT_VECTOR implicit truncation");
3149 unsigned ScalarSize =
Op.getOperand(0).getScalarValueSizeInBits();
3151 "Expected SPLAT_VECTOR_PARTS scalars to cover element width");
3158 const APInt &Step =
Op.getConstantOperandAPInt(0);
3167 const APInt MinNumElts =
3173 .
umul_ov(MinNumElts, Overflow);
3177 const APInt MaxValue = (MaxNumElts - 1).
umul_ov(Step, Overflow);
3185 assert(!
Op.getValueType().isScalableVector());
3189 if (!DemandedElts[i])
3198 "Expected BUILD_VECTOR implicit truncation");
3211 assert(!
Op.getValueType().isScalableVector());
3214 APInt DemandedLHS, DemandedRHS;
3218 DemandedLHS, DemandedRHS))
3223 if (!!DemandedLHS) {
3231 if (!!DemandedRHS) {
3240 const APInt &Multiplier =
Op.getConstantOperandAPInt(0);
3245 if (
Op.getValueType().isScalableVector())
3249 EVT SubVectorVT =
Op.getOperand(0).getValueType();
3252 for (
unsigned i = 0; i != NumSubVectors; ++i) {
3254 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
3255 if (!!DemandedSub) {
3267 if (
Op.getValueType().isScalableVector())
3276 APInt DemandedSrcElts = DemandedElts;
3281 if (!!DemandedSubElts) {
3286 if (!!DemandedSrcElts) {
3296 if (
Op.getValueType().isScalableVector() || Src.getValueType().isScalableVector())
3299 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3305 if (
Op.getValueType().isScalableVector())
3309 if (DemandedElts != 1)
3320 if (
Op.getValueType().isScalableVector())
3340 if ((
BitWidth % SubBitWidth) == 0) {
3347 unsigned SubScale =
BitWidth / SubBitWidth;
3348 APInt SubDemandedElts(NumElts * SubScale, 0);
3349 for (
unsigned i = 0; i != NumElts; ++i)
3350 if (DemandedElts[i])
3351 SubDemandedElts.
setBit(i * SubScale);
3353 for (
unsigned i = 0; i != SubScale; ++i) {
3356 unsigned Shifts = IsLE ? i : SubScale - 1 - i;
3357 Known.
insertBits(Known2, SubBitWidth * Shifts);
3362 if ((SubBitWidth %
BitWidth) == 0) {
3363 assert(
Op.getValueType().isVector() &&
"Expected bitcast to vector");
3368 unsigned SubScale = SubBitWidth /
BitWidth;
3369 APInt SubDemandedElts =
3374 for (
unsigned i = 0; i != NumElts; ++i)
3375 if (DemandedElts[i]) {
3376 unsigned Shifts = IsLE ? i : NumElts - 1 - i;
3407 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3411 Op.getOperand(0), DemandedElts,
false,
Depth + 1);
3417 if (
Op->getFlags().hasNoSignedWrap() &&
3418 Op.getOperand(0) ==
Op.getOperand(1) &&
3448 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3451 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3452 if (
Op.getResNo() == 0)
3459 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3462 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3463 if (
Op.getResNo() == 0)
3507 if (
Op.getResNo() != 1)
3522 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
3536 if (
const APInt *ShMinAmt =
3544 Op->getFlags().hasExact());
3547 if (
const APInt *ShMinAmt =
3555 Op->getFlags().hasExact());
3560 unsigned Amt =
C->getAPIntValue().urem(
BitWidth);
3566 DemandedElts,
Depth + 1);
3591 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3594 unsigned LoBits =
Op.getOperand(0).getScalarValueSizeInBits();
3595 unsigned HiBits =
Op.getOperand(1).getScalarValueSizeInBits();
3598 Known = Known2.
concat(Known);
3612 if (
Op.getResNo() == 0)
3620 EVT EVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3661 !
Op.getValueType().isScalableVector()) {
3675 for (
unsigned i = 0; i != NumElts; ++i) {
3676 if (!DemandedElts[i])
3679 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
3685 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
3686 APInt Value = CFP->getValueAPF().bitcastToAPInt();
3697 if (
auto *CInt = dyn_cast<ConstantInt>(Cst)) {
3699 }
else if (
auto *CFP = dyn_cast<ConstantFP>(Cst)) {
3705 }
else if (
Op.getResNo() == 0) {
3706 KnownBits Known0(!LD->getMemoryVT().isScalableVT()
3707 ? LD->getMemoryVT().getFixedSizeInBits()
3709 EVT VT =
Op.getValueType();
3716 if (
const MDNode *MD = LD->getRanges()) {
3727 if (LD->getMemoryVT().isVector())
3728 Known0 = Known0.
trunc(LD->getMemoryVT().getScalarSizeInBits());
3745 if (
Op.getValueType().isScalableVector())
3747 EVT InVT =
Op.getOperand(0).getValueType();
3759 if (
Op.getValueType().isScalableVector())
3761 EVT InVT =
Op.getOperand(0).getValueType();
3777 if (
Op.getValueType().isScalableVector())
3779 EVT InVT =
Op.getOperand(0).getValueType();
3796 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3799 Known.
Zero |= (~InMask);
3800 Known.
One &= (~Known.Zero);
3804 unsigned LogOfAlign =
Log2(cast<AssertAlignSDNode>(
Op)->
getAlign());
3824 Op.getOpcode() ==
ISD::ADD, Flags.hasNoSignedWrap(),
3825 Flags.hasNoUnsignedWrap(), Known, Known2);
3832 if (
Op.getResNo() == 1) {
3843 "We only compute knownbits for the difference here.");
3850 Borrow = Borrow.
trunc(1);
3864 if (
Op.getResNo() == 1) {
3875 assert(
Op.getResNo() == 0 &&
"We only compute knownbits for the sum here.");
3885 Carry = Carry.
trunc(1);
3921 const unsigned Index =
Op.getConstantOperandVal(1);
3922 const unsigned EltBitWidth =
Op.getValueSizeInBits();
3929 Known = Known.
trunc(EltBitWidth);
3945 Known = Known.
trunc(EltBitWidth);
3950 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
3951 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
3961 if (
Op.getValueType().isScalableVector())
3970 bool DemandedVal =
true;
3971 APInt DemandedVecElts = DemandedElts;
3972 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
3973 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
3974 unsigned EltIdx = CEltNo->getZExtValue();
3975 DemandedVal = !!DemandedElts[EltIdx];
3984 if (!!DemandedVecElts) {
4002 Known = Known2.
abs();
4033 if (CstLow && CstHigh) {
4038 const APInt &ValueHigh = CstHigh->getAPIntValue();
4039 if (ValueLow.
sle(ValueHigh)) {
4042 unsigned MinSignBits = std::min(LowSignBits, HighSignBits);
4065 if (IsMax && CstLow) {
4089 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
4094 if (
Op.getResNo() == 1) {
4121 cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
4123 if (
Op.getResNo() == 0) {
4147 if (
Op.getValueType().isScalableVector())
4294 return C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2();
4302 if (
C &&
C->getAPIntValue() == 1)
4312 if (
C &&
C->getAPIntValue().isSignMask())
4324 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(E))
4325 return C->getAPIntValue().zextOrTrunc(BitWidth).isPowerOf2();
4333 if (
C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2())
4370 EVT VT =
Op.getValueType();
4382 unsigned Depth)
const {
4383 EVT VT =
Op.getValueType();
4388 unsigned FirstAnswer = 1;
4390 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
4391 const APInt &Val =
C->getAPIntValue();
4401 unsigned Opcode =
Op.getOpcode();
4405 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4406 return VTBits-Tmp+1;
4408 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4415 unsigned NumSrcBits =
Op.getOperand(0).getValueSizeInBits();
4417 if (NumSrcSignBits > (NumSrcBits - VTBits))
4418 return NumSrcSignBits - (NumSrcBits - VTBits);
4425 if (!DemandedElts[i])
4432 APInt T =
C->getAPIntValue().trunc(VTBits);
4433 Tmp2 =
T.getNumSignBits();
4437 if (
SrcOp.getValueSizeInBits() != VTBits) {
4439 "Expected BUILD_VECTOR implicit truncation");
4440 unsigned ExtraBits =
SrcOp.getValueSizeInBits() - VTBits;
4441 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
4444 Tmp = std::min(Tmp, Tmp2);
4451 APInt DemandedLHS, DemandedRHS;
4455 DemandedLHS, DemandedRHS))
4458 Tmp = std::numeric_limits<unsigned>::max();
4461 if (!!DemandedRHS) {
4463 Tmp = std::min(Tmp, Tmp2);
4468 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4484 if (VTBits == SrcBits)
4490 if ((SrcBits % VTBits) == 0) {
4493 unsigned Scale = SrcBits / VTBits;
4494 APInt SrcDemandedElts =
4504 for (
unsigned i = 0; i != NumElts; ++i)
4505 if (DemandedElts[i]) {
4506 unsigned SubOffset = i % Scale;
4507 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset);
4508 SubOffset = SubOffset * VTBits;
4509 if (Tmp <= SubOffset)
4511 Tmp2 = std::min(Tmp2, Tmp - SubOffset);
4520 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4521 return VTBits - Tmp + 1;
4523 Tmp = VTBits -
Op.getOperand(0).getScalarValueSizeInBits();
4527 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4530 return std::max(Tmp, Tmp2);
4535 EVT SrcVT = Src.getValueType();
4543 if (
const APInt *ShAmt =
4545 Tmp = std::min<uint64_t>(Tmp + ShAmt->getZExtValue(), VTBits);
4548 if (
const APInt *ShAmt =
4552 if (ShAmt->ult(Tmp))
4553 return Tmp - ShAmt->getZExtValue();
4563 FirstAnswer = std::min(Tmp, Tmp2);
4573 if (Tmp == 1)
return 1;
4575 return std::min(Tmp, Tmp2);
4578 if (Tmp == 1)
return 1;
4580 return std::min(Tmp, Tmp2);
4592 if (CstLow && CstHigh) {
4597 Tmp2 = CstHigh->getAPIntValue().getNumSignBits();
4598 return std::min(Tmp, Tmp2);
4607 return std::min(Tmp, Tmp2);
4615 return std::min(Tmp, Tmp2);
4626 if (
Op.getResNo() != 1)
4640 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
4657 unsigned RotAmt =
C->getAPIntValue().urem(VTBits);
4661 RotAmt = (VTBits - RotAmt) % VTBits;
4665 if (Tmp > (RotAmt + 1))
return (Tmp - RotAmt);
4673 if (Tmp == 1)
return 1;
4678 if (CRHS->isAllOnes()) {
4684 if ((Known.
Zero | 1).isAllOnes())
4694 if (Tmp2 == 1)
return 1;
4695 return std::min(Tmp, Tmp2) - 1;
4698 if (Tmp2 == 1)
return 1;
4703 if (CLHS->isZero()) {
4708 if ((Known.
Zero | 1).isAllOnes())
4722 if (Tmp == 1)
return 1;
4723 return std::min(Tmp, Tmp2) - 1;
4727 if (SignBitsOp0 == 1)
4730 if (SignBitsOp1 == 1)
4732 unsigned OutValidBits =
4733 (VTBits - SignBitsOp0 + 1) + (VTBits - SignBitsOp1 + 1);
4734 return OutValidBits > VTBits ? 1 : VTBits - OutValidBits + 1;
4744 unsigned NumSrcBits =
Op.getOperand(0).getScalarValueSizeInBits();
4746 if (NumSrcSignBits > (NumSrcBits - VTBits))
4747 return NumSrcSignBits - (NumSrcBits - VTBits);
4754 const int BitWidth =
Op.getValueSizeInBits();
4755 const int Items =
Op.getOperand(0).getValueSizeInBits() /
BitWidth;
4759 const int rIndex = Items - 1 -
Op.getConstantOperandVal(1);
4774 bool DemandedVal =
true;
4775 APInt DemandedVecElts = DemandedElts;
4776 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
4777 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
4778 unsigned EltIdx = CEltNo->getZExtValue();
4779 DemandedVal = !!DemandedElts[EltIdx];
4782 Tmp = std::numeric_limits<unsigned>::max();
4788 Tmp = std::min(Tmp, Tmp2);
4790 if (!!DemandedVecElts) {
4792 Tmp = std::min(Tmp, Tmp2);
4794 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4805 const unsigned BitWidth =
Op.getValueSizeInBits();
4806 const unsigned EltBitWidth =
Op.getOperand(0).getScalarValueSizeInBits();
4818 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
4819 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
4829 if (Src.getValueType().isScalableVector())
4832 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
4841 Tmp = std::numeric_limits<unsigned>::max();
4842 EVT SubVectorVT =
Op.getOperand(0).getValueType();
4845 for (
unsigned i = 0; (i < NumSubVectors) && (Tmp > 1); ++i) {
4847 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
4851 Tmp = std::min(Tmp, Tmp2);
4853 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4866 APInt DemandedSrcElts = DemandedElts;
4869 Tmp = std::numeric_limits<unsigned>::max();
4870 if (!!DemandedSubElts) {
4875 if (!!DemandedSrcElts) {
4877 Tmp = std::min(Tmp, Tmp2);
4879 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4884 if (
const MDNode *Ranges = LD->getRanges()) {
4885 if (DemandedElts != 1)
4890 switch (LD->getExtensionType()) {
4925 Tmp = cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
4927 if (
Op.getResNo() == 0) {
4931 return VTBits - Tmp + 1;
4933 return VTBits - Tmp;
4937 return VTBits - Tmp + 1;
4939 return VTBits - Tmp;
4947 if (
Op.getResNo() == 0) {
4950 unsigned ExtType = LD->getExtensionType();
4954 Tmp = LD->getMemoryVT().getScalarSizeInBits();
4955 return VTBits - Tmp + 1;
4957 Tmp = LD->getMemoryVT().getScalarSizeInBits();
4958 return VTBits - Tmp;
4963 Type *CstTy = Cst->getType();
4968 for (
unsigned i = 0; i != NumElts; ++i) {
4969 if (!DemandedElts[i])
4972 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
4974 Tmp = std::min(Tmp,
Value.getNumSignBits());
4977 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
4978 APInt Value = CFP->getValueAPF().bitcastToAPInt();
4979 Tmp = std::min(Tmp,
Value.getNumSignBits());
5005 FirstAnswer = std::max(FirstAnswer, NumBits);
5016 unsigned Depth)
const {
5018 return Op.getScalarValueSizeInBits() - SignBits + 1;
5022 const APInt &DemandedElts,
5023 unsigned Depth)
const {
5025 return Op.getScalarValueSizeInBits() - SignBits + 1;
5029 unsigned Depth)
const {
5035 EVT VT =
Op.getValueType();
5046 const APInt &DemandedElts,
5048 unsigned Depth)
const {
5049 unsigned Opcode =
Op.getOpcode();
5076 if (!DemandedElts[i])
5105 return isGuaranteedNotToBeUndefOrPoison(V, PoisonOnly, Depth + 1);
5111 unsigned Depth)
const {
5113 EVT VT =
Op.getValueType();
5126 unsigned Depth)
const {
5128 EVT VT =
Op.getValueType();
5132 if (ConsiderFlags &&
Op->hasPoisonGeneratingFlags())
5135 unsigned Opcode =
Op.getOpcode();
5162 if (
Op.getOperand(0).getValueType().isInteger())
5170 if (((
unsigned)CCCode & 0x10U))
5195 EVT VecVT =
Op.getOperand(0).getValueType();
5202 EVT VecVT =
Op.getOperand(0).getValueType();
5221 unsigned Opcode =
Op.getOpcode();
5223 return Op->getFlags().hasDisjoint() ||
5245 return !
C->getValueAPF().isNaN() ||
5246 (SNaN && !
C->getValueAPF().isSignaling());
5249 unsigned Opcode =
Op.getOpcode();
5357 assert(
Op.getValueType().isFloatingPoint() &&
5358 "Floating point type expected");
5369 assert(!
Op.getValueType().isFloatingPoint() &&
5370 "Floating point types unsupported - use isKnownNeverZeroFloat");
5379 switch (
Op.getOpcode()) {
5393 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5397 if (ValKnown.
One[0])
5457 if (
Op->getFlags().hasExact())
5473 if (
Op->getFlags().hasExact())
5478 if (
Op->getFlags().hasNoUnsignedWrap())
5489 std::optional<bool> ne =
5496 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5512 if (
A ==
B)
return true;
5517 if (CA->isZero() && CB->isZero())
return true;
5526 return V.getOperand(0);
5533 SDValue ExtArg = V.getOperand(0);
5552 NotOperand = NotOperand->getOperand(0);
5554 if (
Other == NotOperand)
5557 return NotOperand ==
Other->getOperand(0) ||
5558 NotOperand ==
Other->getOperand(1);
5564 A =
A->getOperand(0);
5567 B =
B->getOperand(0);
5570 return MatchNoCommonBitsPattern(
A->getOperand(0),
A->getOperand(1),
B) ||
5571 MatchNoCommonBitsPattern(
A->getOperand(1),
A->getOperand(0),
B);
5577 assert(
A.getValueType() ==
B.getValueType() &&
5578 "Values must have the same type");
5588 if (cast<ConstantSDNode>(Step)->
isZero())
5597 int NumOps = Ops.
size();
5598 assert(NumOps != 0 &&
"Can't build an empty vector!");
5600 "BUILD_VECTOR cannot be used with scalable types");
5602 "Incorrect element count in BUILD_VECTOR!");
5610 bool IsIdentity =
true;
5611 for (
int i = 0; i != NumOps; ++i) {
5613 Ops[i].getOperand(0).getValueType() != VT ||
5614 (IdentitySrc && Ops[i].getOperand(0) != IdentitySrc) ||
5615 !isa<ConstantSDNode>(Ops[i].getOperand(1)) ||
5616 Ops[i].getConstantOperandAPInt(1) != i) {
5620 IdentitySrc = Ops[i].getOperand(0);
5633 assert(!Ops.
empty() &&
"Can't concatenate an empty list of vectors!");
5636 return Ops[0].getValueType() ==
Op.getValueType();
5638 "Concatenation of vectors with inconsistent value types!");
5639 assert((Ops[0].getValueType().getVectorElementCount() * Ops.
size()) ==
5641 "Incorrect element count in vector concatenation!");
5643 if (Ops.
size() == 1)
5654 bool IsIdentity =
true;
5655 for (
unsigned i = 0, e = Ops.
size(); i != e; ++i) {
5657 unsigned IdentityIndex = i *
Op.getValueType().getVectorMinNumElements();
5659 Op.getOperand(0).getValueType() != VT ||
5660 (IdentitySrc &&
Op.getOperand(0) != IdentitySrc) ||
5661 Op.getConstantOperandVal(1) != IdentityIndex) {
5665 assert((!IdentitySrc || IdentitySrc ==
Op.getOperand(0)) &&
5666 "Unexpected identity source vector for concat of extracts");
5667 IdentitySrc =
Op.getOperand(0);
5670 assert(IdentitySrc &&
"Failed to set source vector of extracts");
5685 EVT OpVT =
Op.getValueType();
5697 SVT = (SVT.
bitsLT(
Op.getValueType()) ?
Op.getValueType() : SVT);
5721 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
5724 auto *
N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
5725 CSEMap.InsertNode(
N, IP);
5738 return getNode(Opcode,
DL, VT, N1, Flags);
5789 "STEP_VECTOR can only be used with scalable types");
5792 "Unexpected step operand");
5814 "Invalid FP cast!");
5818 "Vector element count mismatch!");
5836 "Invalid SIGN_EXTEND!");
5838 "SIGN_EXTEND result type type should be vector iff the operand "
5843 "Vector element count mismatch!");
5857 "Invalid ZERO_EXTEND!");
5859 "ZERO_EXTEND result type type should be vector iff the operand "
5864 "Vector element count mismatch!");
5895 "Invalid ANY_EXTEND!");
5897 "ANY_EXTEND result type type should be vector iff the operand "
5902 "Vector element count mismatch!");
5927 "Invalid TRUNCATE!");
5929 "TRUNCATE result type type should be vector iff the operand "
5934 "Vector element count mismatch!");
5957 assert(VT.
isVector() &&
"This DAG node is restricted to vector types.");
5959 "The input must be the same size or smaller than the result.");
5962 "The destination vector type must have fewer lanes than the input.");
5972 "BSWAP types must be a multiple of 16 bits!");
5986 "Cannot BITCAST between types of different sizes!");
5999 "Illegal SCALAR_TO_VECTOR node!");
6056 "Wrong operand type!");
6063 if (VT != MVT::Glue) {
6067 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
6068 E->intersectFlagsWith(Flags);
6072 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
6074 createOperands(
N, Ops);
6075 CSEMap.InsertNode(
N, IP);
6077 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
6078 createOperands(
N, Ops);
6112 if (!C2.getBoolValue())
6116 if (!C2.getBoolValue())
6120 if (!C2.getBoolValue())
6124 if (!C2.getBoolValue())
6144 return std::nullopt;
6149 bool IsUndef1,
const APInt &C2,
6151 if (!(IsUndef1 || IsUndef2))
6159 return std::nullopt;
6169 auto *C2 = dyn_cast<ConstantSDNode>(N2);
6172 int64_t
Offset = C2->getSExtValue();
6190 assert(Ops.
size() == 2 &&
"Div/rem should have 2 operands");
6197 [](
SDValue V) { return V.isUndef() ||
6198 isNullConstant(V); });
6218 unsigned NumOps = Ops.
size();
6234 if (
auto *
C = dyn_cast<ConstantSDNode>(N1)) {
6235 const APInt &Val =
C->getAPIntValue();
6239 C->isTargetOpcode(),
C->isOpaque());
6246 C->isTargetOpcode(),
C->isOpaque());
6251 C->isTargetOpcode(),
C->isOpaque());
6253 C->isTargetOpcode(),
C->isOpaque());
6300 if (VT == MVT::f16 &&
C->getValueType(0) == MVT::i16)
6302 if (VT == MVT::f32 &&
C->getValueType(0) == MVT::i32)
6304 if (VT == MVT::f64 &&
C->getValueType(0) == MVT::i64)
6306 if (VT == MVT::f128 &&
C->getValueType(0) == MVT::i128)
6313 if (
auto *
C = dyn_cast<ConstantFPSDNode>(N1)) {
6367 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6370 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::f16)
6373 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::bf16)
6376 if (VT == MVT::i32 &&
C->getValueType(0) == MVT::f32)
6379 if (VT == MVT::i64 &&
C->getValueType(0) == MVT::f64)
6380 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6395 if (
auto *C1 = dyn_cast<ConstantSDNode>(Ops[0])) {
6396 if (
auto *C2 = dyn_cast<ConstantSDNode>(Ops[1])) {
6397 if (C1->isOpaque() || C2->isOpaque())
6400 std::optional<APInt> FoldAttempt =
6401 FoldValue(Opcode, C1->getAPIntValue(), C2->getAPIntValue());
6407 "Can't fold vectors ops with scalar operands");
6428 Ops[0].getValueType() == VT && Ops[1].getValueType() == VT &&
6433 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
6434 auto *BV2 = dyn_cast<BuildVectorSDNode>(N2);
6441 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) &&
6442 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2)) {
6446 Opcode, RawBits1[
I], UndefElts1[
I], RawBits2[
I], UndefElts2[
I]);
6457 DstBits, RawBits, DstUndefs,
6459 EVT BVEltVT = BV1->getOperand(0).getValueType();
6462 for (
unsigned I = 0, E = DstBits.
size();
I != E; ++
I) {
6480 ? Ops[0].getConstantOperandAPInt(0) * RHSVal
6481 : Ops[0].getConstantOperandAPInt(0) << RHSVal;
6486 auto IsScalarOrSameVectorSize = [NumElts](
const SDValue &
Op) {
6487 return !
Op.getValueType().isVector() ||
6488 Op.getValueType().getVectorElementCount() == NumElts;
6491 auto IsBuildVectorSplatVectorOrUndef = [](
const SDValue &
Op) {
6500 if (!
llvm::all_of(Ops, IsBuildVectorSplatVectorOrUndef) ||
6529 for (
unsigned I = 0;
I != NumVectorElts;
I++) {
6532 EVT InSVT =
Op.getValueType().getScalarType();
6554 !isa<ConstantSDNode>(ScalarOp) &&
6568 if (LegalSVT != SVT)
6569 ScalarResult =
getNode(ExtendCode,
DL, LegalSVT, ScalarResult);
6587 if (Ops.
size() != 2)
6598 if (N1CFP && N2CFP) {
6645 if (N1C && N1C->getValueAPF().isNegZero() && N2.
isUndef())
6674 ID.AddInteger(
A.value());
6677 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
6681 newSDNode<AssertAlignSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs,
A);
6682 createOperands(
N, {Val});
6684 CSEMap.InsertNode(
N, IP);
6697 return getNode(Opcode,
DL, VT, N1, N2, Flags);
6711 if ((N1C && !N2C) || (N1CFP && !N2CFP))
6725 "Operand is DELETED_NODE!");
6729 auto *N1C = dyn_cast<ConstantSDNode>(N1);
6730 auto *N2C = dyn_cast<ConstantSDNode>(N2);
6741 N2.
getValueType() == MVT::Other &&
"Invalid token factor!");
6745 if (N1 == N2)
return N1;
6761 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6763 N1.
getValueType() == VT &&
"Binary operator types must match!");
6766 if (N2CV && N2CV->
isZero())
6775 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6777 N1.
getValueType() == VT &&
"Binary operator types must match!");
6780 if (N2CV && N2CV->
isZero())
6787 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6789 N1.
getValueType() == VT &&
"Binary operator types must match!");
6794 const APInt &N2CImm = N2C->getAPIntValue();
6808 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6810 N1.
getValueType() == VT &&
"Binary operator types must match!");
6822 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6824 N1.
getValueType() == VT &&
"Binary operator types must match!");
6828 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6830 N1.
getValueType() == VT &&
"Binary operator types must match!");
6836 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6838 N1.
getValueType() == VT &&
"Binary operator types must match!");
6849 N1.
getValueType() == VT &&
"Binary operator types must match!");
6857 "Invalid FCOPYSIGN!");
6862 const APInt &ShiftImm = N2C->getAPIntValue();
6874 "Shift operators return type must be the same as their first arg");
6876 "Shifts only work on integers");
6878 "Vector shift amounts must be in the same as their first arg");
6885 "Invalid use of small shift amount with oversized value!");
6892 if (N2CV && N2CV->
isZero())
6899 N2C && (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
6900 "Invalid FP_ROUND!");
6905 EVT EVT = cast<VTSDNode>(N2)->getVT();
6908 "Cannot *_EXTEND_INREG FP types");
6910 "AssertSExt/AssertZExt type should be the vector element type "
6911 "rather than the vector type!");
6917 EVT EVT = cast<VTSDNode>(N2)->getVT();
6920 "Cannot *_EXTEND_INREG FP types");
6922 "SIGN_EXTEND_INREG type should be vector iff the operand "
6926 "Vector element counts must match in SIGN_EXTEND_INREG");
6928 if (
EVT == VT)
return N1;
6938 const APInt &Val = N1C->getAPIntValue();
6939 return SignExtendInReg(Val, VT);
6952 APInt Val =
C->getAPIntValue();
6953 Ops.
push_back(SignExtendInReg(Val, OpVT));
6971 "FP_TO_*INT_SAT type should be vector iff the operand type is "
6975 "Vector element counts must match in FP_TO_*INT_SAT");
6976 assert(!cast<VTSDNode>(N2)->getVT().isVector() &&
6977 "Type to saturate to must be a scalar.");
6984 "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \
6985 element type of the vector.");
7017 "BUILD_VECTOR used for scalable vectors");
7040 if (N1Op2C && N2C) {
7070 assert(N2C && (
unsigned)N2C->getZExtValue() < 2 &&
"Bad EXTRACT_ELEMENT!");
7074 "Wrong types for EXTRACT_ELEMENT!");
7085 unsigned Shift = ElementSize * N2C->getZExtValue();
7086 const APInt &Val = N1C->getAPIntValue();
7093 "Extract subvector VTs must be vectors!");
7095 "Extract subvector VTs must have the same element type!");
7097 "Cannot extract a scalable vector from a fixed length vector!");
7100 "Extract subvector must be from larger vector to smaller vector!");
7101 assert(N2C &&
"Extract subvector index must be a constant");
7105 "Extract subvector overflow!");
7106 assert(N2C->getAPIntValue().getBitWidth() ==
7108 "Constant index for EXTRACT_SUBVECTOR has an invalid size");
7123 return N1.
getOperand(N2C->getZExtValue() / Factor);
7191 if (VT != MVT::Glue) {
7195 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7196 E->intersectFlagsWith(Flags);
7200 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7202 createOperands(
N, Ops);
7203 CSEMap.InsertNode(
N, IP);
7205 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7206 createOperands(
N, Ops);
7220 return getNode(Opcode,
DL, VT, N1, N2, N3, Flags);
7229 "Operand is DELETED_NODE!");
7240 if (N1CFP && N2CFP && N3CFP) {
7269 "SETCC operands must have the same type!");
7271 "SETCC type should be vector iff the operand type is vector!");
7274 "SETCC vector element counts must match!");
7294 if (cast<ConstantSDNode>(N3)->
isZero())
7324 "Dest and insert subvector source types must match!");
7326 "Insert subvector VTs must be vectors!");
7328 "Insert subvector VTs must have the same element type!");
7330 "Cannot insert a scalable vector into a fixed length vector!");
7333 "Insert subvector must be from smaller vector to larger vector!");
7334 assert(isa<ConstantSDNode>(N3) &&
7335 "Insert subvector index must be constant");
7339 "Insert subvector overflow!");
7342 "Constant index for INSERT_SUBVECTOR has an invalid size");
7360 case ISD::VP_TRUNCATE:
7361 case ISD::VP_SIGN_EXTEND:
7362 case ISD::VP_ZERO_EXTEND:
7373 if (VT != MVT::Glue) {
7377 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7378 E->intersectFlagsWith(Flags);
7382 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7384 createOperands(
N, Ops);
7385 CSEMap.InsertNode(
N, IP);
7387 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7388 createOperands(
N, Ops);
7399 SDValue Ops[] = { N1, N2, N3, N4 };
7406 SDValue Ops[] = { N1, N2, N3, N4, N5 };
7424 if (FI->getIndex() < 0)
7439 assert(
C->getAPIntValue().getBitWidth() == 8);
7444 return DAG.
getConstant(Val, dl, VT,
false, IsOpaque);
7450 assert(
Value.getValueType() == MVT::i8 &&
"memset with non-byte fill value?");
7466 if (VT !=
Value.getValueType())
7479 if (Slice.
Array ==
nullptr) {
7482 if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
7497 unsigned NumVTBytes = NumVTBits / 8;
7498 unsigned NumBytes = std::min(NumVTBytes,
unsigned(Slice.
Length));
7500 APInt Val(NumVTBits, 0);
7502 for (
unsigned i = 0; i != NumBytes; ++i)
7505 for (
unsigned i = 0; i != NumBytes; ++i)
7506 Val |= (
uint64_t)(
unsigned char)Slice[i] << (NumVTBytes-i-1)*8;
7525 APInt(
Base.getValueSizeInBits().getFixedValue(),
7526 Offset.getKnownMinValue()));
7537 EVT BasePtrVT =
Ptr.getValueType();
7546 G = cast<GlobalAddressSDNode>(Src);
7547 else if (Src.getOpcode() ==
ISD::ADD &&
7550 G = cast<GlobalAddressSDNode>(Src.getOperand(0));
7551 SrcDelta = Src.getConstantOperandVal(1);
7557 SrcDelta +
G->getOffset());
7573 assert(OutLoadChains.
size() &&
"Missing loads in memcpy inlining");
7574 assert(OutStoreChains.
size() &&
"Missing stores in memcpy inlining");
7576 for (
unsigned i =
From; i < To; ++i) {
7578 GluedLoadChains.
push_back(OutLoadChains[i]);
7585 for (
unsigned i =
From; i < To; ++i) {
7586 StoreSDNode *ST = dyn_cast<StoreSDNode>(OutStoreChains[i]);
7588 ST->getBasePtr(), ST->getMemoryVT(),
7589 ST->getMemOperand());
7597 bool isVol,
bool AlwaysInline,
7613 std::vector<EVT> MemOps;
7614 bool DstAlignCanChange =
false;
7620 DstAlignCanChange =
true;
7622 if (!SrcAlign || Alignment > *SrcAlign)
7623 SrcAlign = Alignment;
7624 assert(SrcAlign &&
"SrcAlign must be set");
7628 bool isZeroConstant = CopyFromConstant && Slice.
Array ==
nullptr;
7630 const MemOp Op = isZeroConstant
7634 *SrcAlign, isVol, CopyFromConstant);
7640 if (DstAlignCanChange) {
7641 Type *Ty = MemOps[0].getTypeForEVT(
C);
7642 Align NewAlign =
DL.getABITypeAlign(Ty);
7648 if (!
TRI->hasStackRealignment(MF))
7649 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7652 if (NewAlign > Alignment) {
7656 Alignment = NewAlign;
7664 const Value *SrcVal = dyn_cast_if_present<const Value *>(SrcPtrInfo.
V);
7674 unsigned NumMemOps = MemOps.
size();
7676 for (
unsigned i = 0; i != NumMemOps; ++i) {
7681 if (VTSize >
Size) {
7684 assert(i == NumMemOps-1 && i != 0);
7685 SrcOff -= VTSize -
Size;
7686 DstOff -= VTSize -
Size;
7689 if (CopyFromConstant &&
7697 if (SrcOff < Slice.
Length) {
7699 SubSlice.
move(SrcOff);
7702 SubSlice.
Array =
nullptr;
7704 SubSlice.
Length = VTSize;
7707 if (
Value.getNode()) {
7711 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
7716 if (!Store.getNode()) {
7725 bool isDereferenceable =
7728 if (isDereferenceable)
7743 DstPtrInfo.
getWithOffset(DstOff), VT, Alignment, MMOFlags, NewAAInfo);
7753 unsigned NumLdStInMemcpy = OutStoreChains.
size();
7755 if (NumLdStInMemcpy) {
7761 for (
unsigned i = 0; i < NumLdStInMemcpy; ++i) {
7767 if (NumLdStInMemcpy <= GluedLdStLimit) {
7769 NumLdStInMemcpy, OutLoadChains,
7772 unsigned NumberLdChain = NumLdStInMemcpy / GluedLdStLimit;
7773 unsigned RemainingLdStInMemcpy = NumLdStInMemcpy % GluedLdStLimit;
7774 unsigned GlueIter = 0;
7776 for (
unsigned cnt = 0; cnt < NumberLdChain; ++cnt) {
7777 unsigned IndexFrom = NumLdStInMemcpy - GlueIter - GluedLdStLimit;
7778 unsigned IndexTo = NumLdStInMemcpy - GlueIter;
7781 OutLoadChains, OutStoreChains);
7782 GlueIter += GluedLdStLimit;
7786 if (RemainingLdStInMemcpy) {
7788 RemainingLdStInMemcpy, OutLoadChains,
7800 bool isVol,
bool AlwaysInline,
7814 std::vector<EVT> MemOps;
7815 bool DstAlignCanChange =
false;
7821 DstAlignCanChange =
true;
7823 if (!SrcAlign || Alignment > *SrcAlign)
7824 SrcAlign = Alignment;
7825 assert(SrcAlign &&
"SrcAlign must be set");
7835 if (DstAlignCanChange) {
7836 Type *Ty = MemOps[0].getTypeForEVT(
C);
7837 Align NewAlign =
DL.getABITypeAlign(Ty);
7843 if (!
TRI->hasStackRealignment(MF))
7844 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7847 if (NewAlign > Alignment) {
7851 Alignment = NewAlign;
7865 unsigned NumMemOps = MemOps.
size();
7866 for (
unsigned i = 0; i < NumMemOps; i++) {
7871 bool isDereferenceable =
7874 if (isDereferenceable)
7880 SrcPtrInfo.
getWithOffset(SrcOff), *SrcAlign, SrcMMOFlags, NewAAInfo);
7887 for (
unsigned i = 0; i < NumMemOps; i++) {
7893 Chain, dl, LoadValues[i],
7895 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
7935 std::vector<EVT> MemOps;
7936 bool DstAlignCanChange =
false;
7942 DstAlignCanChange =
true;
7948 MemOp::Set(
Size, DstAlignCanChange, Alignment, IsZeroVal, isVol),
7952 if (DstAlignCanChange) {
7955 Align NewAlign =
DL.getABITypeAlign(Ty);
7961 if (!
TRI->hasStackRealignment(MF))
7962 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7965 if (NewAlign > Alignment) {
7969 Alignment = NewAlign;
7975 unsigned NumMemOps = MemOps.size();
7978 EVT LargestVT = MemOps[0];
7979 for (
unsigned i = 1; i < NumMemOps; i++)
7980 if (MemOps[i].bitsGT(LargestVT))
7981 LargestVT = MemOps[i];
7988 for (
unsigned i = 0; i < NumMemOps; i++) {
7991 if (VTSize >
Size) {
7994 assert(i == NumMemOps-1 && i != 0);
7995 DstOff -= VTSize -
Size;
8002 if (VT.
bitsLT(LargestVT)) {
8023 assert(
Value.getValueType() == VT &&
"Value with wrong type.");
8050 bool isVol,
bool AlwaysInline,
bool isTailCall,
8059 if (ConstantSize->
isZero())
8063 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8064 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8065 if (Result.getNode())
8073 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline,
8074 DstPtrInfo, SrcPtrInfo);
8075 if (Result.getNode())
8082 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
8084 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8085 isVol,
true, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8101 Entry.Node = Dst; Args.push_back(Entry);
8102 Entry.Node = Src; Args.push_back(Entry);
8105 Entry.Node =
Size; Args.push_back(Entry);
8111 Dst.getValueType().getTypeForEVT(*
getContext()),
8118 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8119 return CallResult.second;
8124 Type *SizeTy,
unsigned ElemSz,
8133 Args.push_back(Entry);
8136 Args.push_back(Entry);
8140 Args.push_back(Entry);
8144 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8158 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8159 return CallResult.second;
8164 bool isVol,
bool isTailCall,
8173 if (ConstantSize->
isZero())
8177 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8178 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo);
8179 if (Result.getNode())
8188 Alignment, isVol, DstPtrInfo, SrcPtrInfo);
8189 if (Result.getNode())
8203 Entry.Node = Dst; Args.push_back(Entry);
8204 Entry.Node = Src; Args.push_back(Entry);
8207 Entry.Node =
Size; Args.push_back(Entry);
8213 Dst.getValueType().getTypeForEVT(*
getContext()),
8220 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8221 return CallResult.second;
8226 Type *SizeTy,
unsigned ElemSz,
8235 Args.push_back(Entry);
8238 Args.push_back(Entry);
8242 Args.push_back(Entry);
8246 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8260 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8261 return CallResult.second;
8266 bool isVol,
bool AlwaysInline,
bool isTailCall,
8274 if (ConstantSize->
isZero())
8279 isVol,
false, DstPtrInfo, AAInfo);
8281 if (Result.getNode())
8289 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline, DstPtrInfo);
8290 if (Result.getNode())
8297 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
8300 isVol,
true, DstPtrInfo, AAInfo);
8302 "getMemsetStores must return a valid sequence when AlwaysInline");
8319 const auto CreateEntry = [](
SDValue Node,
Type *Ty) {
8330 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8337 Args.push_back(CreateEntry(Src, Src.getValueType().getTypeForEVT(Ctx)));
8338 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8340 Dst.getValueType().getTypeForEVT(Ctx),
8348 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8349 return CallResult.second;
8354 Type *SizeTy,
unsigned ElemSz,
8362 Args.push_back(Entry);
8366 Args.push_back(Entry);
8370 Args.push_back(Entry);
8374 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8388 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8389 return CallResult.second;
8401 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8402 cast<AtomicSDNode>(E)->refineAlignment(MMO);
8407 VTList, MemVT, MMO);
8408 createOperands(
N, Ops);
8410 CSEMap.InsertNode(
N, IP);
8424 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8449 "Invalid Atomic Op");
8456 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8466 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8471 if (Ops.
size() == 1)
8486 if (
Size.hasValue() && !
Size.getValue())
8503 (Opcode <= (
unsigned)std::numeric_limits<int>::max() &&
8505 "Opcode is not a memory-accessing opcode!");
8509 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
8512 ID.AddInteger(getSyntheticNodeSubclassData<MemIntrinsicSDNode>(
8513 Opcode, dl.
getIROrder(), VTList, MemVT, MMO));
8518 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8519 cast<MemIntrinsicSDNode>(E)->refineAlignment(MMO);
8524 VTList, MemVT, MMO);
8525 createOperands(
N, Ops);
8527 CSEMap.InsertNode(
N, IP);
8530 VTList, MemVT, MMO);
8531 createOperands(
N, Ops);
8540 SDValue Chain,
int FrameIndex,
8552 ID.AddInteger(FrameIndex);
8556 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
8561 createOperands(
N, Ops);
8562 CSEMap.InsertNode(
N, IP);
8577 ID.AddInteger(Guid);
8580 if (
SDNode *E = FindNodeOrInsertPos(
ID, Dl, IP))
8583 auto *
N = newSDNode<PseudoProbeSDNode>(
8585 createOperands(
N, Ops);
8586 CSEMap.InsertNode(
N, IP);
8607 !isa<ConstantSDNode>(
Ptr.getOperand(1)) ||
8608 !isa<FrameIndexSDNode>(
Ptr.getOperand(0)))
8611 int FI = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
8614 Offset + cast<ConstantSDNode>(
Ptr.getOperand(1))->getSExtValue());
8625 if (
ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp))
8640 "Invalid chain type");
8652 Alignment, AAInfo, Ranges);
8663 assert(VT == MemVT &&
"Non-extending load from different memory type!");
8667 "Should only be an extending load, not truncating!");
8669 "Cannot convert from FP to Int or Int -> FP!");
8671 "Cannot use an ext load to convert to or from a vector!");
8674 "Cannot use an ext load to change the number of vector elements!");
8686 ID.AddInteger(getSyntheticNodeSubclassData<LoadSDNode>(
8687 dl.
getIROrder(), VTs, AM, ExtType, MemVT, MMO));
8691 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8692 cast<LoadSDNode>(E)->refineAlignment(MMO);
8696 ExtType, MemVT, MMO);
8697 createOperands(
N, Ops);
8699 CSEMap.InsertNode(
N, IP);
8713 PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges);
8731 MemVT, Alignment, MMOFlags, AAInfo);
8746 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
8749 LD->getMemOperand()->getFlags() &
8752 LD->getChain(),
Base,
Offset, LD->getPointerInfo(),
8753 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo());
8779 "Invalid chain type");
8787 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
8792 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8793 cast<StoreSDNode>(E)->refineAlignment(MMO);
8798 createOperands(
N, Ops);
8800 CSEMap.InsertNode(
N, IP);
8813 "Invalid chain type");
8834 "Invalid chain type");
8839 "Should only be a truncating store, not extending!");
8841 "Can't do FP-INT conversion!");
8843 "Cannot use trunc store to convert to or from a vector!");
8846 "Cannot use trunc store to change the number of vector elements!");
8854 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
8859 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8860 cast<StoreSDNode>(E)->refineAlignment(MMO);
8865 createOperands(
N, Ops);
8867 CSEMap.InsertNode(
N, IP);
8878 assert(ST->getOffset().isUndef() &&
"Store is already a indexed store!");
8883 ID.AddInteger(ST->getMemoryVT().getRawBits());
8884 ID.AddInteger(ST->getRawSubclassData());
8885 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
8886 ID.AddInteger(ST->getMemOperand()->getFlags());
8888 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
8892 ST->isTruncatingStore(), ST->getMemoryVT(),
8893 ST->getMemOperand());
8894 createOperands(
N, Ops);
8896 CSEMap.InsertNode(
N, IP);
8908 const MDNode *Ranges,
bool IsExpanding) {
8921 Alignment, AAInfo, Ranges);
8922 return getLoadVP(AM, ExtType, VT, dl, Chain,
Ptr,
Offset, Mask, EVL, MemVT,
8941 ID.AddInteger(getSyntheticNodeSubclassData<VPLoadSDNode>(
8942 dl.
getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
8946 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8947 cast<VPLoadSDNode>(E)->refineAlignment(MMO);
8951 ExtType, IsExpanding, MemVT, MMO);
8952 createOperands(
N, Ops);
8954 CSEMap.InsertNode(
N, IP);
8970 Mask, EVL, PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges,
8979 Mask, EVL, VT, MMO, IsExpanding);
8988 const AAMDNodes &AAInfo,
bool IsExpanding) {
8991 EVL, PtrInfo, MemVT, Alignment, MMOFlags, AAInfo,
nullptr,
9001 EVL, MemVT, MMO, IsExpanding);
9007 auto *LD = cast<VPLoadSDNode>(OrigLoad);
9008 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
9011 LD->getMemOperand()->getFlags() &
9015 LD->getVectorLength(), LD->getPointerInfo(),
9016 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo(),
9017 nullptr, LD->isExpandingLoad());
9024 bool IsCompressing) {
9034 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
9035 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9039 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9040 cast<VPStoreSDNode>(E)->refineAlignment(MMO);
9044 IsTruncating, IsCompressing, MemVT, MMO);
9045 createOperands(
N, Ops);
9047 CSEMap.InsertNode(
N, IP);
9060 bool IsCompressing) {
9081 bool IsCompressing) {
9088 false, IsCompressing);
9091 "Should only be a truncating store, not extending!");
9094 "Cannot use trunc store to convert to or from a vector!");
9097 "Cannot use trunc store to change the number of vector elements!");
9101 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Mask, EVL};
9105 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
9110 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9111 cast<VPStoreSDNode>(E)->refineAlignment(MMO);
9117 createOperands(
N, Ops);
9119 CSEMap.InsertNode(
N, IP);
9129 auto *ST = cast<VPStoreSDNode>(OrigStore);
9130 assert(ST->getOffset().isUndef() &&
"Store is already an indexed store!");
9132 SDValue Ops[] = {ST->getChain(), ST->getValue(),
Base,
9133 Offset, ST->getMask(), ST->getVectorLength()};
9136 ID.AddInteger(ST->getMemoryVT().getRawBits());
9137 ID.AddInteger(ST->getRawSubclassData());
9138 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
9139 ID.AddInteger(ST->getMemOperand()->getFlags());
9141 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9144 auto *
N = newSDNode<VPStoreSDNode>(
9146 ST->isCompressingStore(), ST->getMemoryVT(), ST->getMemOperand());
9147 createOperands(
N, Ops);
9149 CSEMap.InsertNode(
N, IP);
9169 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedLoadSDNode>(
9170 DL.getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
9174 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9175 cast<VPStridedLoadSDNode>(E)->refineAlignment(MMO);
9180 newSDNode<VPStridedLoadSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs, AM,
9181 ExtType, IsExpanding, MemVT, MMO);
9182 createOperands(
N, Ops);
9183 CSEMap.InsertNode(
N, IP);
9197 Undef, Stride, Mask, EVL, VT, MMO, IsExpanding);
9206 Stride, Mask, EVL, MemVT, MMO, IsExpanding);
9215 bool IsTruncating,
bool IsCompressing) {
9225 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9226 DL.getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9229 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9230 cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
9233 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9234 VTs, AM, IsTruncating,
9235 IsCompressing, MemVT, MMO);
9236 createOperands(
N, Ops);
9238 CSEMap.InsertNode(
N, IP);
9250 bool IsCompressing) {
9257 false, IsCompressing);
9260 "Should only be a truncating store, not extending!");
9263 "Cannot use trunc store to convert to or from a vector!");
9266 "Cannot use trunc store to change the number of vector elements!");
9270 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Stride, Mask, EVL};
9274 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9278 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9279 cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
9282 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9284 IsCompressing, SVT, MMO);
9285 createOperands(
N, Ops);
9287 CSEMap.InsertNode(
N, IP);
9297 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9302 ID.AddInteger(getSyntheticNodeSubclassData<VPGatherSDNode>(
9307 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9308 cast<VPGatherSDNode>(E)->refineAlignment(MMO);
9313 VT, MMO, IndexType);
9314 createOperands(
N, Ops);
9316 assert(
N->getMask().getValueType().getVectorElementCount() ==
9317 N->getValueType(0).getVectorElementCount() &&
9318 "Vector width mismatch between mask and data");
9319 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9320 N->getValueType(0).getVectorElementCount().isScalable() &&
9321 "Scalable flags of index and data do not match");
9323 N->getIndex().getValueType().getVectorElementCount(),
9324 N->getValueType(0).getVectorElementCount()) &&
9325 "Vector width mismatch between index and data");
9326 assert(isa<ConstantSDNode>(
N->getScale()) &&
9327 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9328 "Scale should be a constant power of 2");
9330 CSEMap.InsertNode(
N, IP);
9341 assert(Ops.
size() == 7 &&
"Incompatible number of operands");
9346 ID.AddInteger(getSyntheticNodeSubclassData<VPScatterSDNode>(
9351 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9352 cast<VPScatterSDNode>(E)->refineAlignment(MMO);
9356 VT, MMO, IndexType);
9357 createOperands(
N, Ops);
9359 assert(
N->getMask().getValueType().getVectorElementCount() ==
9360 N->getValue().getValueType().getVectorElementCount() &&
9361 "Vector width mismatch between mask and data");
9363 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9364 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9365 "Scalable flags of index and data do not match");
9367 N->getIndex().getValueType().getVectorElementCount(),
9368 N->getValue().getValueType().getVectorElementCount()) &&
9369 "Vector width mismatch between index and data");
9370 assert(isa<ConstantSDNode>(
N->getScale()) &&
9371 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9372 "Scale should be a constant power of 2");
9374 CSEMap.InsertNode(
N, IP);
9389 "Unindexed masked load with an offset!");
9396 ID.AddInteger(getSyntheticNodeSubclassData<MaskedLoadSDNode>(
9397 dl.
getIROrder(), VTs, AM, ExtTy, isExpanding, MemVT, MMO));
9401 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9402 cast<MaskedLoadSDNode>(E)->refineAlignment(MMO);
9406 AM, ExtTy, isExpanding, MemVT, MMO);
9407 createOperands(
N, Ops);
9409 CSEMap.InsertNode(
N, IP);
9420 assert(LD->getOffset().isUndef() &&
"Masked load is already a indexed load!");
9422 Offset, LD->getMask(), LD->getPassThru(),
9423 LD->getMemoryVT(), LD->getMemOperand(), AM,
9424 LD->getExtensionType(), LD->isExpandingLoad());
9432 bool IsCompressing) {
9434 "Invalid chain type");
9437 "Unindexed masked store with an offset!");
9444 ID.AddInteger(getSyntheticNodeSubclassData<MaskedStoreSDNode>(
9445 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9449 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9450 cast<MaskedStoreSDNode>(E)->refineAlignment(MMO);
9455 IsTruncating, IsCompressing, MemVT, MMO);
9456 createOperands(
N, Ops);
9458 CSEMap.InsertNode(
N, IP);
9469 assert(ST->getOffset().isUndef() &&
9470 "Masked store is already a indexed store!");
9472 ST->getMask(), ST->getMemoryVT(), ST->getMemOperand(),
9473 AM, ST->isTruncatingStore(), ST->isCompressingStore());
9481 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9486 ID.AddInteger(getSyntheticNodeSubclassData<MaskedGatherSDNode>(
9487 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, ExtTy));
9491 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9492 cast<MaskedGatherSDNode>(E)->refineAlignment(MMO);
9497 VTs, MemVT, MMO, IndexType, ExtTy);
9498 createOperands(
N, Ops);
9500 assert(
N->getPassThru().getValueType() ==
N->getValueType(0) &&
9501 "Incompatible type of the PassThru value in MaskedGatherSDNode");
9502 assert(
N->getMask().getValueType().getVectorElementCount() ==
9503 N->getValueType(0).getVectorElementCount() &&
9504 "Vector width mismatch between mask and data");
9505 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9506 N->getValueType(0).getVectorElementCount().isScalable() &&
9507 "Scalable flags of index and data do not match");
9509 N->getIndex().getValueType().getVectorElementCount(),
9510 N->getValueType(0).getVectorElementCount()) &&
9511 "Vector width mismatch between index and data");
9512 assert(isa<ConstantSDNode>(
N->getScale()) &&
9513 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9514 "Scale should be a constant power of 2");
9516 CSEMap.InsertNode(
N, IP);
9528 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9533 ID.AddInteger(getSyntheticNodeSubclassData<MaskedScatterSDNode>(
9534 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, IsTrunc));
9538 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9539 cast<MaskedScatterSDNode>(E)->refineAlignment(MMO);
9544 VTs, MemVT, MMO, IndexType, IsTrunc);
9545 createOperands(
N, Ops);
9547 assert(
N->getMask().getValueType().getVectorElementCount() ==
9548 N->getValue().getValueType().getVectorElementCount() &&
9549 "Vector width mismatch between mask and data");
9551 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9552 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9553 "Scalable flags of index and data do not match");
9555 N->getIndex().getValueType().getVectorElementCount(),
9556 N->getValue().getValueType().getVectorElementCount()) &&
9557 "Vector width mismatch between index and data");
9558 assert(isa<ConstantSDNode>(
N->getScale()) &&
9559 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9560 "Scale should be a constant power of 2");
9562 CSEMap.InsertNode(
N, IP);
9577 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9582 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9587 createOperands(
N, Ops);
9589 CSEMap.InsertNode(
N, IP);
9604 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9609 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9614 createOperands(
N, Ops);
9616 CSEMap.InsertNode(
N, IP);
9636 if (
auto *CondC = dyn_cast<ConstantSDNode>(
Cond))
9637 return CondC->isZero() ?
F :
T;
9643 if (CondC->isZero())
9669 return !Val || Val->getAPIntValue().uge(
X.getScalarValueSizeInBits());
9675 if (
X.getValueType().getScalarType() == MVT::i1)
9688 bool HasNan = (XC && XC->getValueAPF().isNaN()) ||
9690 bool HasInf = (XC && XC->getValueAPF().isInfinity()) ||
9693 if (Flags.hasNoNaNs() && (HasNan ||
X.isUndef() ||
Y.isUndef()))
9696 if (Flags.hasNoInfs() && (HasInf ||
X.isUndef() ||
Y.isUndef()))
9719 if (Opcode ==
ISD::FMUL && Flags.hasNoNaNs() && Flags.hasNoSignedZeros())
9734 switch (Ops.
size()) {
9736 case 1:
return getNode(Opcode,
DL, VT,
static_cast<const SDValue>(Ops[0]));
9737 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1]);
9738 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2]);
9753 return getNode(Opcode,
DL, VT, Ops, Flags);
9758 unsigned NumOps = Ops.
size();
9761 case 1:
return getNode(Opcode,
DL, VT, Ops[0], Flags);
9762 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Flags);
9763 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2], Flags);
9768 for (
const auto &
Op : Ops)
9770 "Operand is DELETED_NODE!");
9785 assert(NumOps == 5 &&
"SELECT_CC takes 5 operands!");
9787 "LHS and RHS of condition must have same type!");
9789 "True and False arms of SelectCC must have same type!");
9791 "select_cc node must be of same type as true and false value!");
9795 "Expected select_cc with vector result to have the same sized "
9796 "comparison type!");
9799 assert(NumOps == 5 &&
"BR_CC takes 5 operands!");
9801 "LHS/RHS of comparison should match types!");
9807 Opcode = ISD::VP_XOR;
9812 Opcode = ISD::VP_AND;
9814 case ISD::VP_REDUCE_MUL:
9817 Opcode = ISD::VP_REDUCE_AND;
9819 case ISD::VP_REDUCE_ADD:
9822 Opcode = ISD::VP_REDUCE_XOR;
9824 case ISD::VP_REDUCE_SMAX:
9825 case ISD::VP_REDUCE_UMIN:
9829 Opcode = ISD::VP_REDUCE_AND;
9831 case ISD::VP_REDUCE_SMIN:
9832 case ISD::VP_REDUCE_UMAX:
9836 Opcode = ISD::VP_REDUCE_OR;
9844 if (VT != MVT::Glue) {
9849 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
9852 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
9853 createOperands(
N, Ops);
9855 CSEMap.InsertNode(
N, IP);
9857 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
9858 createOperands(
N, Ops);
9878 return getNode(Opcode,
DL, VTList, Ops, Flags);
9887 for (
const auto &
Op : Ops)
9889 "Operand is DELETED_NODE!");
9898 "Invalid add/sub overflow op!");
9900 Ops[0].getValueType() == Ops[1].getValueType() &&
9901 Ops[0].getValueType() == VTList.
VTs[0] &&
9902 "Binary operator types must match!");
9903 SDValue N1 = Ops[0], N2 = Ops[1];
9909 if (N2CV && N2CV->
isZero()) {
9941 "Invalid add/sub overflow op!");
9943 Ops[0].getValueType() == Ops[1].getValueType() &&
9944 Ops[0].getValueType() == VTList.
VTs[0] &&
9945 Ops[2].getValueType() == VTList.
VTs[1] &&
9946 "Binary operator types must match!");
9952 VTList.
VTs[0] == Ops[0].getValueType() &&
9953 VTList.
VTs[0] == Ops[1].getValueType() &&
9954 "Binary operator types must match!");
9960 unsigned OutWidth = Width * 2;
9964 Val = Val.
sext(OutWidth);
9965 Mul =
Mul.sext(OutWidth);
9967 Val = Val.
zext(OutWidth);
9968 Mul =
Mul.zext(OutWidth);
9982 VTList.
VTs[0] == Ops[0].getValueType() &&
"frexp type mismatch");
9998 "Invalid STRICT_FP_EXTEND!");
10000 Ops[1].getValueType().isFloatingPoint() &&
"Invalid FP cast!");
10002 "STRICT_FP_EXTEND result type should be vector iff the operand "
10003 "type is vector!");
10006 Ops[1].getValueType().getVectorElementCount()) &&
10007 "Vector element count mismatch!");
10009 "Invalid fpext node, dst <= src!");
10012 assert(VTList.
NumVTs == 2 && Ops.
size() == 3 &&
"Invalid STRICT_FP_ROUND!");
10014 "STRICT_FP_ROUND result type should be vector iff the operand "
10015 "type is vector!");
10018 Ops[1].getValueType().getVectorElementCount()) &&
10019 "Vector element count mismatch!");
10021 Ops[1].getValueType().isFloatingPoint() &&
10022 VTList.
VTs[0].
bitsLT(Ops[1].getValueType()) &&
10023 isa<ConstantSDNode>(Ops[2]) &&
10024 (Ops[2]->getAsZExtVal() == 0 || Ops[2]->getAsZExtVal() == 1) &&
10025 "Invalid STRICT_FP_ROUND!");
10035 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
10036 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
10037 else if (N3.getOpcode() ==
ISD::AND)
10038 if (
ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
10042 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
10043 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
10051 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
10054 void *IP =
nullptr;
10055 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
10058 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
10059 createOperands(
N, Ops);
10060 CSEMap.InsertNode(
N, IP);
10062 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
10063 createOperands(
N, Ops);
10066 N->setFlags(Flags);
10075 return getNode(Opcode,
DL, VTList, std::nullopt);
10081 return getNode(Opcode,
DL, VTList, Ops);
10087 return getNode(Opcode,
DL, VTList, Ops);
10092 SDValue Ops[] = { N1, N2, N3 };
10093 return getNode(Opcode,
DL, VTList, Ops);
10098 SDValue Ops[] = { N1, N2, N3, N4 };
10099 return getNode(Opcode,
DL, VTList, Ops);
10105 SDValue Ops[] = { N1, N2, N3, N4, N5 };
10106 return getNode(Opcode,
DL, VTList, Ops);
10110 return makeVTList(SDNode::getValueTypeList(VT), 1);
10119 void *IP =
nullptr;
10125 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 2);
10126 VTListMap.InsertNode(Result, IP);
10128 return Result->getSDVTList();
10138 void *IP =
nullptr;
10145 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 3);
10146 VTListMap.InsertNode(Result, IP);
10148 return Result->getSDVTList();
10159 void *IP =
nullptr;
10167 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 4);
10168 VTListMap.InsertNode(Result, IP);
10170 return Result->getSDVTList();
10174 unsigned NumVTs = VTs.
size();
10176 ID.AddInteger(NumVTs);
10177 for (
unsigned index = 0; index < NumVTs; index++) {
10178 ID.AddInteger(VTs[index].getRawBits());
10181 void *IP =
nullptr;
10186 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, NumVTs);
10187 VTListMap.InsertNode(Result, IP);
10189 return Result->getSDVTList();
10200 assert(
N->getNumOperands() == 1 &&
"Update with wrong number of operands");
10203 if (
Op ==
N->getOperand(0))
return N;
10206 void *InsertPos =
nullptr;
10207 if (
SDNode *Existing = FindModifiedNodeSlot(
N,
Op, InsertPos))
10212 if (!RemoveNodeFromCSEMaps(
N))
10213 InsertPos =
nullptr;
10216 N->OperandList[0].set(
Op);
10220 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10225 assert(
N->getNumOperands() == 2 &&
"Update with wrong number of operands");
10228 if (Op1 ==
N->getOperand(0) && Op2 ==
N->getOperand(1))
10232 void *InsertPos =
nullptr;
10233 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Op1, Op2, InsertPos))
10238 if (!RemoveNodeFromCSEMaps(
N))
10239 InsertPos =
nullptr;
10242 if (
N->OperandList[0] != Op1)
10243 N->OperandList[0].set(Op1);
10244 if (
N->OperandList[1] != Op2)
10245 N->OperandList[1].set(Op2);
10249 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10255 SDValue Ops[] = { Op1, Op2, Op3 };
10262 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
10269 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
10275 unsigned NumOps = Ops.
size();
10276 assert(
N->getNumOperands() == NumOps &&
10277 "Update with wrong number of operands");
10280 if (std::equal(Ops.
begin(), Ops.
end(),
N->op_begin()))
10284 void *InsertPos =
nullptr;
10285 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Ops, InsertPos))
10290 if (!RemoveNodeFromCSEMaps(
N))
10291 InsertPos =
nullptr;
10294 for (
unsigned i = 0; i != NumOps; ++i)
10295 if (
N->OperandList[i] != Ops[i])
10296 N->OperandList[i].set(Ops[i]);
10300 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10317 if (NewMemRefs.
empty()) {
10323 if (NewMemRefs.
size() == 1) {
10324 N->MemRefs = NewMemRefs[0];
10330 Allocator.template Allocate<MachineMemOperand *>(NewMemRefs.
size());
10332 N->MemRefs = MemRefsBuffer;
10333 N->NumMemRefs =
static_cast<int>(NewMemRefs.
size());
10356 SDValue Ops[] = { Op1, Op2 };
10364 SDValue Ops[] = { Op1, Op2, Op3 };
10397 SDValue Ops[] = { Op1, Op2 };
10405 New->setNodeId(-1);
10425 unsigned Order = std::min(
N->getIROrder(), OLoc.
getIROrder());
10426 N->setIROrder(Order);
10449 void *IP =
nullptr;
10450 if (VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue) {
10454 return UpdateSDLocOnMergeSDNode(ON,
SDLoc(
N));
10457 if (!RemoveNodeFromCSEMaps(
N))
10462 N->ValueList = VTs.
VTs;
10472 if (Used->use_empty())
10473 DeadNodeSet.
insert(Used);
10478 MN->clearMemRefs();
10482 createOperands(
N, Ops);
10486 if (!DeadNodeSet.
empty()) {
10488 for (
SDNode *
N : DeadNodeSet)
10489 if (
N->use_empty())
10495 CSEMap.InsertNode(
N, IP);
10500 unsigned OrigOpc = Node->getOpcode();
10505#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10506 case ISD::STRICT_##DAGN: NewOpc = ISD::DAGN; break;
10507#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10508 case ISD::STRICT_##DAGN: NewOpc = ISD::SETCC; break;
10509#include "llvm/IR/ConstrainedOps.def"
10512 assert(Node->getNumValues() == 2 &&
"Unexpected number of results!");
10515 SDValue InputChain = Node->getOperand(0);
10520 for (
unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
10563 SDValue Ops[] = { Op1, Op2 };
10571 SDValue Ops[] = { Op1, Op2, Op3 };
10585 SDValue Ops[] = { Op1, Op2 };
10593 SDValue Ops[] = { Op1, Op2, Op3 };
10608 SDValue Ops[] = { Op1, Op2 };
10617 SDValue Ops[] = { Op1, Op2, Op3 };
10638 bool DoCSE = VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue;
10640 void *IP =
nullptr;
10646 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
10647 return cast<MachineSDNode>(UpdateSDLocOnMergeSDNode(E,
DL));
10652 N = newSDNode<MachineSDNode>(~Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
10653 createOperands(
N, Ops);
10656 CSEMap.InsertNode(
N, IP);
10669 VT, Operand, SRIdxVal);
10679 VT, Operand, Subreg, SRIdxVal);
10696 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10699 void *IP =
nullptr;
10701 E->intersectFlagsWith(Flags);
10711 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10714 void *IP =
nullptr;
10715 if (FindNodeOrInsertPos(
ID,
SDLoc(), IP))
10725 SDNode *
N,
unsigned R,
bool IsIndirect,
10727 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10728 "Expected inlined-at fields to agree");
10731 {}, IsIndirect,
DL, O,
10740 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10741 "Expected inlined-at fields to agree");
10754 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10755 "Expected inlined-at fields to agree");
10766 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10767 "Expected inlined-at fields to agree");
10770 Dependencies, IsIndirect,
DL, O,
10776 unsigned VReg,
bool IsIndirect,
10778 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10779 "Expected inlined-at fields to agree");
10782 {}, IsIndirect,
DL, O,
10790 unsigned O,
bool IsVariadic) {
10791 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10792 "Expected inlined-at fields to agree");
10795 DL, O, IsVariadic);
10799 unsigned OffsetInBits,
unsigned SizeInBits,
10800 bool InvalidateDbg) {
10803 assert(FromNode && ToNode &&
"Can't modify dbg values");
10808 if (
From == To || FromNode == ToNode)
10820 if (Dbg->isInvalidated())
10827 bool Changed =
false;
10828 auto NewLocOps = Dbg->copyLocationOps();
10830 NewLocOps.begin(), NewLocOps.end(),
10832 bool Match = Op == FromLocOp;
10842 auto *Expr = Dbg->getExpression();
10848 if (
auto FI = Expr->getFragmentInfo())
10849 if (OffsetInBits + SizeInBits > FI->SizeInBits)
10858 auto AdditionalDependencies = Dbg->getAdditionalDependencies();
10861 Var, Expr, NewLocOps, AdditionalDependencies, Dbg->isIndirect(),
10862 Dbg->getDebugLoc(), std::max(ToNode->
getIROrder(), Dbg->getOrder()),
10863 Dbg->isVariadic());
10866 if (InvalidateDbg) {
10868 Dbg->setIsInvalidated();
10869 Dbg->setIsEmitted();
10875 "Transferred DbgValues should depend on the new SDNode");
10881 if (!
N.getHasDebugValue())
10886 if (DV->isInvalidated())
10888 switch (
N.getOpcode()) {
10894 if (!isa<ConstantSDNode>(N0)) {
10895 bool RHSConstant = isa<ConstantSDNode>(N1);
10898 Offset =
N.getConstantOperandVal(1);
10901 if (!RHSConstant && DV->isIndirect())
10908 auto *DIExpr = DV->getExpression();
10909 auto NewLocOps = DV->copyLocationOps();
10910 bool Changed =
false;
10911 size_t OrigLocOpsSize = NewLocOps.size();
10912 for (
size_t i = 0; i < OrigLocOpsSize; ++i) {
10917 NewLocOps[i].getSDNode() != &
N)
10928 const auto *TmpDIExpr =
10936 NewLocOps.push_back(
RHS);
10942 assert(Changed &&
"Salvage target doesn't use N");
10945 DV->isVariadic() || OrigLocOpsSize != NewLocOps.size();
10947 auto AdditionalDependencies = DV->getAdditionalDependencies();
10949 DV->getVariable(), DIExpr, NewLocOps, AdditionalDependencies,
10950 DV->isIndirect(), DV->getDebugLoc(), DV->getOrder(), IsVariadic);
10952 DV->setIsInvalidated();
10953 DV->setIsEmitted();
10955 N0.
getNode()->dumprFull(
this);
10956 dbgs() <<
" into " << *DIExpr <<
'\n');
10963 TypeSize ToSize =
N.getValueSizeInBits(0);
10967 auto NewLocOps = DV->copyLocationOps();
10968 bool Changed =
false;
10969 for (
size_t i = 0; i < NewLocOps.size(); ++i) {
10971 NewLocOps[i].getSDNode() != &
N)
10978 assert(Changed &&
"Salvage target doesn't use N");
10983 DV->getAdditionalDependencies(), DV->isIndirect(),
10984 DV->getDebugLoc(), DV->getOrder(), DV->isVariadic());
10987 DV->setIsInvalidated();
10988 DV->setIsEmitted();
10990 dbgs() <<
" into " << *DbgExpression <<
'\n');
10997 assert(!Dbg->getSDNodes().empty() &&
10998 "Salvaged DbgValue should depend on a new SDNode");
11006 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) &&
11007 "Expected inlined-at fields to agree");
11023 while (UI != UE &&
N == *UI)
11031 :
SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
11044 "Cannot replace with this method!");
11060 RAUWUpdateListener Listener(*
this, UI, UE);
11065 RemoveNodeFromCSEMaps(
User);
11077 }
while (UI != UE && *UI ==
User);
11080 AddModifiedNodeToCSEMaps(
User);
11096 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
11099 "Cannot use this version of ReplaceAllUsesWith!");
11107 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
11108 if (
From->hasAnyUseOfValue(i)) {
11109 assert((i < To->getNumValues()) &&
"Invalid To location");
11118 RAUWUpdateListener Listener(*
this, UI, UE);
11123 RemoveNodeFromCSEMaps(
User);
11135 }
while (UI != UE && *UI ==
User);
11139 AddModifiedNodeToCSEMaps(
User);
11153 if (
From->getNumValues() == 1)
11156 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i) {
11166 RAUWUpdateListener Listener(*
this, UI, UE);
11171 RemoveNodeFromCSEMaps(
User);
11177 bool To_IsDivergent =
false;
11184 }
while (UI != UE && *UI ==
User);
11186 if (To_IsDivergent !=
From->isDivergent())
11191 AddModifiedNodeToCSEMaps(
User);
11204 if (
From == To)
return;
11207 if (
From.getNode()->getNumValues() == 1) {
11219 UE =
From.getNode()->use_end();
11220 RAUWUpdateListener Listener(*
this, UI, UE);
11223 bool UserRemovedFromCSEMaps =
false;
11233 if (
Use.getResNo() !=
From.getResNo()) {
11240 if (!UserRemovedFromCSEMaps) {
11241 RemoveNodeFromCSEMaps(
User);
11242 UserRemovedFromCSEMaps =
true;
11249 }
while (UI != UE && *UI ==
User);
11252 if (!UserRemovedFromCSEMaps)
11257 AddModifiedNodeToCSEMaps(
User);
11276bool operator<(
const UseMemo &L,
const UseMemo &R) {
11277 return (intptr_t)L.User < (intptr_t)R.User;
11287 for (UseMemo &Memo :
Uses)
11288 if (Memo.User ==
N)
11289 Memo.User =
nullptr;
11302 "Conflicting divergence information!");
11307 for (
const auto &
Op :
N->ops()) {
11308 if (
Op.Val.getValueType() != MVT::Other &&
Op.getNode()->isDivergent())
11319 if (
N->SDNodeBits.IsDivergent != IsDivergent) {
11320 N->SDNodeBits.IsDivergent = IsDivergent;
11323 }
while (!Worklist.
empty());
11326void SelectionDAG::CreateTopologicalOrder(std::vector<SDNode *> &Order) {
11328 Order.
reserve(AllNodes.size());
11330 unsigned NOps =
N.getNumOperands();
11333 Order.push_back(&
N);
11335 for (
size_t I = 0;
I != Order.size(); ++
I) {
11337 for (
auto *U :
N->uses()) {
11338 unsigned &UnsortedOps = Degree[U];
11339 if (0 == --UnsortedOps)
11340 Order.push_back(U);
11347 std::vector<SDNode *> TopoOrder;
11348 CreateTopologicalOrder(TopoOrder);
11349 for (
auto *
N : TopoOrder) {
11351 "Divergence bit inconsistency detected");
11374 for (
unsigned i = 0; i != Num; ++i) {
11375 unsigned FromResNo =
From[i].getResNo();
11378 E = FromNode->
use_end(); UI != E; ++UI) {
11380 if (
Use.getResNo() == FromResNo) {
11381 UseMemo Memo = { *UI, i, &
Use };
11382 Uses.push_back(Memo);
11389 RAUOVWUpdateListener Listener(*
this,
Uses);
11391 for (
unsigned UseIndex = 0, UseIndexEnd =
Uses.size();
11392 UseIndex != UseIndexEnd; ) {
11398 if (
User ==
nullptr) {
11404 RemoveNodeFromCSEMaps(
User);
11411 unsigned i =
Uses[UseIndex].Index;
11416 }
while (UseIndex != UseIndexEnd &&
Uses[UseIndex].
User ==
User);
11420 AddModifiedNodeToCSEMaps(
User);
11428 unsigned DAGSize = 0;
11444 unsigned Degree =
N.getNumOperands();
11447 N.setNodeId(DAGSize++);
11449 if (Q != SortedPos)
11450 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
11451 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11455 N.setNodeId(Degree);
11467 unsigned Degree =
P->getNodeId();
11468 assert(Degree != 0 &&
"Invalid node degree");
11472 P->setNodeId(DAGSize++);
11473 if (
P->getIterator() != SortedPos)
11474 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(
P));
11475 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11479 P->setNodeId(Degree);
11482 if (Node.getIterator() == SortedPos) {
11486 dbgs() <<
"Overran sorted position:\n";
11488 dbgs() <<
"Checking if this is due to cycles\n";
11495 assert(SortedPos == AllNodes.end() &&
11496 "Topological sort incomplete!");
11498 "First node in topological sort is not the entry token!");
11499 assert(AllNodes.front().getNodeId() == 0 &&
11500 "First node in topological sort has non-zero id!");
11501 assert(AllNodes.front().getNumOperands() == 0 &&
11502 "First node in topological sort has operands!");
11503 assert(AllNodes.back().getNodeId() == (
int)DAGSize-1 &&
11504 "Last node in topologic sort has unexpected id!");
11505 assert(AllNodes.back().use_empty() &&
11506 "Last node in topologic sort has users!");
11514 for (
SDNode *SD : DB->getSDNodes()) {
11518 SD->setHasDebugValue(
true);
11520 DbgInfo->
add(DB, isParameter);
11527 assert(isa<MemSDNode>(NewMemOpChain) &&
"Expected a memop node");
11533 if (OldChain == NewMemOpChain || OldChain.
use_empty())
11534 return NewMemOpChain;
11537 OldChain, NewMemOpChain);
11540 return TokenFactor;
11545 assert(isa<MemSDNode>(NewMemOp.
getNode()) &&
"Expected a memop node");
11553 assert(isa<ExternalSymbolSDNode>(
Op) &&
"Node should be an ExternalSymbol");
11555 auto *Symbol = cast<ExternalSymbolSDNode>(
Op)->getSymbol();
11559 if (OutFunction !=
nullptr)
11567 std::string ErrorStr;
11569 ErrorFormatter <<
"Undefined external symbol ";
11570 ErrorFormatter <<
'"' << Symbol <<
'"';
11580 return Const !=
nullptr && Const->isZero();
11585 return Const !=
nullptr && Const->isZero() && !Const->isNegative();
11590 return Const !=
nullptr && Const->isAllOnes();
11595 return Const !=
nullptr && Const->isOne();
11600 return Const !=
nullptr && Const->isMinSignedValue();
11604 unsigned OperandNo) {
11609 APInt Const = ConstV->getAPIntValue().trunc(V.getScalarValueSizeInBits());
11615 return Const.isZero();
11617 return Const.isOne();
11620 return Const.isAllOnes();
11622 return Const.isMinSignedValue();
11624 return Const.isMaxSignedValue();
11629 return OperandNo == 1 && Const.isZero();
11632 return OperandNo == 1 && Const.isOne();
11637 return ConstFP->isZero() &&
11638 (Flags.hasNoSignedZeros() || ConstFP->isNegative());
11640 return OperandNo == 1 && ConstFP->isZero() &&
11641 (Flags.hasNoSignedZeros() || !ConstFP->isNegative());
11643 return ConstFP->isExactlyValue(1.0);
11645 return OperandNo == 1 && ConstFP->isExactlyValue(1.0);
11649 EVT VT = V.getValueType();
11651 APFloat NeutralAF = !Flags.hasNoNaNs()
11653 : !Flags.hasNoInfs()
11659 return ConstFP->isExactlyValue(NeutralAF);
11668 V = V.getOperand(0);
11673 while (V.getOpcode() ==
ISD::BITCAST && V.getOperand(0).hasOneUse())
11674 V = V.getOperand(0);
11680 V = V.getOperand(0);
11686 V = V.getOperand(0);
11694 unsigned NumBits = V.getScalarValueSizeInBits();
11697 return C && (
C->getAPIntValue().countr_one() >= NumBits);
11701 bool AllowTruncation) {
11702 EVT VT =
N.getValueType();
11711 bool AllowTruncation) {
11718 EVT VecEltVT =
N->getValueType(0).getVectorElementType();
11719 if (
auto *CN = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
11720 EVT CVT = CN->getValueType(0);
11721 assert(CVT.
bitsGE(VecEltVT) &&
"Illegal splat_vector element extension");
11722 if (AllowTruncation || CVT == VecEltVT)
11729 ConstantSDNode *CN = BV->getConstantSplatNode(DemandedElts, &UndefElements);
11734 if (CN && (UndefElements.
none() || AllowUndefs)) {
11736 EVT NSVT =
N.getValueType().getScalarType();
11737 assert(CVT.
bitsGE(NSVT) &&
"Illegal build vector element extension");
11738 if (AllowTruncation || (CVT == NSVT))
11747 EVT VT =
N.getValueType();
11755 const APInt &DemandedElts,
11756 bool AllowUndefs) {
11763 BV->getConstantFPSplatNode(DemandedElts, &UndefElements);
11765 if (CN && (UndefElements.
none() || AllowUndefs))
11780 return C &&
C->isZero();
11786 return C &&
C->isOne();
11791 unsigned BitWidth =
N.getScalarValueSizeInBits();
11793 return C &&
C->isAllOnes() &&
C->getValueSizeInBits(0) ==
BitWidth;
11802 :
SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) {
11826 std::vector<EVT> VTs;
11839const EVT *SDNode::getValueTypeList(
EVT VT) {
11840 static std::set<EVT, EVT::compareRawBits> EVTs;
11841 static EVTArray SimpleVTArray;
11846 return &(*EVTs.insert(VT).first);
11860 if (UI.getUse().getResNo() ==
Value) {
11877 if (UI.getUse().getResNo() ==
Value)
11915 return any_of(
N->op_values(),
11916 [
this](
SDValue Op) { return this == Op.getNode(); });
11930 unsigned Depth)
const {
11931 if (*
this == Dest)
return true;
11935 if (
Depth == 0)
return false;
11955 return Op.reachesChainWithoutSideEffects(Dest, Depth - 1);
11960 if (
LoadSDNode *Ld = dyn_cast<LoadSDNode>(*
this)) {
11961 if (Ld->isUnordered())
11962 return Ld->getChain().reachesChainWithoutSideEffects(Dest,
Depth-1);
11981 bool AllowPartials) {
11990 return Op.getOpcode() ==
unsigned(BinOp);
11996 unsigned CandidateBinOp =
Op.getOpcode();
11997 if (
Op.getValueType().isFloatingPoint()) {
11999 switch (CandidateBinOp) {
12001 if (!Flags.hasNoSignedZeros() || !Flags.hasAllowReassociation())
12011 auto PartialReduction = [&](
SDValue Op,
unsigned NumSubElts) {
12012 if (!AllowPartials || !
Op)
12014 EVT OpVT =
Op.getValueType();
12037 unsigned Stages =
Log2_32(
Op.getValueType().getVectorNumElements());
12039 for (
unsigned i = 0; i < Stages; ++i) {
12040 unsigned MaskEnd = (1 << i);
12042 if (
Op.getOpcode() != CandidateBinOp)
12043 return PartialReduction(PrevOp, MaskEnd);
12052 Shuffle = dyn_cast<ShuffleVectorSDNode>(Op1);
12059 return PartialReduction(PrevOp, MaskEnd);
12064 return PartialReduction(PrevOp, MaskEnd);
12071 while (
Op.getOpcode() == CandidateBinOp) {
12072 unsigned NumElts =
Op.getValueType().getVectorNumElements();
12080 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
12081 if (NumSrcElts != (2 * NumElts))
12096 EVT VT =
N->getValueType(0);
12105 else if (NE > ResNE)
12108 if (
N->getNumValues() == 2) {
12111 EVT VT1 =
N->getValueType(1);
12115 for (i = 0; i != NE; ++i) {
12116 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12117 SDValue Operand =
N->getOperand(j);
12136 assert(
N->getNumValues() == 1 &&
12137 "Can't unroll a vector with multiple results!");
12143 for (i= 0; i != NE; ++i) {
12144 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12145 SDValue Operand =
N->getOperand(j);
12158 switch (
N->getOpcode()) {
12185 for (; i < ResNE; ++i)
12194 unsigned Opcode =
N->getOpcode();
12198 "Expected an overflow opcode");
12200 EVT ResVT =
N->getValueType(0);
12201 EVT OvVT =
N->getValueType(1);
12210 else if (NE > ResNE)
12222 for (
unsigned i = 0; i < NE; ++i) {
12223 SDValue Res =
getNode(Opcode, dl, VTs, LHSScalars[i], RHSScalars[i]);
12246 if (LD->isVolatile() ||
Base->isVolatile())
12249 if (!LD->isSimple())
12251 if (LD->isIndexed() ||
Base->isIndexed())
12253 if (LD->getChain() !=
Base->getChain())
12255 EVT VT = LD->getMemoryVT();
12263 if (BaseLocDecomp.equalBaseIndex(LocDecomp, *
this,
Offset))
12264 return (Dist * (int64_t)Bytes ==
Offset);
12273 int64_t GVOffset = 0;
12285 int FrameIdx = INT_MIN;
12286 int64_t FrameOffset = 0;
12288 FrameIdx = FI->getIndex();
12290 isa<FrameIndexSDNode>(
Ptr.getOperand(0))) {
12292 FrameIdx = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
12293 FrameOffset =
Ptr.getConstantOperandVal(1);
12296 if (FrameIdx != INT_MIN) {
12301 return std::nullopt;
12311 "Split node must be a scalar type");
12316 return std::make_pair(
Lo,
Hi);
12329 return std::make_pair(LoVT, HiVT);
12337 bool *HiIsEmpty)
const {
12347 "Mixing fixed width and scalable vectors when enveloping a type");
12352 *HiIsEmpty =
false;
12360 return std::make_pair(LoVT, HiVT);
12365std::pair<SDValue, SDValue>
12370 "Splitting vector with an invalid mixture of fixed and scalable "
12373 N.getValueType().getVectorMinNumElements() &&
12374 "More vector elements requested than available!");
12384 return std::make_pair(
Lo,
Hi);
12391 EVT VT =
N.getValueType();
12393 "Expecting the mask to be an evenly-sized vector");
12401 return std::make_pair(
Lo,
Hi);
12406 EVT VT =
N.getValueType();
12415 unsigned Start,
unsigned Count,
12417 EVT VT =
Op.getValueType();
12420 if (EltVT ==
EVT())
12423 for (
unsigned i = Start, e = Start + Count; i != e; ++i) {
12436 return Val.MachineCPVal->getType();
12437 return Val.ConstVal->getType();
12441 unsigned &SplatBitSize,
12442 bool &HasAnyUndefs,
12443 unsigned MinSplatBits,
12444 bool IsBigEndian)
const {
12448 if (MinSplatBits > VecWidth)
12453 SplatValue =
APInt(VecWidth, 0);
12454 SplatUndef =
APInt(VecWidth, 0);
12461 assert(NumOps > 0 &&
"isConstantSplat has 0-size build vector");
12464 for (
unsigned j = 0; j < NumOps; ++j) {
12465 unsigned i = IsBigEndian ? NumOps - 1 - j : j;
12467 unsigned BitPos = j * EltWidth;
12470 SplatUndef.
setBits(BitPos, BitPos + EltWidth);
12471 else if (
auto *CN = dyn_cast<ConstantSDNode>(OpVal))
12472 SplatValue.
insertBits(CN->getAPIntValue().zextOrTrunc(EltWidth), BitPos);
12473 else if (
auto *CN = dyn_cast<ConstantFPSDNode>(OpVal))
12474 SplatValue.
insertBits(CN->getValueAPF().bitcastToAPInt(), BitPos);
12481 HasAnyUndefs = (SplatUndef != 0);
12484 while (VecWidth > 8) {
12489 unsigned HalfSize = VecWidth / 2;
12496 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
12497 MinSplatBits > HalfSize)
12500 SplatValue = HighValue | LowValue;
12501 SplatUndef = HighUndef & LowUndef;
12503 VecWidth = HalfSize;
12512 SplatBitSize = VecWidth;
12519 if (UndefElements) {
12520 UndefElements->
clear();
12521 UndefElements->
resize(NumOps);
12527 for (
unsigned i = 0; i != NumOps; ++i) {
12528 if (!DemandedElts[i])
12531 if (
Op.isUndef()) {
12533 (*UndefElements)[i] =
true;
12534 }
else if (!Splatted) {
12536 }
else if (Splatted !=
Op) {
12542 unsigned FirstDemandedIdx = DemandedElts.
countr_zero();
12544 "Can only have a splat without a constant for all undefs.");
12561 if (UndefElements) {
12562 UndefElements->
clear();
12563 UndefElements->
resize(NumOps);
12571 for (
unsigned I = 0;
I != NumOps; ++
I)
12573 (*UndefElements)[
I] =
true;
12576 for (
unsigned SeqLen = 1; SeqLen < NumOps; SeqLen *= 2) {
12577 Sequence.append(SeqLen,
SDValue());
12578 for (
unsigned I = 0;
I != NumOps; ++
I) {
12579 if (!DemandedElts[
I])
12581 SDValue &SeqOp = Sequence[
I % SeqLen];
12583 if (
Op.isUndef()) {
12588 if (SeqOp && !SeqOp.
isUndef() && SeqOp !=
Op) {
12594 if (!Sequence.empty())
12598 assert(Sequence.empty() &&
"Failed to empty non-repeating sequence pattern");
12611 return dyn_cast_or_null<ConstantSDNode>(
12617 return dyn_cast_or_null<ConstantSDNode>(
getSplatValue(UndefElements));
12623 return dyn_cast_or_null<ConstantFPSDNode>(
12629 return dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements));
12636 dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements))) {
12639 const APFloat &APF = CN->getValueAPF();
12645 return IntVal.exactLogBase2();
12651 bool IsLittleEndian,
unsigned DstEltSizeInBits,
12659 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12660 "Invalid bitcast scale");
12665 BitVector SrcUndeElements(NumSrcOps,
false);
12667 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12669 if (
Op.isUndef()) {
12670 SrcUndeElements.
set(
I);
12673 auto *CInt = dyn_cast<ConstantSDNode>(
Op);
12674 auto *CFP = dyn_cast<ConstantFPSDNode>(
Op);
12675 assert((CInt || CFP) &&
"Unknown constant");
12676 SrcBitElements[
I] = CInt ? CInt->getAPIntValue().trunc(SrcEltSizeInBits)
12677 : CFP->getValueAPF().bitcastToAPInt();
12681 recastRawBits(IsLittleEndian, DstEltSizeInBits, RawBitElements,
12682 SrcBitElements, UndefElements, SrcUndeElements);
12687 unsigned DstEltSizeInBits,
12692 unsigned NumSrcOps = SrcBitElements.
size();
12693 unsigned SrcEltSizeInBits = SrcBitElements[0].getBitWidth();
12694 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12695 "Invalid bitcast scale");
12696 assert(NumSrcOps == SrcUndefElements.
size() &&
12697 "Vector size mismatch");
12699 unsigned NumDstOps = (NumSrcOps * SrcEltSizeInBits) / DstEltSizeInBits;
12700 DstUndefElements.
clear();
12701 DstUndefElements.
resize(NumDstOps,
false);
12705 if (SrcEltSizeInBits <= DstEltSizeInBits) {
12706 unsigned Scale = DstEltSizeInBits / SrcEltSizeInBits;
12707 for (
unsigned I = 0;
I != NumDstOps; ++
I) {
12708 DstUndefElements.
set(
I);
12709 APInt &DstBits = DstBitElements[
I];
12710 for (
unsigned J = 0; J != Scale; ++J) {
12711 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12712 if (SrcUndefElements[
Idx])
12714 DstUndefElements.
reset(
I);
12715 const APInt &SrcBits = SrcBitElements[
Idx];
12717 "Illegal constant bitwidths");
12718 DstBits.
insertBits(SrcBits, J * SrcEltSizeInBits);
12725 unsigned Scale = SrcEltSizeInBits / DstEltSizeInBits;
12726 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12727 if (SrcUndefElements[
I]) {
12728 DstUndefElements.
set(
I * Scale, (
I + 1) * Scale);
12731 const APInt &SrcBits = SrcBitElements[
I];
12732 for (
unsigned J = 0; J != Scale; ++J) {
12733 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12734 APInt &DstBits = DstBitElements[
Idx];
12735 DstBits = SrcBits.
extractBits(DstEltSizeInBits, J * DstEltSizeInBits);
12742 unsigned Opc =
Op.getOpcode();
12749std::optional<std::pair<APInt, APInt>>
12753 return std::nullopt;
12757 return std::nullopt;
12764 return std::nullopt;
12766 for (
unsigned i = 2; i < NumOps; ++i) {
12768 return std::nullopt;
12771 if (Val != (Start + (Stride * i)))
12772 return std::nullopt;
12775 return std::make_pair(Start, Stride);
12791 for (
int Idx = Mask[i]; i != e; ++i)
12792 if (Mask[i] >= 0 && Mask[i] !=
Idx)
12800 if (isa<ConstantSDNode>(
N))
12801 return N.getNode();
12803 return N.getNode();
12811 isa<ConstantSDNode>(
N.getOperand(0)))
12812 return N.getNode();
12819 if (isa<ConstantFPSDNode>(
N))
12820 return N.getNode();
12823 return N.getNode();
12826 isa<ConstantFPSDNode>(
N.getOperand(0)))
12827 return N.getNode();
12833 assert(!Node->OperandList &&
"Node already has operands");
12835 "too many operands to fit into SDNode");
12836 SDUse *Ops = OperandRecycler.allocate(
12839 bool IsDivergent =
false;
12840 for (
unsigned I = 0;
I != Vals.
size(); ++
I) {
12841 Ops[
I].setUser(Node);
12842 Ops[
I].setInitial(Vals[
I]);
12843 if (Ops[
I].Val.getValueType() != MVT::Other)
12847 Node->OperandList = Ops;
12850 Node->SDNodeBits.IsDivergent = IsDivergent;
12858 while (Vals.
size() > Limit) {
12859 unsigned SliceIdx = Vals.
size() - Limit;
12933 const SDLoc &DLoc) {
12938 Entry.Ty =
Ptr.getValueType().getTypeForEVT(*
getContext());
12939 Args.push_back(Entry);
12951 assert(
From && To &&
"Invalid SDNode; empty source SDValue?");
12952 auto I = SDEI.find(
From);
12953 if (
I == SDEI.end())
12958 NodeExtraInfo NEI =
I->second;
12967 SDEI[To] = std::move(NEI);
12986 Leafs.emplace_back(
N);
12989 if (!FromReach.
insert(
N).second)
12997 auto DeepCopyTo = [&](
auto &&Self,
const SDNode *
N) {
13000 if (!Visited.
insert(
N).second)
13005 if (!Self(Self,
Op.getNode()))
13025 for (
const SDNode *
N : StartFrom)
13026 VisitFrom(VisitFrom,
N,
MaxDepth - PrevDepth);
13038 errs() <<
"warning: incomplete propagation of SelectionDAG::NodeExtraInfo\n";
13039 assert(
false &&
"From subgraph too complex - increase max. MaxDepth?");
13041 SDEI[To] = std::move(NEI);
13055 if (!Visited.
insert(
N).second) {
13056 errs() <<
"Detected cycle in SelectionDAG\n";
13057 dbgs() <<
"Offending node:\n";
13058 N->dumprFull(DAG);
dbgs() <<
"\n";
13074 bool check = force;
13075#ifdef EXPENSIVE_CHECKS
13079 assert(
N &&
"Checking nonexistent SDNode");
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static bool isConstant(const MachineInstr &MI)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
This file implements the BitVector class.
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
static std::optional< bool > isBigEndian(const SmallDenseMap< int64_t, int64_t, 8 > &MemOffset2Idx, int64_t LowestIdx)
Given a map from byte offsets in memory to indices in a load/store, determine if that map corresponds...
#define __asan_unpoison_memory_region(p, size)
#define LLVM_LIKELY(EXPR)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Looks at all the uses of the given value Returns the Liveness deduced from the uses of this value Adds all uses that cause the result to be MaybeLive to MaybeLiveRetUses If the result is MaybeLiveUses might be modified but its content should be ignored(since it might not be complete). DeadArgumentEliminationPass
Given that RA is a live propagate it s liveness to any other values it uses(according to Uses). void DeadArgumentEliminationPass
Given that RA is a live value
This file defines the DenseSet and SmallDenseSet classes.
This file contains constants used for implementing Dwarf debug support.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file defines a hash set that can be used to remove duplication of nodes in a graph.
Rewrite Partial Register Uses
static const unsigned MaxDepth
static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB)
static bool shouldLowerMemFuncForSize(const MachineFunction &MF)
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG)
mir Rename Register Operands
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
Contains matchers for matching SelectionDAG nodes and values.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static uint64_t umul_ov(uint64_t i, uint64_t j, bool &Overflow)
static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo)
Lower the call to 'memset' intrinsic function into a series of store operations.
static std::optional< APInt > FoldValueWithUndef(unsigned Opcode, const APInt &C1, bool IsUndef1, const APInt &C2, bool IsUndef2)
static SDValue FoldSTEP_VECTOR(const SDLoc &DL, EVT VT, SDValue Step, SelectionDAG &DAG)
static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned OpC, SDVTList VTList, ArrayRef< SDValue > OpList)
static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG, const TargetLowering &TLI, const ConstantDataArraySlice &Slice)
getMemsetStringVal - Similar to getMemsetValue.
static cl::opt< bool > EnableMemCpyDAGOpt("enable-memcpy-dag-opt", cl::Hidden, cl::init(true), cl::desc("Gang up loads and stores generated by inlining of memcpy"))
static bool haveNoCommonBitsSetCommutative(SDValue A, SDValue B)
static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList)
AddNodeIDValueTypes - Value type lists are intern'd so we can represent them solely with their pointe...
static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef< int > M)
Swaps the values of N1 and N2.
static bool isMemSrcFromConstant(SDValue Src, ConstantDataArraySlice &Slice)
Returns true if memcpy source is constant data.
static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo)
static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo, AAResults *AA)
static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC)
AddNodeIDOpcode - Add the node opcode to the NodeID data.
static ISD::CondCode getSetCCInverseImpl(ISD::CondCode Op, bool isIntegerLike)
static bool doNotCSE(SDNode *N)
doNotCSE - Return true if CSE should not be performed for this node.
static cl::opt< int > MaxLdStGlue("ldstmemcpy-glue-max", cl::desc("Number limit for gluing ld/st of memcpy."), cl::Hidden, cl::init(0))
static void AddNodeIDOperands(FoldingSetNodeID &ID, ArrayRef< SDValue > Ops)
AddNodeIDOperands - Various routines for adding operands to the NodeID data.
static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
Try to simplify vector concatenation to an input value, undef, or build vector.
static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info, SelectionDAG &DAG, SDValue Ptr, int64_t Offset=0)
InferPointerInfo - If the specified ptr/offset is a frame index, infer a MachinePointerInfo record fr...
static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N)
If this is an SDNode with special info, add this info to the NodeID data.
static void NewSDValueDbgMsg(SDValue V, StringRef Msg, SelectionDAG *G)
static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs)
makeVTList - Return an instance of the SDVTList struct initialized with the specified members.
static void VerifySDNode(SDNode *N, const TargetLowering *TLI)
VerifySDNode - Check the given SDNode. Aborts if it is invalid.
static void checkForCyclesHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallPtrSetImpl< const SDNode * > &Checked, const llvm::SelectionDAG *DAG)
static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SmallVector< SDValue, 32 > &OutChains, unsigned From, unsigned To, SmallVector< SDValue, 16 > &OutLoadChains, SmallVector< SDValue, 16 > &OutStoreChains)
static int isSignedOp(ISD::CondCode Opcode)
For an integer comparison, return 1 if the comparison is a signed operation and 2 if the result is an...
static std::optional< APInt > FoldValue(unsigned Opcode, const APInt &C1, const APInt &C2)
static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI, unsigned AS)
static Constant * ConstantFold(Instruction *I, const DataLayout &DL, const SmallDenseMap< Value *, Constant * > &ConstantPool)
Try to fold instruction I into a constant.
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file describes how to lower LLVM code to machine code.
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static OverflowResult mapOverflowResult(ConstantRange::OverflowResult OR)
Convert ConstantRange OverflowResult into ValueTracking OverflowResult.
static unsigned getSize(unsigned Kind)
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
static APFloat getQNaN(const fltSemantics &Sem, bool Negative=false, const APInt *payload=nullptr)
Factory for QNaN values.
opStatus divide(const APFloat &RHS, roundingMode RM)
void copySign(const APFloat &RHS)
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
opStatus subtract(const APFloat &RHS, roundingMode RM)
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
opStatus add(const APFloat &RHS, roundingMode RM)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
opStatus multiply(const APFloat &RHS, roundingMode RM)
opStatus fusedMultiplyAdd(const APFloat &Multiplicand, const APFloat &Addend, roundingMode RM)
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
opStatus convertToInteger(MutableArrayRef< integerPart > Input, unsigned int Width, bool IsSigned, roundingMode RM, bool *IsExact) const
static APFloat getInf(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Infinity.
opStatus mod(const APFloat &RHS)
static APFloat getNaN(const fltSemantics &Sem, bool Negative=false, uint64_t payload=0)
Factory for NaN values.
Class for arbitrary precision integers.
APInt umul_ov(const APInt &RHS, bool &Overflow) const
APInt usub_sat(const APInt &RHS) const
APInt udiv(const APInt &RHS) const
Unsigned division operation.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
APInt zext(unsigned width) const
Zero extend to a new width.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
uint64_t getZExtValue() const
Get zero extended value.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
unsigned popcount() const
Count the number of bits set.
void setBitsFrom(unsigned loBit)
Set the top bits starting from loBit.
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
APInt trunc(unsigned width) const
Truncate to new width.
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
APInt abs() const
Get the absolute value.
APInt sadd_sat(const APInt &RHS) const
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
bool ugt(const APInt &RHS) const
Unsigned greater than comparison.
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool ult(const APInt &RHS) const
Unsigned less than comparison.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
bool isNegative() const
Determine sign of this APInt.
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
void clearAllBits()
Set every bit to 0.
APInt rotr(unsigned rotateAmt) const
Rotate right by rotateAmt.
APInt reverseBits() const
void ashrInPlace(unsigned ShiftAmt)
Arithmetic right-shift this APInt by ShiftAmt in place.
bool sle(const APInt &RHS) const
Signed less or equal comparison.
unsigned countr_zero() const
Count the number of trailing zero bits.
unsigned getNumSignBits() const
Computes the number of leading bits of this APInt that are equal to its sign bit.
unsigned countl_zero() const
The APInt version of std::countl_zero.
static APInt getSplat(unsigned NewLen, const APInt &V)
Return a value containing V broadcasted over NewLen bits.
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
APInt sshl_sat(const APInt &RHS) const
APInt ushl_sat(const APInt &RHS) const
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
void insertBits(const APInt &SubBits, unsigned bitPosition)
Insert the bits from a smaller APInt starting at bitPosition.
void clearLowBits(unsigned loBits)
Set bottom loBits bits to 0.
unsigned logBase2() const
APInt uadd_sat(const APInt &RHS) const
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
void setAllBits()
Set every bit to 1.
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
bool ule(const APInt &RHS) const
Unsigned less or equal comparison.
APInt sext(unsigned width) const
Sign extend to a new width.
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
APInt shl(unsigned shiftAmt) const
Left-shift function.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
APInt extractBits(unsigned numBits, unsigned bitPosition) const
Return an APInt with the extracted bits [bitPosition,bitPosition+numBits).
bool sge(const APInt &RHS) const
Signed greater or equal comparison.
static APInt getBitsSetFrom(unsigned numBits, unsigned loBit)
Constructs an APInt value that has a contiguous range of bits set.
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
APInt ssub_sat(const APInt &RHS) const
An arbitrary precision integer that knows its signedness.
Recycle small arrays allocated from a BumpPtrAllocator.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
This is an SDNode representing atomic operations.
static BaseIndexOffset match(const SDNode *N, const SelectionDAG &DAG)
Parses tree in N for base, index, offset addresses.
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
bool none() const
none - Returns true if none of the bits are set.
size_type size() const
size - Returns the number of bits in this bitvector.
int64_t getOffset() const
unsigned getTargetFlags() const
const BlockAddress * getBlockAddress() const
The address of a basic block.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool getConstantRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &RawBitElements, BitVector &UndefElements) const
Extract the raw bit data from a build vector of Undef, Constant or ConstantFP node elements.
static void recastRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &DstBitElements, ArrayRef< APInt > SrcBitElements, BitVector &DstUndefElements, const BitVector &SrcUndefElements)
Recast bit data SrcBitElements to DstEltSizeInBits wide elements.
bool getRepeatedSequence(const APInt &DemandedElts, SmallVectorImpl< SDValue > &Sequence, BitVector *UndefElements=nullptr) const
Find the shortest repeating sequence of values in the build vector.
ConstantFPSDNode * getConstantFPSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant FP or null if this is not a constant FP splat.
std::optional< std::pair< APInt, APInt > > isConstantSequence() const
If this BuildVector is constant and represents the numerical series "<a, a+n, a+2n,...
SDValue getSplatValue(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted value or a null value if this is not a splat.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
ConstantSDNode * getConstantSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant or null if this is not a constant splat.
int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements, uint32_t BitWidth) const
If this is a constant FP splat and the splatted constant FP is an exact power or 2,...
LLVM_ATTRIBUTE_RETURNS_NONNULL void * Allocate(size_t Size, Align Alignment)
Allocate space at the specified alignment.
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it,...
static bool isValueValidForType(EVT VT, const APFloat &Val)
const APFloat & getValueAPF() const
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
const APInt & getValue() const
Return the constant as an APInt value reference.
bool isMachineConstantPoolEntry() const
This class represents a range of values.
ConstantRange multiply(const ConstantRange &Other) const
Return a new range representing the possible values resulting from a multiplication of a value in thi...
const APInt * getSingleElement() const
If this set contains a single element, return it, otherwise return null.
static ConstantRange fromKnownBits(const KnownBits &Known, bool IsSigned)
Initialize a range based on a known bits constraint.
OverflowResult unsignedSubMayOverflow(const ConstantRange &Other) const
Return whether unsigned sub of the two ranges always/never overflows.
OverflowResult unsignedAddMayOverflow(const ConstantRange &Other) const
Return whether unsigned add of the two ranges always/never overflows.
KnownBits toKnownBits() const
Return known bits for values in this range.
ConstantRange zeroExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getSignedMin() const
Return the smallest signed value contained in the ConstantRange.
OverflowResult unsignedMulMayOverflow(const ConstantRange &Other) const
Return whether unsigned mul of the two ranges always/never overflows.
ConstantRange signExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
APInt getSignedMax() const
Return the largest signed value contained in the ConstantRange.
OverflowResult
Represents whether an operation on the given constant range is known to always or never overflow.
@ NeverOverflows
Never overflows.
@ AlwaysOverflowsHigh
Always overflows in the direction of signed/unsigned max value.
@ AlwaysOverflowsLow
Always overflows in the direction of signed/unsigned min value.
@ MayOverflow
May or may not overflow.
uint32_t getBitWidth() const
Get the bit width of this ConstantRange.
OverflowResult signedSubMayOverflow(const ConstantRange &Other) const
Return whether signed sub of the two ranges always/never overflows.
uint64_t getZExtValue() const
const APInt & getAPIntValue() const
This is an important base class in LLVM.
Constant * getSplatValue(bool AllowPoison=false) const
If all elements of the vector constant have the same value, return that value.
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
static ExtOps getExtOps(unsigned FromSize, unsigned ToSize, bool Signed)
Returns the ops for a zero- or sign-extension in a DIExpression.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
static std::optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
Base class for variables.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
void reserve(size_type NumEntries)
Grow the densemap so that it can contain at least NumEntries items before resizing again.
Implements a dense probed hash-table based set.
const char * getSymbol() const
unsigned getTargetFlags() const
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
MachineBasicBlock * MBB
MBB - The current block.
Data structure describing the variable locations in a function.
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
AttributeList getAttributes() const
Return the attribute list for this Function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
int64_t getOffset() const
unsigned getAddressSpace() const
unsigned getTargetFlags() const
const GlobalValue * getGlobal() const
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
unsigned getAddressSpace() const
Module * getParent()
Get the module that this global value is contained inside of...
PointerType * getType() const
Global values are always pointers.
This class is used to form a handle around another node that is persistent and is updated across invo...
static bool compare(const APInt &LHS, const APInt &RHS, ICmpInst::Predicate Pred)
Return result of LHS Pred RHS comparison.
constexpr bool isValid() const
This is an important class for using LLVM in a threaded context.
This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate the offet and size that ar...
This class is used to represent ISD::LOAD nodes.
static LocationSize precise(uint64_t Value)
TypeSize getValue() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MVT getIntegerVT(unsigned BitWidth)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Abstract base class for all machine specific constantpool value subclasses.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
bool isNonTemporal() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
bool isDereferenceable() const
An SDNode that represents everything that will be needed to construct a MachineInstr.
This class is used to represent an MGATHER node.
This class is used to represent an MLOAD node.
This class is used to represent an MSCATTER node.
This class is used to represent an MSTORE node.
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT memvt, MachineMemOperand *MMO)
MachineMemOperand * MMO
Memory reference information.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
unsigned getRawSubclassData() const
Return the SubclassData value, without HasDebugValue.
EVT getMemoryVT() const
Return the type of the in-memory value.
Representation for a specific memory location.
A Module instance is used to store all the information related to an LLVM module.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Pass interface - Implemented by all 'passes'.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Analysis providing profile information.
void Deallocate(SubClass *E)
Deallocate - Release storage for the pointed-to object.
Keeps track of dbg_value information through SDISel.
BumpPtrAllocator & getAlloc()
void add(SDDbgValue *V, bool isParameter)
void erase(const SDNode *Node)
Invalidate all DbgValues attached to the node and remove it from the Node-to-DbgValues map.
ArrayRef< SDDbgValue * > getSDDbgValues(const SDNode *Node) const
Holds the information from a dbg_label node through SDISel.
Holds the information for a single machine location through SDISel; either an SDNode,...
static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo)
static SDDbgOperand fromFrameIdx(unsigned FrameIdx)
static SDDbgOperand fromVReg(unsigned VReg)
static SDDbgOperand fromConst(const Value *Const)
@ SDNODE
Value is the result of an expression.
Holds the information from a dbg_value node through SDISel.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const DebugLoc & getDebugLoc() const
unsigned getIROrder() const
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
ArrayRef< SDUse > ops() const
const APInt & getAsAPIntVal() const
Helper method returns the APInt value of a ConstantSDNode.
void dumprFull(const SelectionDAG *G=nullptr) const
printrFull to dbgs().
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isOnlyUserOf(const SDNode *N) const
Return true if this node is the only use of N.
iterator_range< value_op_iterator > op_values() const
unsigned getIROrder() const
Return the node ordering.
static constexpr size_t getMaxNumOperands()
Return the maximum number of operands that a SDNode can hold.
MemSDNodeBitfields MemSDNodeBits
void Profile(FoldingSetNodeID &ID) const
Gather unique data for the node.
bool getHasDebugValue() const
SDNodeFlags getFlags() const
void setNodeId(int Id)
Set unique node id.
void intersectFlagsWith(const SDNodeFlags Flags)
Clear any flags in this node that aren't also set in Flags.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallVectorImpl< const SDNode * > &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
bool use_empty() const
Return true if there are no uses of this node.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
static bool areOnlyUsersOf(ArrayRef< const SDNode * > Nodes, const SDNode *N)
Return true if all the users of N are contained in Nodes.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
const APInt & getConstantOperandAPInt(unsigned Num) const
Helper method returns the APInt of a ConstantSDNode operand.
bool hasPredecessor(const SDNode *N) const
Return true if N is a predecessor of this node.
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isUndef() const
Return true if the type of the node type undefined.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
Return true if there are exactly NUSES uses of the indicated value.
op_iterator op_end() const
op_iterator op_begin() const
static use_iterator use_end()
void DropOperands()
Release the operands and set this node to have zero operands.
Represents a use of a SDNode.
SDNode * getNode() const
Convenience function for get().getNode().
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
bool reachesChainWithoutSideEffects(SDValue Dest, unsigned Depth=2) const
Return true if this operand (which must be a chain) reaches the specified operand without crossing an...
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
const APInt & getConstantOperandAPInt(unsigned i) const
uint64_t getScalarValueSizeInBits() const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
uint64_t getConstantOperandVal(unsigned i) const
unsigned getOpcode() const
virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo) const
Emit target-specific code that performs a memset.
virtual SDValue EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memmove.
virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memcpy.
SDNodeFlags getFlags() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Align getReducedAlign(EVT VT, bool UseABI)
In most cases this function returns the ABI alignment for a given type, except for illegal vector typ...
SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op)
Return the specified value casted to the target's desired shift amount type.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false)
SDValue getSplatSourceVector(SDValue V, int &SplatIndex)
If V is a splatted value, return the source vector and its splat index.
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
OverflowKind computeOverflowForUnsignedSub(SDValue N0, SDValue N1) const
Determine if the result of the unsigned sub of 2 nodes can overflow.
unsigned ComputeMaxSignificantBits(SDValue Op, unsigned Depth=0) const
Get the upper bound on bit size for this Value Op as a signed integer.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
bool isKnownNeverSNaN(SDValue Op, unsigned Depth=0) const
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
const TargetSubtargetInfo & getSubtarget() const
const APInt * getValidMaximumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of th...
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
void updateDivergence(SDNode *N)
SDValue getSplatValue(SDValue V, bool LegalTypes=false)
If V is a splat vector, return its scalar source operand by extracting that element from the source v...
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
Constant fold a setcc to true or false.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue getNeutralElement(unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags)
Get the (commutative) neutral element for the given opcode, if it exists.
SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing,...
SDValue getFreeze(SDValue V)
Return a freeze using the SDLoc of the value operand.
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type,...
SelectionDAG(const TargetMachine &TM, CodeGenOptLevel)
SDValue getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getStridedLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDNode * isConstantIntBuildVectorOrConstantInt(SDValue N) const
Test whether the given value is a constant int or similar node.
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
Gets a node for an atomic cmpxchg op.
SDValue makeEquivalentMemoryOrdering(SDValue OldChain, SDValue NewMemOpChain)
If an existing load has uses of its chain, create a token factor node with that chain and the new mem...
SDDbgValue * getVRegDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a VReg SDDbgValue node.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
SDValue getJumpTableDebugInfo(int JTI, SDValue Chain, const SDLoc &DL)
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getSymbolFunctionGlobalAddress(SDValue Op, Function **TargetFunction=nullptr)
Return a GlobalAddress of the function from the current module with name matching the given ExternalS...
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
OverflowKind
Used to represent the possible overflow behavior of an operation.
bool isADDLike(SDValue Op) const
Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::AD...
bool haveNoCommonBitsSet(SDValue A, SDValue B) const
Return true if A and B have no common bits set.
bool calculateDivergence(SDNode *N)
SDValue getElementCount(const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
SDValue getGetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A)
Return an AssertAlignSDNode.
SDNode * mutateStrictFPToFP(SDNode *Node)
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain a...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getBitcastedZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal)
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
void VerifyDAGDivergence()
bool shouldOptForSize() const
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT,...
const TargetLowering & getTargetLoweringInfo() const
bool isEqualTo(SDValue A, SDValue B) const
Test whether two SDValues are known to compare equal.
static constexpr unsigned MaxRecursionDepth
SDValue getStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue expandVACopy(SDNode *Node)
Expand the specified ISD::VACOPY node as the Legalize pass would.
SDValue getIndexedMaskedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
APInt computeVectorKnownZeroElements(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
For each demanded element of a vector, see if it is known to be zero.
void AddDbgValue(SDDbgValue *DB, bool isParameter)
Add a dbg_value SDNode.
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
void salvageDebugInfo(SDNode &N)
To be invoked on an SDNode that is slated to be erased.
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
std::pair< SDValue, SDValue > UnrollVectorOverflowOp(SDNode *N, unsigned ResNE=0)
Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
allnodes_const_iterator allnodes_begin() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
Test whether V has a splatted value for all the demanded elements.
void DeleteNode(SDNode *N)
Remove the specified node from the system.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDDbgValue * getDbgValueList(DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
Creates a SDDbgValue node from a list of locations.
SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT)
Create negative operation as (SUB 0, Val).
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
SDValue simplifySelect(SDValue Cond, SDValue TVal, SDValue FVal)
Try to simplify a select/vselect into 1 of its operands or a constant.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
const DataLayout & getDataLayout() const
SDNode * isConstantFPBuildVectorOrConstantFP(SDValue N) const
Test whether the given value is a constant FP or similar node.
SDValue expandVAArg(SDNode *Node)
Expand the specified ISD::VAARG node as the Legalize pass would.
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
Check if a node exists without modifying its flags.
bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
Return true if loads are next to each other and can be merged.
SDDbgLabel * getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O)
Creates a SDDbgLabel node.
SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
OverflowKind computeOverflowForUnsignedMul(SDValue N0, SDValue N1) const
Determine if the result of the unsigned mul of 2 nodes can overflow.
void copyExtraInfo(SDNode *From, SDNode *To)
Copy extra info associated with one node to another.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV)
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swa...
std::pair< SDValue, SDValue > SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
const APInt * getValidShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has a constant or splat constant shift amount that is less than the element b...
SDValue makeStateFunctionCall(unsigned LibFunc, SDValue Ptr, SDValue InChain, const SDLoc &DLoc)
Helper used to make a call to a library function that has one argument of pointer type.
bool isGuaranteedNotToBeUndefOrPoison(SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getIndexedLoadVP(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
OverflowKind computeOverflowForSignedMul(SDValue N0, SDValue N1) const
Determine if the result of the signed mul of 2 nodes can overflow.
MaybeAlign InferPtrAlign(SDValue Ptr) const
Infer alignment of a load / store address.
bool MaskedValueIsAllOnes(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if '(Op & Mask) == Mask'.
bool SignBitIsZero(SDValue Op, unsigned Depth=0) const
Return true if the sign bit of Op is known to be zero.
SDValue getRegister(unsigned Reg, EVT VT)
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, FunctionVarLocs const *FnVarLocs)
Prepare this SelectionDAG to process code in the given MachineFunction.
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
void AddDbgLabel(SDDbgLabel *DB)
Add a dbg_label SDNode.
bool isConstantValueOfAnyType(SDValue N) const
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getBasicBlock(MachineBasicBlock *MBB)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
bool isKnownToBeAPowerOfTwo(SDValue Val, unsigned Depth=0) const
Test if the given value is known to have exactly one bit set.
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label)
SDValue getIndexedStoreVP(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
bool isKnownNeverZero(SDValue Op, unsigned Depth=0) const
Test whether the given SDValue is known to contain non-zero value(s).
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getSetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
std::pair< SDValue, SDValue > getStrictFPExtendOrRound(SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT)
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending...
std::pair< SDValue, SDValue > SplitEVL(SDValue N, EVT VecVT, const SDLoc &DL)
Split the explicit vector length parameter of a VP operation.
SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or perform...
SDValue getVPLogicalNOT(const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT)
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask,...
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
iterator_range< allnodes_iterator > allnodes()
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue WidenVector(const SDValue &N, const SDLoc &DL)
Widen the vector up to the next power of two using INSERT_SUBVECTOR.
bool isKnownNeverZeroFloat(SDValue Op) const
Test whether the given floating point SDValue is known to never be positive or negative zero.
SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDDbgValue * getConstantDbgValue(DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
Creates a constant SDDbgValue node.
SDValue getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getValueType(EVT)
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD) const
Get the debug values which reference the given SDNode.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
OverflowKind computeOverflowForSignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the signed addition of 2 nodes can overflow.
SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by tr...
unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
ilist< SDNode >::size_type allnodes_size() const
SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
bool isKnownNeverNaN(SDValue Op, bool SNaN=false, unsigned Depth=0) const
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
SDValue getIndexedMaskedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTruncStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
bool MaskedVectorIsZero(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
Return true if 'Op' is known to be zero in DemandedElts.
SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT)
Create a true or false constant of type VT using the target's BooleanContent for type OpVT.
SDDbgValue * getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a FrameIndex SDDbgValue node.
SDValue getExtStridedLoadVP(ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy ...
bool canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
OverflowKind computeOverflowForUnsignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the unsigned addition of 2 nodes can overflow.
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getTruncStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
void canonicalizeCommutativeBinop(unsigned Opcode, SDValue &N1, SDValue &N2) const
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite o...
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1)
Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the por...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
OverflowKind computeOverflowForSignedSub(SDValue N0, SDValue N1) const
Determine if the result of the signed sub of 2 nodes can overflow.
LLVMContext * getContext() const
SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags)
Try to simplify a floating-point binary operation into 1 of its operands or a constant.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
const APInt * getValidMinimumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of th...
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL, bool LegalTypes=true)
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
bool isUndef(unsigned Opcode, ArrayRef< SDValue > Ops)
Return true if the result of this operation is always undefined.
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
std::pair< EVT, EVT > GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been sp...
SDValue foldConstantFPMath(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
Fold floating-point operations when all operands are constants and/or undefined.
SDNode * getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
Get the specified node if it's already available, or else return NULL.
SDValue FoldSymbolOffset(unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2)
SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDDbgValue * getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a SDDbgValue node.
SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)
Returns a node representing a splat of one value into all lanes of the provided vector type.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
SDValue matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false)
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector ...
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
SDValue simplifyShift(SDValue X, SDValue Y)
Try to simplify a shift into 1 of its operands or a constant.
void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true)
Transfer debug values from one node to another, while optionally generating fragment expressions for ...
SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a logical NOT operation as (XOR Val, BooleanOne).
SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
ilist< SDNode >::iterator allnodes_iterator
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
static bool isSplatMask(const int *Mask, EVT VT)
int getMaskElt(unsigned Idx) const
ArrayRef< int > getMask() const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void assign(size_type NumElts, ValueParamT Elt)
reference emplace_back(ArgTypes &&... Args)
void reserve(size_type N)
iterator erase(const_iterator CI)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Completely target-dependent object reference.
int64_t getOffset() const
unsigned getTargetFlags() const
Provides information about what library functions are available for the current target.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
const TargetMachine & getTargetMachine() const
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
virtual bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
Return true if the target shall perform extract vector element and store given that the vector is kno...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
BooleanContent
Enum that describes how the target represents true/false values.
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
virtual unsigned getMaxGluedStoresPerMemcpy() const
Get maximum # of store operations to be glued together.
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
std::vector< ArgListEntry > ArgListTy
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
virtual bool isLegalStoreImmediate(int64_t Value) const
Return true if the specified immediate is legal for the value input of a store instruction.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
static ISD::NodeType getExtendForContent(BooleanContent Content)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual void computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const
Determine which of the bits of FrameIndex FIOp are known to be 0.
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
virtual void verifyTargetSDNode(const SDNode *N) const
Check the given SDNode. Aborts if it is invalid.
virtual bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const
Determines the optimal series of memory ops to replace the memset / memcpy.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const
If SNaN is false,.
virtual void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const
virtual bool isSDNodeAlwaysUniform(const SDNode *N) const
virtual bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
virtual const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const
This method returns the constant pool value that will be loaded by LD.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
virtual bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
virtual bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
Primary interface to the complete machine description for the target machine.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetLowering * getTargetLowering() const
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
static Type * getVoidTy(LLVMContext &C)
static IntegerType * getInt8Ty(LLVMContext &C)
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
A Use represents the edge between a Value definition and its users.
This class is used to represent an VP_GATHER node.
This class is used to represent a VP_LOAD node.
This class is used to represent an VP_SCATTER node.
This class is used to represent a VP_STORE node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_LOAD node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_STORE node.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
constexpr ScalarTy getFixedValue() const
static constexpr bool isKnownLE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr bool isKnownEven() const
A return value of true indicates we know at compile time that the number of elements (vscale * Min) i...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
SmartMutex - A mutex with a compile time constant parameter that indicates whether this mutex should ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APInt mulhu(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on zero-extended operands.
const APInt abdu(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be unsigned.
APInt avgCeilU(const APInt &C1, const APInt &C2)
Compute the ceil of the unsigned average of C1 and C2.
APInt avgFloorU(const APInt &C1, const APInt &C2)
Compute the floor of the unsigned average of C1 and C2.
const APInt abds(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be signed.
APInt mulhs(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on sign-extended operands.
APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth, bool MatchAllBits=false)
Splat/Merge neighboring bits to widen/narrow the bitmask represented by.
APInt avgFloorS(const APInt &C1, const APInt &C2)
Compute the floor of the signed average of C1 and C2.
APInt avgCeilS(const APInt &C1, const APInt &C2)
Compute the ceil of the signed average of C1 and C2.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X...
bool isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are ~0 ...
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ JUMP_TABLE_DEBUG_INFO
JUMP_TABLE_DEBUG_INFO - Jumptable debug info.
@ BSWAP
Byte Swap and Counting operators.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ SSUBO
Same for subtraction.
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ UNDEF
UNDEF - An undefined node.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
@ BasicBlock
Various leaf nodes.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ LIFETIME_START
This corresponds to the llvm.lifetime.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ GET_FPENV_MEM
Gets the current floating-point environment.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ SET_FPENV_MEM
Sets the current floating point environment.
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
unsigned getVPForBaseOpcode(unsigned Opcode)
Translate this non-VP Opcode to its corresponding VP Opcode.
bool isBuildVectorOfConstantSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantSDNode or undef.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
bool matchUnaryPredicate(SDValue Op, std::function< bool(ConstantSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantSDNode predicate.
bool isZEXTLoad(const SDNode *N)
Returns true if the specified node is a ZEXTLOAD.
bool matchUnaryFpPredicate(SDValue Op, std::function< bool(ConstantFPSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantFPSDNode predicate.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
bool isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are 0 o...
bool isVectorShrinkable(const SDNode *N, unsigned NewEltSize, bool Signed)
Returns true if the specified node is a vector where all elements can be truncated to the specified e...
bool matchUnaryPredicateImpl(SDValue Op, std::function< bool(ConstNodeType *)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant BUI...
bool isVPBinaryOp(unsigned Opcode)
Whether this is a vector-predicated binary operation opcode.
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
std::optional< unsigned > getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept)
Translate this VP Opcode to its corresponding non-VP Opcode.
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal.
std::optional< unsigned > getVPMaskIdx(unsigned Opcode)
The operand position of the vector mask.
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
std::optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)
The operand position of the explicit vector length parameter.
bool isEXTLoad(const SDNode *N)
Returns true if the specified node is a EXTLOAD.
bool allOperandsUndef(const SDNode *N)
Return true if the node has at least one operand and all operands of the specified node are ISD::UNDE...
bool isFreezeUndef(const SDNode *N)
Return true if the specified node is FREEZE(UNDEF).
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
bool isConstantSplatVector(const SDNode *N, APInt &SplatValue)
Node predicates.
bool matchBinaryPredicate(SDValue LHS, SDValue RHS, std::function< bool(ConstantSDNode *, ConstantSDNode *)> Match, bool AllowUndefs=false, bool AllowTypeMismatch=false)
Attempt to match a binary predicate against a pair of scalar/splat constants or every element of a pa...
bool isVPReduction(unsigned Opcode)
Whether this is a vector-predicated reduction opcode.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
bool isBuildVectorOfConstantFPSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantFPSDNode or undef.
bool isSEXTLoad(const SDNode *N)
Returns true if the specified node is a SEXTLOAD.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.
NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode)
Get underlying scalar opcode for VECREDUCE opcode.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X ...
BinaryOp_match< LHS, RHS, Instruction::And > m_And(const LHS &L, const RHS &R)
deferredval_ty< Value > m_Deferred(Value *const &V)
Like m_Specific(), but works if the specific value to match is determined as part of the same match()...
BinaryOp_match< cst_pred_ty< is_zero_int >, ValTy, Instruction::Sub > m_Neg(const ValTy &V)
Matches a 'Neg' as 'sub 0, V'.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
bool sd_match(SDNode *N, const SelectionDAG *DAG, Pattern &&P)
initializer< Ty > init(const Ty &Val)
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
std::lock_guard< SmartMutex< mt_only > > SmartScopedLock
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
bool operator<(int64_t V1, const APSInt &V2)
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
SDValue peekThroughExtractSubvectors(SDValue V)
Return the non-extracted vector source operand of V if it exists.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
SDValue getBitwiseNotOperand(SDValue V, SDValue Mask, bool AllowUndefs)
If V is a bitwise not, returns the inverted operand.
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
bool isIntOrFPConstant(SDValue V)
Return true if V is either a integer or FP constant.
bool getAlign(const Function &F, unsigned index, unsigned &align)
bool getConstantDataArrayInfo(const Value *V, ConstantDataArraySlice &Slice, unsigned ElementSize, uint64_t Offset=0)
Returns true if the value V is a pointer into a ConstantDataArray.
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
bool isMinSignedConstant(SDValue V)
Returns true if V is a constant min signed integer value.
ConstantFPSDNode * isConstOrConstSplatFP(SDValue N, bool AllowUndefs=false)
Returns the SDNode if it is a constant splat BuildVector or constant float.
ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)
Parse out a conservative ConstantRange from !range metadata.
APFloat frexp(const APFloat &X, int &Exp, APFloat::roundingMode RM)
Equivalent of C standard library function.
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
bool getShuffleDemandedElts(int SrcWidth, ArrayRef< int > Mask, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS, bool AllowUndefElts=false)
Transform a shuffle mask's output demanded element mask into demanded element masks for the 2 operand...
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 maximumNumber semantics.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void checkForCycles(const SelectionDAG *DAG, bool force=false)
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
SDValue peekThroughTruncates(SDValue V)
Return the non-truncated source operand of V if it exists.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
SDValue peekThroughOneUseBitcasts(SDValue V)
Return the non-bitcasted and one-use source operand of V if it exists.
CodeGenOptLevel
Code generation optimization level.
bool isOneOrOneSplat(SDValue V, bool AllowUndefs=false)
Return true if the value is a constant 1 integer or a splatted vector of a constant 1 integer (with n...
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 minimumNumber semantics.
@ Mul
Product of integers.
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
DWARFExpression::Operation Op
ConstantSDNode * isConstOrConstSplat(SDValue N, bool AllowUndefs=false, bool AllowTruncation=false)
Returns the SDNode if it is a constant splat BuildVector or constant int.
OutputIt copy(R &&Range, OutputIt Out)
constexpr unsigned BitWidth
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool isNullFPConstant(SDValue V)
Returns true if V is an FP constant with a value of positive zero.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void computeKnownBitsFromRangeMetadata(const MDNode &Ranges, KnownBits &Known)
Compute known bits from the range metadata.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
bool isNeutralConstant(unsigned Opc, SDNodeFlags Flags, SDValue V, unsigned OperandNo)
Returns true if V is a neutral element of Opc with Flags.
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * TBAAStruct
The tag for type-based alias analysis (tbaa struct).
MDNode * TBAA
The tag for type-based alias analysis.
static const fltSemantics & IEEEsingle() LLVM_READNONE
cmpResult
IEEE-754R 5.11: Floating Point Comparison Relations.
static constexpr roundingMode rmTowardNegative
static constexpr roundingMode rmNearestTiesToEven
static constexpr roundingMode rmTowardZero
static const fltSemantics & IEEEquad() LLVM_READNONE
static const fltSemantics & IEEEdouble() LLVM_READNONE
static const fltSemantics & IEEEhalf() LLVM_READNONE
static constexpr roundingMode rmTowardPositive
static const fltSemantics & BFloat() LLVM_READNONE
opStatus
IEEE-754R 7: Default exception handling.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Represents offset+length into a ConstantDataArray.
uint64_t Length
Length of the slice.
uint64_t Offset
Slice starts at this Offset.
void move(uint64_t Delta)
Moves the Offset and adjusts Length accordingly.
const ConstantDataArray * Array
ConstantDataArray pointer.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
intptr_t getRawBits() const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
bool bitsEq(EVT VT) const
Return true if this has the same number of bits as VT.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
KnownBits sextInReg(unsigned SrcBitWidth) const
Return known bits for a in-register sign extension of the value we're tracking.
static KnownBits mulhu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from zero-extended multiply-hi.
unsigned countMinSignBits() const
Returns the number of times the sign bit is replicated into the other bits.
static KnownBits smax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smax(LHS, RHS).
bool isNonNegative() const
Returns true if this value is known to be non-negative.
bool isZero() const
Returns true if value is all zero.
void makeNonNegative()
Make this value non-negative.
static KnownBits usub_sat(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from llvm.usub.sat(LHS, RHS)
unsigned countMinTrailingZeros() const
Returns the minimum number of trailing zero bits.
static KnownBits ashr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for ashr(LHS, RHS).
static KnownBits urem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for urem(LHS, RHS).
bool isUnknown() const
Returns true if we don't know any bits.
unsigned countMaxTrailingZeros() const
Returns the maximum number of trailing zero bits possible.
static std::optional< bool > ne(const KnownBits &LHS, const KnownBits &RHS)
Determine if these known bits always give the same ICMP_NE result.
void makeNegative()
Make this value negative.
KnownBits trunc(unsigned BitWidth) const
Return known bits for a truncation of the value we're tracking.
KnownBits byteSwap() const
bool hasConflict() const
Returns true if there is conflicting information.
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
void setAllZero()
Make all bits known to be zero and discard any previous information.
KnownBits reverseBits() const
KnownBits concat(const KnownBits &Lo) const
Concatenate the bits from Lo onto the bottom of *this.
unsigned getBitWidth() const
Get the bit width of this value.
static KnownBits umax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umax(LHS, RHS).
KnownBits zext(unsigned BitWidth) const
Return known bits for a zero extension of the value we're tracking.
void resetAll()
Resets the known state of all bits.
KnownBits unionWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for either this or RHS or both.
static KnownBits lshr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for lshr(LHS, RHS).
bool isNonZero() const
Returns true if this value is known to be non-zero.
static KnownBits abdu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for abdu(LHS, RHS).
KnownBits extractBits(unsigned NumBits, unsigned BitPosition) const
Return a subset of the known bits from [bitPosition,bitPosition+numBits).
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
static KnownBits computeForSubBorrow(const KnownBits &LHS, KnownBits RHS, const KnownBits &Borrow)
Compute known bits results from subtracting RHS from LHS with 1-bit Borrow.
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
APInt getMaxValue() const
Return the maximal unsigned value possible given these KnownBits.
static KnownBits abds(KnownBits LHS, KnownBits RHS)
Compute known bits for abds(LHS, RHS).
static KnownBits smin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smin(LHS, RHS).
static KnownBits mulhs(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from sign-extended multiply-hi.
static KnownBits srem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for srem(LHS, RHS).
static KnownBits udiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for udiv(LHS, RHS).
static KnownBits computeForAddSub(bool Add, bool NSW, bool NUW, const KnownBits &LHS, const KnownBits &RHS)
Compute known bits resulting from adding LHS and RHS.
bool isStrictlyPositive() const
Returns true if this value is known to be positive.
static KnownBits sdiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for sdiv(LHS, RHS).
static bool haveNoCommonBitsSet(const KnownBits &LHS, const KnownBits &RHS)
Return true if LHS and RHS have no common bits set.
bool isNegative() const
Returns true if this value is known to be negative.
static KnownBits computeForAddCarry(const KnownBits &LHS, const KnownBits &RHS, const KnownBits &Carry)
Compute known bits resulting from adding LHS, RHS and a 1-bit Carry.
unsigned countMaxLeadingZeros() const
Returns the maximum number of leading zero bits possible.
void insertBits(const KnownBits &SubBits, unsigned BitPosition)
Insert the bits from a smaller known bits starting at bitPosition.
static KnownBits mul(const KnownBits &LHS, const KnownBits &RHS, bool NoUndefSelfMultiply=false)
Compute known bits resulting from multiplying LHS and RHS.
KnownBits anyext(unsigned BitWidth) const
Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...
KnownBits abs(bool IntMinIsPoison=false) const
Compute known bits for the absolute value.
static KnownBits shl(const KnownBits &LHS, const KnownBits &RHS, bool NUW=false, bool NSW=false, bool ShAmtNonZero=false)
Compute known bits for shl(LHS, RHS).
static KnownBits umin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umin(LHS, RHS).
This class contains a discriminated union of information about pointers in memory operands,...
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign, bool IsZeroMemset, bool IsVolatile)
static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, Align SrcAlign, bool IsVolatile, bool MemcpyStrSrc=false)
These are IR-level optimization flags that may be propagated to SDNodes.
void intersectWith(const SDNodeFlags Flags)
Clear any flags in this flag set that aren't also set in Flags.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Clients of various APIs that cause global effects on the DAG can optionally implement this interface.
DAGUpdateListener *const Next
virtual void NodeDeleted(SDNode *N, SDNode *E)
The node N that was deleted and, if E is not null, an equivalent node E that replaced it.
virtual void NodeInserted(SDNode *N)
The node N that was inserted.
virtual void NodeUpdated(SDNode *N)
The node N that was updated.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)