47#define GET_INSTRINFO_CTOR_DTOR
48#define GET_INSTRMAP_INFO
49#include "SystemZGenInstrInfo.inc"
51#define DEBUG_TYPE "systemz-II"
55 return Count == 0 ? 0 : (
uint64_t(1) << (Count - 1) << 1) - 1;
59void SystemZInstrInfo::anchor() {}
63 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
69 unsigned NewOpcode)
const {
84 HighRegOp.
setReg(RI.getSubReg(HighRegOp.
getReg(), SystemZ::subreg_h64));
85 LowRegOp.
setReg(RI.getSubReg(LowRegOp.
getReg(), SystemZ::subreg_l64));
112 assert(HighOpcode && LowOpcode &&
"Both offsets should be in range");
115 MI->setDesc(
get(LowOpcode));
131 assert(NewOpcode &&
"No support for huge argument lists yet");
132 MI->setDesc(
get(NewOpcode));
142void SystemZInstrInfo::expandRIPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
144 bool ConvertHigh)
const {
147 MI.setDesc(
get(IsHigh ? HighOpcode : LowOpcode));
148 if (IsHigh && ConvertHigh)
149 MI.getOperand(1).setImm(
uint32_t(
MI.getOperand(1).getImm()));
156void SystemZInstrInfo::expandRIEPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
158 unsigned HighOpcode)
const {
163 if (!DestIsHigh && !SrcIsHigh)
164 MI.setDesc(
get(LowOpcodeK));
166 if (DestReg != SrcReg) {
167 emitGRX32Move(*
MI.getParent(),
MI,
MI.getDebugLoc(), DestReg, SrcReg,
168 SystemZ::LR, 32,
MI.getOperand(1).isKill(),
169 MI.getOperand(1).isUndef());
170 MI.getOperand(1).setReg(DestReg);
172 MI.setDesc(
get(DestIsHigh ? HighOpcode : LowOpcode));
173 MI.tieOperands(0, 1);
180void SystemZInstrInfo::expandRXYPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
181 unsigned HighOpcode)
const {
185 MI.getOperand(2).getImm());
186 MI.setDesc(
get(Opcode));
192void SystemZInstrInfo::expandLOCPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
193 unsigned HighOpcode)
const {
196 MI.setDesc(
get(Opcode));
202void SystemZInstrInfo::expandZExtPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
203 unsigned Size)
const {
205 emitGRX32Move(*
MI.getParent(),
MI,
MI.getDebugLoc(),
206 MI.getOperand(0).getReg(),
MI.getOperand(1).getReg(), LowOpcode,
207 Size,
MI.getOperand(1).isKill(),
MI.getOperand(1).isUndef());
213 MI.eraseFromParent();
216void SystemZInstrInfo::expandLoadStackGuard(
MachineInstr *
MI)
const {
219 const Register Reg64 =
MI->getOperand(0).getReg();
220 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
241 MI->setDesc(
get(SystemZ::LG));
254 unsigned SrcReg,
unsigned LowLowOpcode,
255 unsigned Size,
bool KillSrc,
256 bool UndefSrc)
const {
260 if (DestIsHigh && SrcIsHigh)
261 Opcode = SystemZ::RISBHH;
262 else if (DestIsHigh && !SrcIsHigh)
263 Opcode = SystemZ::RISBHL;
264 else if (!DestIsHigh && SrcIsHigh)
265 Opcode = SystemZ::RISBLH;
270 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
280 unsigned OpIdx2)
const {
283 return *
MI.getParent()->getParent()->CloneMachineInstr(&
MI);
287 switch (
MI.getOpcode()) {
288 case SystemZ::SELRMux:
289 case SystemZ::SELFHR:
292 case SystemZ::LOCRMux:
293 case SystemZ::LOCFHR:
295 case SystemZ::LOCGR: {
296 auto &WorkingMI = cloneIfNew(
MI);
298 unsigned CCValid = WorkingMI.getOperand(3).getImm();
299 unsigned CCMask = WorkingMI.getOperand(4).getImm();
300 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
317 if ((MCID.
TSFlags & Flag) &&
MI.getOperand(1).isFI() &&
318 MI.getOperand(2).getImm() == 0 &&
MI.getOperand(3).getReg() == 0) {
319 FrameIndex =
MI.getOperand(1).getIndex();
320 return MI.getOperand(0).getReg();
326 int &FrameIndex)
const {
331 int &FrameIndex)
const {
337 int &SrcFrameIndex)
const {
340 if (
MI.getOpcode() != SystemZ::MVC || !
MI.getOperand(0).isFI() ||
341 MI.getOperand(1).getImm() != 0 || !
MI.getOperand(3).isFI() ||
342 MI.getOperand(4).getImm() != 0)
346 int64_t
Length =
MI.getOperand(2).getImm();
347 unsigned FI1 =
MI.getOperand(0).getIndex();
348 unsigned FI2 =
MI.getOperand(3).getIndex();
353 DestFrameIndex = FI1;
362 bool AllowModify)
const {
370 if (
I->isDebugInstr())
375 if (!isUnpredicatedTerminator(*
I))
385 if (!Branch.hasMBBTarget())
395 TBB = Branch.getMBBTarget();
408 I->eraseFromParent();
414 TBB = Branch.getMBBTarget();
422 TBB = Branch.getMBBTarget();
429 assert(
Cond.size() == 2 &&
TBB &&
"Should have seen a conditional branch");
433 if (
TBB != Branch.getMBBTarget())
437 unsigned OldCCValid =
Cond[0].getImm();
438 unsigned OldCCMask =
Cond[1].getImm();
439 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
450 int *BytesRemoved)
const {
451 assert(!BytesRemoved &&
"code size not handled");
459 if (
I->isDebugInstr())
466 I->eraseFromParent();
476 assert(
Cond.size() == 2 &&
"Invalid condition");
486 int *BytesAdded)
const {
492 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
494 "SystemZ branch conditions have one component!");
495 assert(!BytesAdded &&
"code size not handled");
499 assert(!FBB &&
"Unconditional branch with multiple successors!");
506 unsigned CCValid =
Cond[0].getImm();
507 unsigned CCMask =
Cond[1].getImm();
522 int64_t &
Value)
const {
523 assert(
MI.isCompare() &&
"Caller should have checked for a comparison");
525 if (
MI.getNumExplicitOperands() == 2 &&
MI.getOperand(0).isReg() &&
526 MI.getOperand(1).isImm()) {
527 SrcReg =
MI.getOperand(0).getReg();
529 Value =
MI.getOperand(1).getImm();
542 int &FalseCycles)
const {
544 if (!STI.hasLoadStoreOnCond())
546 if (Pred.
size() != 2)
552 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
557 if ((STI.hasLoadStoreOnCond2() &&
558 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
559 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
560 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
580 assert(Pred.
size() == 2 &&
"Invalid condition");
581 unsigned CCValid = Pred[0].getImm();
582 unsigned CCMask = Pred[1].getImm();
585 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
586 if (STI.hasMiscellaneousExtensions3())
587 Opc = SystemZ::SELRMux;
588 else if (STI.hasLoadStoreOnCond2())
589 Opc = SystemZ::LOCRMux;
592 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
593 Register TReg =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
594 Register FReg =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
600 }
else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
601 if (STI.hasMiscellaneousExtensions3())
602 Opc = SystemZ::SELGR;
604 Opc = SystemZ::LOCGR;
618 DefMI =
MRI->getVRegDef(FoldAsLoadDefReg);
620 bool SawStore =
false;
622 !
MRI->hasOneNonDBGUse(FoldAsLoadDefReg))
626 MI.findRegisterUseOperandIdx(FoldAsLoadDefReg,
nullptr);
627 assert(UseOpIdx != -1 &&
"Expected FoldAsLoadDefReg to be used by MI.");
632 FoldAsLoadDefReg = 0;
642 unsigned DefOpc =
DefMI.getOpcode();
644 if (DefOpc == SystemZ::VGBM) {
645 int64_t ImmVal =
DefMI.getOperand(1).getImm();
660 MRI->getRegClass(CopyDstReg) == &SystemZ::GR128BitRegClass &&
661 MRI->hasOneNonDBGUse(Reg)) {
665 Register TmpReg =
MRI->createVirtualRegister(&SystemZ::GR64BitRegClass);
670 UseMI.setDesc(
get(SystemZ::REG_SEQUENCE));
671 UseMI.getOperand(1).setReg(TmpReg);
673 .
addImm(SystemZ::subreg_h64)
675 .
addImm(SystemZ::subreg_l64);
677 if (
MRI->use_nodbg_empty(Reg))
678 DefMI.eraseFromParent();
685 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
686 DefOpc != SystemZ::LGHI)
690 int32_t ImmVal = (int32_t)
DefMI.getOperand(1).getImm();
692 unsigned UseOpc =
UseMI.getOpcode();
698 case SystemZ::SELRMux:
701 case SystemZ::LOCRMux:
702 if (!STI.hasLoadStoreOnCond2())
704 NewUseOpc = SystemZ::LOCHIMux;
708 UseIdx = 2, CommuteIdx = 1;
716 if (!STI.hasLoadStoreOnCond2())
718 NewUseOpc = SystemZ::LOCGHI;
722 UseIdx = 2, CommuteIdx = 1;
730 if (CommuteIdx != -1)
731 if (!commuteInstruction(
UseMI,
false, CommuteIdx, UseIdx))
734 bool DeleteDef =
MRI->hasOneNonDBGUse(Reg);
737 UseMI.tieOperands(0, 1);
738 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
740 DefMI.eraseFromParent();
746 unsigned Opcode =
MI.getOpcode();
747 if (Opcode == SystemZ::Return ||
748 Opcode == SystemZ::Return_XPLINK ||
749 Opcode == SystemZ::Trap ||
750 Opcode == SystemZ::CallJG ||
751 Opcode == SystemZ::CallBR)
758 unsigned NumCycles,
unsigned ExtraPredCycles,
772 return NumCycles == 1;
777 unsigned NumCyclesT,
unsigned ExtraPredCyclesT,
779 unsigned NumCyclesF,
unsigned ExtraPredCyclesF,
789 return NumCycles == 1;
794 assert(Pred.
size() == 2 &&
"Invalid condition");
795 unsigned CCValid = Pred[0].getImm();
796 unsigned CCMask = Pred[1].getImm();
797 assert(CCMask > 0 && CCMask < 15 &&
"Invalid predicate");
798 unsigned Opcode =
MI.getOpcode();
799 if (Opcode == SystemZ::Trap) {
800 MI.setDesc(
get(SystemZ::CondTrap));
806 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
807 MI.setDesc(
get(Opcode == SystemZ::Return ? SystemZ::CondReturn
808 : SystemZ::CondReturn_XPLINK));
815 if (Opcode == SystemZ::CallJG) {
817 const uint32_t *RegMask =
MI.getOperand(1).getRegMask();
820 MI.setDesc(
get(SystemZ::CallBRCL));
829 if (Opcode == SystemZ::CallBR) {
831 const uint32_t *RegMask =
MI.getOperand(1).getRegMask();
834 MI.setDesc(
get(SystemZ::CallBCR));
852 if (SystemZ::GR128BitRegClass.
contains(DestReg, SrcReg)) {
854 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
858 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
864 if (SystemZ::GRX32BitRegClass.
contains(DestReg, SrcReg)) {
865 emitGRX32Move(
MBB,
MBBI,
DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
871 if (SystemZ::VR128BitRegClass.
contains(DestReg) &&
872 SystemZ::FP128BitRegClass.
contains(SrcReg)) {
874 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
875 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
877 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
878 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
885 if (SystemZ::FP128BitRegClass.
contains(DestReg) &&
886 SystemZ::VR128BitRegClass.
contains(SrcReg)) {
888 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
889 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
891 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
892 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
894 if (DestRegHi != SrcReg)
901 if (SystemZ::FP128BitRegClass.
contains(DestReg) &&
902 SystemZ::GR128BitRegClass.
contains(SrcReg)) {
903 MCRegister DestRegHi = RI.getSubReg(DestReg, SystemZ::subreg_h64);
904 MCRegister DestRegLo = RI.getSubReg(DestReg, SystemZ::subreg_l64);
905 MCRegister SrcRegHi = RI.getSubReg(SrcReg, SystemZ::subreg_h64);
906 MCRegister SrcRegLo = RI.getSubReg(SrcReg, SystemZ::subreg_l64);
918 if (DestReg == SystemZ::CC) {
920 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
927 if (SystemZ::GR128BitRegClass.
contains(DestReg) &&
928 SystemZ::VR128BitRegClass.
contains(SrcReg)) {
929 MCRegister DestH64 = RI.getSubReg(DestReg, SystemZ::subreg_h64);
930 MCRegister DestL64 = RI.getSubReg(DestReg, SystemZ::subreg_l64);
934 .
addReg(SystemZ::NoRegister)
939 .
addReg(SystemZ::NoRegister)
944 if (SystemZ::VR128BitRegClass.
contains(DestReg) &&
945 SystemZ::GR128BitRegClass.
contains(SrcReg)) {
947 .
addReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64))
948 .
addReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64));
954 if (SystemZ::GR64BitRegClass.
contains(DestReg, SrcReg))
955 Opcode = SystemZ::LGR;
956 else if (SystemZ::FP32BitRegClass.
contains(DestReg, SrcReg))
958 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
959 else if (SystemZ::FP64BitRegClass.
contains(DestReg, SrcReg))
960 Opcode = SystemZ::LDR;
961 else if (SystemZ::FP128BitRegClass.
contains(DestReg, SrcReg))
962 Opcode = SystemZ::LXR;
963 else if (SystemZ::VR32BitRegClass.
contains(DestReg, SrcReg))
964 Opcode = SystemZ::VLR32;
965 else if (SystemZ::VR64BitRegClass.
contains(DestReg, SrcReg))
966 Opcode = SystemZ::VLR64;
967 else if (SystemZ::VR128BitRegClass.
contains(DestReg, SrcReg))
968 Opcode = SystemZ::VLR;
969 else if (SystemZ::AR32BitRegClass.
contains(DestReg, SrcReg))
970 Opcode = SystemZ::CPYA;
986 unsigned LoadOpcode, StoreOpcode;
1003 unsigned LoadOpcode, StoreOpcode;
1013 return ((MCID.
TSFlags & Flag) &&
1014 isUInt<12>(
MI->getOperand(2).getImm()) &&
1015 MI->getOperand(3).getReg() == 0);
1021 LogicOp() =
default;
1022 LogicOp(
unsigned regSize,
unsigned immLSB,
unsigned immSize)
1023 :
RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
1025 explicit operator bool()
const {
return RegSize; }
1028 unsigned ImmLSB = 0;
1029 unsigned ImmSize = 0;
1036 case SystemZ::NILMux:
return LogicOp(32, 0, 16);
1037 case SystemZ::NIHMux:
return LogicOp(32, 16, 16);
1038 case SystemZ::NILL64:
return LogicOp(64, 0, 16);
1039 case SystemZ::NILH64:
return LogicOp(64, 16, 16);
1040 case SystemZ::NIHL64:
return LogicOp(64, 32, 16);
1041 case SystemZ::NIHH64:
return LogicOp(64, 48, 16);
1042 case SystemZ::NIFMux:
return LogicOp(32, 0, 32);
1043 case SystemZ::NILF64:
return LogicOp(64, 0, 32);
1044 case SystemZ::NIHF64:
return LogicOp(64, 32, 32);
1045 default:
return LogicOp();
1053 if (CCDef !=
nullptr)
1075 unsigned Start,
End;
1078 if (
And.RegSize == 64) {
1079 NewOpcode = SystemZ::RISBG;
1081 if (STI.hasMiscellaneousExtensions())
1082 NewOpcode = SystemZ::RISBGN;
1084 NewOpcode = SystemZ::RISBMux;
1100 unsigned NumOps =
MI.getNumOperands();
1101 for (
unsigned I = 1;
I < NumOps; ++
I) {
1103 if (
Op.isReg() &&
Op.isKill())
1117 bool Invert)
const {
1123 Opc = *InverseOpcode;
1130 case SystemZ::WFADB:
1131 case SystemZ::WFASB:
1132 case SystemZ::WFAXB:
1133 case SystemZ::VFADB:
1134 case SystemZ::VFASB:
1135 case SystemZ::WFMDB:
1136 case SystemZ::WFMSB:
1137 case SystemZ::WFMXB:
1138 case SystemZ::VFMDB:
1139 case SystemZ::VFMSB:
1147std::optional<unsigned>
1151 case SystemZ::WFADB:
1152 return SystemZ::WFSDB;
1153 case SystemZ::WFASB:
1154 return SystemZ::WFSSB;
1155 case SystemZ::WFAXB:
1156 return SystemZ::WFSXB;
1157 case SystemZ::VFADB:
1158 return SystemZ::VFSDB;
1159 case SystemZ::VFASB:
1160 return SystemZ::VFSSB;
1162 case SystemZ::WFSDB:
1163 return SystemZ::WFADB;
1164 case SystemZ::WFSSB:
1165 return SystemZ::WFASB;
1166 case SystemZ::WFSXB:
1167 return SystemZ::WFAXB;
1168 case SystemZ::VFSDB:
1169 return SystemZ::VFADB;
1170 case SystemZ::VFSSB:
1171 return SystemZ::VFASB;
1173 return std::nullopt;
1185 unsigned Opcode =
MI.getOpcode();
1190 bool CCLiveAtMI =
true;
1195 CCLiveRange = &LIS->
getRegUnit(*CCUnits.begin());
1196 CCLiveAtMI = CCLiveRange->
liveAt(MISlot);
1199 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1200 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1201 isInt<8>(
MI.getOperand(2).getImm()) && !
MI.getOperand(3).getReg()) {
1204 MI.getDebugLoc(),
get(SystemZ::AGSI))
1207 .
addImm(
MI.getOperand(2).getImm());
1217 if (Ops.
size() != 1)
1220 unsigned OpNum = Ops[0];
1224 "Invalid size combination");
1226 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1227 isInt<8>(
MI.getOperand(2).getImm())) {
1229 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1231 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1234 .
addImm(
MI.getOperand(2).getImm());
1240 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1241 isInt<8>((int32_t)
MI.getOperand(2).getImm())) ||
1242 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1243 isInt<8>((int64_t)
MI.getOperand(2).getImm()))) {
1245 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1247 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1250 .
addImm((int8_t)
MI.getOperand(2).getImm());
1255 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1256 isInt<8>((int32_t)-
MI.getOperand(2).getImm())) ||
1257 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1258 isInt<8>((int64_t)-
MI.getOperand(2).getImm()))) {
1260 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1262 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1265 .
addImm((int8_t)-
MI.getOperand(2).getImm());
1270 unsigned MemImmOpc = 0;
1272 case SystemZ::LHIMux:
1273 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI;
break;
1274 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI;
break;
1275 case SystemZ::CHIMux:
1276 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI;
break;
1277 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI;
break;
1278 case SystemZ::CLFIMux:
1280 if (isUInt<16>(
MI.getOperand(1).getImm()))
1281 MemImmOpc = SystemZ::CLFHSI;
1283 case SystemZ::CLGFI:
1284 if (isUInt<16>(
MI.getOperand(1).getImm()))
1285 MemImmOpc = SystemZ::CLGHSI;
1290 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1294 .
addImm(
MI.getOperand(1).getImm());
1296 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1297 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1298 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1302 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1303 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1305 .
add(
MI.getOperand(1))
1313 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1314 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1316 .
add(
MI.getOperand(0))
1336 if (OpNum == 0 &&
MI.hasOneMemOperand()) {
1341 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1346 .
add(
MI.getOperand(1))
1352 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1354 .
add(
MI.getOperand(1))
1367 unsigned NumOps =
MI.getNumExplicitOperands();
1368 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1369 if (MemOpcode == -1 ||
1370 (CCLiveAtMI && !
MI.definesRegister(SystemZ::CC,
nullptr) &&
1371 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
1382 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1388 !(SystemZ::FP32BitRegClass.
contains(PhysReg) ||
1389 SystemZ::FP64BitRegClass.
contains(PhysReg) ||
1390 SystemZ::VF128BitRegClass.
contains(PhysReg)))
1395 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1396 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1400 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1405 bool NeedsCommute =
false;
1406 if ((
MI.getOpcode() == SystemZ::CR ||
MI.getOpcode() == SystemZ::CGR ||
1407 MI.getOpcode() == SystemZ::CLR ||
MI.getOpcode() == SystemZ::CLGR ||
1408 MI.getOpcode() == SystemZ::WFCDB ||
MI.getOpcode() == SystemZ::WFCSB ||
1409 MI.getOpcode() == SystemZ::WFKDB ||
MI.getOpcode() == SystemZ::WFKSB) &&
1411 NeedsCommute =
true;
1413 bool CCOperands =
false;
1414 if (
MI.getOpcode() == SystemZ::LOCRMux ||
MI.getOpcode() == SystemZ::LOCGR ||
1415 MI.getOpcode() == SystemZ::SELRMux ||
MI.getOpcode() == SystemZ::SELGR) {
1416 assert(
MI.getNumOperands() == 6 && NumOps == 5 &&
1417 "LOCR/SELR instruction operands corrupt?");
1432 Register SrcReg = (OpNum == 2 ?
MI.getOperand(1).getReg()
1433 : ((OpNum == 1 &&
MI.isCommutable())
1434 ?
MI.getOperand(2).getReg()
1436 if (DstPhys && !SystemZ::GRH32BitRegClass.
contains(DstPhys) && SrcReg &&
1438 NeedsCommute = (OpNum == 1);
1444 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1447 assert(AccessBytes != 0 &&
"Size of access should be known");
1448 assert(AccessBytes <=
Size &&
"Access outside the frame index");
1451 MI.getDebugLoc(),
get(MemOpcode));
1452 if (
MI.isCompare()) {
1453 assert(NumOps == 2 &&
"Expected 2 register operands for a compare.");
1454 MIB.
add(
MI.getOperand(NeedsCommute ? 1 : 0));
1456 else if (FusedFPOp) {
1457 MIB.
add(
MI.getOperand(0));
1458 MIB.
add(
MI.getOperand(3));
1459 MIB.
add(
MI.getOperand(OpNum == 1 ? 2 : 1));
1462 MIB.
add(
MI.getOperand(0));
1464 MIB.
add(
MI.getOperand(2));
1466 for (
unsigned I = 1;
I < OpNum; ++
I)
1467 MIB.
add(
MI.getOperand(
I));
1473 unsigned CCValid =
MI.getOperand(NumOps).getImm();
1474 unsigned CCMask =
MI.getOperand(NumOps + 1).getImm();
1476 MIB.
addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
1479 (!
MI.definesRegister(SystemZ::CC,
nullptr) ||
1480 MI.registerDefIsDead(SystemZ::CC,
nullptr))) {
1488 if (MO.isReg() && MO.getReg().isVirtual()) {
1490 if (
MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1491 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1492 else if (
MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1493 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1494 else if (
MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
1495 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
1520 unsigned LoadOpc = 0;
1521 unsigned RegMemOpcode = 0;
1523 RegMemOpcode =
MI.getOpcode() == SystemZ::WFADB ? SystemZ::ADB
1524 :
MI.getOpcode() == SystemZ::WFSDB ? SystemZ::SDB
1525 :
MI.getOpcode() == SystemZ::WFMDB ? SystemZ::MDB
1528 LoadOpc = SystemZ::VL64;
1529 FPRC = &SystemZ::FP64BitRegClass;
1531 RegMemOpcode =
MI.getOpcode() == SystemZ::WFASB ? SystemZ::AEB
1532 :
MI.getOpcode() == SystemZ::WFSSB ? SystemZ::SEB
1533 :
MI.getOpcode() == SystemZ::WFMSB ? SystemZ::MEEB
1536 LoadOpc = SystemZ::VL32;
1537 FPRC = &SystemZ::FP32BitRegClass;
1540 if (!RegMemOpcode || LoadMI.
getOpcode() != LoadOpc)
1544 if (
get(RegMemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)) {
1546 assert(LoadMI != InsertPt &&
"Assuming InsertPt not to be first in MBB.");
1549 if (MII->definesRegister(SystemZ::CC,
nullptr)) {
1550 if (!MII->registerDefIsDead(SystemZ::CC,
nullptr))
1563 if (Ops.
size() != 1 || FoldAsLoadDefReg !=
MI.getOperand(Ops[0]).getReg())
1569 if ((RegMemOpcode == SystemZ::SDB || RegMemOpcode == SystemZ::SEB) &&
1570 FoldAsLoadDefReg !=
RHS.getReg())
1577 BuildMI(*
MI.getParent(), InsertPt,
MI.getDebugLoc(),
get(RegMemOpcode), DstReg)
1583 MRI->setRegClass(DstReg, FPRC);
1591 switch (
MI.getOpcode()) {
1593 splitMove(
MI, SystemZ::LG);
1596 case SystemZ::ST128:
1597 splitMove(
MI, SystemZ::STG);
1601 splitMove(
MI, SystemZ::LD);
1605 splitMove(
MI, SystemZ::STD);
1608 case SystemZ::LBMux:
1609 expandRXYPseudo(
MI, SystemZ::LB, SystemZ::LBH);
1612 case SystemZ::LHMux:
1613 expandRXYPseudo(
MI, SystemZ::LH, SystemZ::LHH);
1616 case SystemZ::LLCRMux:
1617 expandZExtPseudo(
MI, SystemZ::LLCR, 8);
1620 case SystemZ::LLHRMux:
1621 expandZExtPseudo(
MI, SystemZ::LLHR, 16);
1624 case SystemZ::LLCMux:
1625 expandRXYPseudo(
MI, SystemZ::LLC, SystemZ::LLCH);
1628 case SystemZ::LLHMux:
1629 expandRXYPseudo(
MI, SystemZ::LLH, SystemZ::LLHH);
1633 expandRXYPseudo(
MI, SystemZ::L, SystemZ::LFH);
1636 case SystemZ::LOCMux:
1637 expandLOCPseudo(
MI, SystemZ::LOC, SystemZ::LOCFH);
1640 case SystemZ::LOCHIMux:
1641 expandLOCPseudo(
MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1644 case SystemZ::STCMux:
1645 expandRXYPseudo(
MI, SystemZ::STC, SystemZ::STCH);
1648 case SystemZ::STHMux:
1649 expandRXYPseudo(
MI, SystemZ::STH, SystemZ::STHH);
1652 case SystemZ::STMux:
1653 expandRXYPseudo(
MI, SystemZ::ST, SystemZ::STFH);
1656 case SystemZ::STOCMux:
1657 expandLOCPseudo(
MI, SystemZ::STOC, SystemZ::STOCFH);
1660 case SystemZ::LHIMux:
1661 expandRIPseudo(
MI, SystemZ::LHI, SystemZ::IIHF,
true);
1664 case SystemZ::IIFMux:
1665 expandRIPseudo(
MI, SystemZ::IILF, SystemZ::IIHF,
false);
1668 case SystemZ::IILMux:
1669 expandRIPseudo(
MI, SystemZ::IILL, SystemZ::IIHL,
false);
1672 case SystemZ::IIHMux:
1673 expandRIPseudo(
MI, SystemZ::IILH, SystemZ::IIHH,
false);
1676 case SystemZ::NIFMux:
1677 expandRIPseudo(
MI, SystemZ::NILF, SystemZ::NIHF,
false);
1680 case SystemZ::NILMux:
1681 expandRIPseudo(
MI, SystemZ::NILL, SystemZ::NIHL,
false);
1684 case SystemZ::NIHMux:
1685 expandRIPseudo(
MI, SystemZ::NILH, SystemZ::NIHH,
false);
1688 case SystemZ::OIFMux:
1689 expandRIPseudo(
MI, SystemZ::OILF, SystemZ::OIHF,
false);
1692 case SystemZ::OILMux:
1693 expandRIPseudo(
MI, SystemZ::OILL, SystemZ::OIHL,
false);
1696 case SystemZ::OIHMux:
1697 expandRIPseudo(
MI, SystemZ::OILH, SystemZ::OIHH,
false);
1700 case SystemZ::XIFMux:
1701 expandRIPseudo(
MI, SystemZ::XILF, SystemZ::XIHF,
false);
1704 case SystemZ::TMLMux:
1705 expandRIPseudo(
MI, SystemZ::TMLL, SystemZ::TMHL,
false);
1708 case SystemZ::TMHMux:
1709 expandRIPseudo(
MI, SystemZ::TMLH, SystemZ::TMHH,
false);
1712 case SystemZ::AHIMux:
1713 expandRIPseudo(
MI, SystemZ::AHI, SystemZ::AIH,
false);
1716 case SystemZ::AHIMuxK:
1717 expandRIEPseudo(
MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1720 case SystemZ::AFIMux:
1721 expandRIPseudo(
MI, SystemZ::AFI, SystemZ::AIH,
false);
1724 case SystemZ::CHIMux:
1725 expandRIPseudo(
MI, SystemZ::CHI, SystemZ::CIH,
false);
1728 case SystemZ::CFIMux:
1729 expandRIPseudo(
MI, SystemZ::CFI, SystemZ::CIH,
false);
1732 case SystemZ::CLFIMux:
1733 expandRIPseudo(
MI, SystemZ::CLFI, SystemZ::CLIH,
false);
1737 expandRXYPseudo(
MI, SystemZ::C, SystemZ::CHF);
1740 case SystemZ::CLMux:
1741 expandRXYPseudo(
MI, SystemZ::CL, SystemZ::CLHF);
1744 case SystemZ::RISBMux: {
1747 if (SrcIsHigh == DestIsHigh)
1748 MI.setDesc(
get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1750 MI.setDesc(
get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1751 MI.getOperand(5).setImm(
MI.getOperand(5).getImm() ^ 32);
1756 case SystemZ::ADJDYNALLOC:
1757 splitAdjDynAlloc(
MI);
1760 case TargetOpcode::LOAD_STACK_GUARD:
1761 expandLoadStackGuard(&
MI);
1770 if (
MI.isInlineAsm()) {
1772 const char *AsmStr =
MI.getOperand(0).getSymbolName();
1775 else if (
MI.getOpcode() == SystemZ::PATCHPOINT)
1777 else if (
MI.getOpcode() == SystemZ::STACKMAP)
1778 return MI.getOperand(1).getImm();
1779 else if (
MI.getOpcode() == SystemZ::FENTRY_CALL)
1782 return MI.getDesc().getSize();
1787 switch (
MI.getOpcode()) {
1798 MI.getOperand(1).getImm(), &
MI.getOperand(2));
1801 case SystemZ::BRCTH:
1805 case SystemZ::BRCTG:
1812 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1817 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1822 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1824 case SystemZ::CLGIJ:
1825 case SystemZ::CLGRJ:
1827 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1829 case SystemZ::INLINEASM_BR:
1839 unsigned &LoadOpcode,
1840 unsigned &StoreOpcode)
const {
1841 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1842 LoadOpcode = SystemZ::L;
1843 StoreOpcode = SystemZ::ST;
1844 }
else if (RC == &SystemZ::GRH32BitRegClass) {
1845 LoadOpcode = SystemZ::LFH;
1846 StoreOpcode = SystemZ::STFH;
1847 }
else if (RC == &SystemZ::GRX32BitRegClass) {
1848 LoadOpcode = SystemZ::LMux;
1849 StoreOpcode = SystemZ::STMux;
1850 }
else if (RC == &SystemZ::GR64BitRegClass ||
1851 RC == &SystemZ::ADDR64BitRegClass) {
1852 LoadOpcode = SystemZ::LG;
1853 StoreOpcode = SystemZ::STG;
1854 }
else if (RC == &SystemZ::GR128BitRegClass ||
1855 RC == &SystemZ::ADDR128BitRegClass) {
1856 LoadOpcode = SystemZ::L128;
1857 StoreOpcode = SystemZ::ST128;
1858 }
else if (RC == &SystemZ::FP32BitRegClass) {
1859 LoadOpcode = SystemZ::LE;
1860 StoreOpcode = SystemZ::STE;
1861 }
else if (RC == &SystemZ::FP64BitRegClass) {
1862 LoadOpcode = SystemZ::LD;
1863 StoreOpcode = SystemZ::STD;
1864 }
else if (RC == &SystemZ::FP128BitRegClass) {
1865 LoadOpcode = SystemZ::LX;
1866 StoreOpcode = SystemZ::STX;
1867 }
else if (RC == &SystemZ::VR32BitRegClass) {
1868 LoadOpcode = SystemZ::VL32;
1869 StoreOpcode = SystemZ::VST32;
1870 }
else if (RC == &SystemZ::VR64BitRegClass) {
1871 LoadOpcode = SystemZ::VL64;
1872 StoreOpcode = SystemZ::VST64;
1873 }
else if (RC == &SystemZ::VF128BitRegClass ||
1874 RC == &SystemZ::VR128BitRegClass) {
1875 LoadOpcode = SystemZ::VL;
1876 StoreOpcode = SystemZ::VST;
1886 if (isUInt<12>(
Offset) && isUInt<12>(Offset2)) {
1888 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1889 if (Disp12Opcode >= 0)
1890 return Disp12Opcode;
1896 if (isInt<20>(
Offset) && isInt<20>(Offset2)) {
1898 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1899 if (Disp20Opcode >= 0)
1900 return Disp20Opcode;
1907 if (
MI &&
MI->getOperand(0).isReg()) {
1912 return SystemZ::LEY;
1913 case SystemZ::VST32:
1914 return SystemZ::STEY;
1916 return SystemZ::LDY;
1917 case SystemZ::VST64:
1918 return SystemZ::STDY;
1930 return SystemZ::getDisp12Opcode(Opcode) >= 0;
1931 return SystemZ::getDisp20Opcode(Opcode) >= 0;
1936 case SystemZ::L:
return SystemZ::LT;
1937 case SystemZ::LY:
return SystemZ::LT;
1938 case SystemZ::LG:
return SystemZ::LTG;
1939 case SystemZ::LGF:
return SystemZ::LTGF;
1940 case SystemZ::LR:
return SystemZ::LTR;
1941 case SystemZ::LGFR:
return SystemZ::LTGFR;
1942 case SystemZ::LGR:
return SystemZ::LTGR;
1943 case SystemZ::LCDFR:
return SystemZ::LCDBR;
1944 case SystemZ::LPDFR:
return SystemZ::LPDBR;
1945 case SystemZ::LNDFR:
return SystemZ::LNDBR;
1946 case SystemZ::LCDFR_32:
return SystemZ::LCEBR;
1947 case SystemZ::LPDFR_32:
return SystemZ::LPEBR;
1948 case SystemZ::LNDFR_32:
return SystemZ::LNEBR;
1953 case SystemZ::RISBGN:
return SystemZ::RISBG;
1959 unsigned &Start,
unsigned &
End)
const {
1969 Start = 63 - (LSB +
Length - 1);
1977 assert(LSB > 0 &&
"Bottom bit must be set");
1978 assert(LSB +
Length < BitSize &&
"Top bit must be set");
1979 Start = 63 - (LSB - 1);
1993 if (!(
MI && isInt<8>(
MI->getOperand(1).getImm())))
1997 case SystemZ::CLGFI:
1998 if (!(
MI && isUInt<8>(
MI->getOperand(1).getImm())))
2003 if (!STI.hasMiscellaneousExtensions())
2005 if (!(
MI &&
MI->getOperand(3).getReg() == 0))
2013 return SystemZ::CRJ;
2015 return SystemZ::CGRJ;
2017 return SystemZ::CIJ;
2019 return SystemZ::CGIJ;
2021 return SystemZ::CLRJ;
2023 return SystemZ::CLGRJ;
2025 return SystemZ::CLIJ;
2026 case SystemZ::CLGFI:
2027 return SystemZ::CLGIJ;
2034 return SystemZ::CRBReturn;
2036 return SystemZ::CGRBReturn;
2038 return SystemZ::CIBReturn;
2040 return SystemZ::CGIBReturn;
2042 return SystemZ::CLRBReturn;
2044 return SystemZ::CLGRBReturn;
2046 return SystemZ::CLIBReturn;
2047 case SystemZ::CLGFI:
2048 return SystemZ::CLGIBReturn;
2055 return SystemZ::CRBCall;
2057 return SystemZ::CGRBCall;
2059 return SystemZ::CIBCall;
2061 return SystemZ::CGIBCall;
2063 return SystemZ::CLRBCall;
2065 return SystemZ::CLGRBCall;
2067 return SystemZ::CLIBCall;
2068 case SystemZ::CLGFI:
2069 return SystemZ::CLGIBCall;
2076 return SystemZ::CRT;
2078 return SystemZ::CGRT;
2080 return SystemZ::CIT;
2082 return SystemZ::CGIT;
2084 return SystemZ::CLRT;
2086 return SystemZ::CLGRT;
2088 return SystemZ::CLFIT;
2089 case SystemZ::CLGFI:
2090 return SystemZ::CLGIT;
2092 return SystemZ::CLT;
2094 return SystemZ::CLGT;
2105 MBBI->getOperand(1).isReg() && !
MBBI->mayLoad() &&
2106 "Not a compare reg/reg.");
2112 if (
MI.readsRegister(SystemZ::CC,
nullptr)) {
2113 unsigned Flags =
MI.getDesc().TSFlags;
2119 if (
MI.definesRegister(SystemZ::CC,
nullptr)) {
2133 unsigned Flags = CCUsers[
Idx]->getDesc().TSFlags;
2135 0 : CCUsers[
Idx]->getNumExplicitOperands() - 2);
2138 CCMaskMO.
setImm(NewCCMask);
2176 if (!STI.hasLoadAndTrap())
2181 return SystemZ::LAT;
2183 return SystemZ::LGAT;
2185 return SystemZ::LFHAT;
2187 return SystemZ::LLGFAT;
2189 return SystemZ::LLGTAT;
2198 unsigned Opcode = 0;
2199 if (isInt<16>(
Value))
2200 Opcode = SystemZ::LGHI;
2202 Opcode = SystemZ::LLILL;
2204 Opcode = SystemZ::LLILH;
2207 else if (isInt<32>(
Value))
2208 Opcode = SystemZ::LGFI;
2215 assert (
MRI.isSSA() &&
"Huge values only handled before reg-alloc .");
2216 Register Reg0 =
MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2217 Register Reg1 =
MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2228 for (
unsigned I = 0, E =
MI.getNumOperands();
I != E; ++
I) {
2239 ErrInfo =
"Addressing mode operands corrupt!";
2262 bool SameVal = (VALa && VALb && (VALa == VALb));
2266 if (PSVa && PSVb && (PSVa == PSVb))
2272 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2273 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2274 LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2276 LowOffset + (int)LowWidth.
getValue() <= HighOffset)
2285 int64_t &ImmVal)
const {
2287 if (
MI.getOpcode() == SystemZ::VGBM && Reg ==
MI.getOperand(0).getReg()) {
2288 ImmVal =
MI.getOperand(1).getImm();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI, MachineInstr::MIFlag Flag)
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
static LogicOp interpretAndImmediate(unsigned Opcode)
static uint64_t allOnes(unsigned int Count)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
This class represents an Operation in the Expression.
SlotIndexes * getSlotIndexes() const
VNInfo::Allocator & getVNInfoAllocator()
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
This class represents the liveness of a register, stack slot, etc.
bool liveAt(SlotIndex index) const
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
A set of register units used to track register liveness.
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
TypeSize getValue() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
This holds information about one operand of a machine instruction, indicating the register class for ...
uint8_t OperandType
Information about the type of the operand.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Wrapper class representing physical registers. Should be passed by value.
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
const MachineBasicBlock * getParent() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const
Returns true if the register is dead in this machine instruction.
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr fully defines the specified register.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
iterator_range< mop_iterator > operands()
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
const MachineOperand & getOperand(unsigned i) const
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
void setImm(int64_t immVal)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setIsDead(bool Val=true)
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
static MachineOperand CreateImm(int64_t Val)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
MI-level patchpoint operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
A SystemZ-specific class detailing special use registers particular for calling conventions.
virtual int getStackPointerBias()=0
virtual int getCallFrameSize()=0
unsigned getLoadAndTrap(unsigned Opcode) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
unsigned getLoadAndTest(unsigned Opcode) const
bool isPredicable(const MachineInstr &MI) const override
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset, const MachineInstr *MI=nullptr) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
SystemZInstrInfo(SystemZSubtarget &STI)
bool hasDisplacementPairInsn(unsigned Opcode) const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
bool expandPostRAPseudo(MachineInstr &MBBI) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
SystemZCallingConventionRegisters * getSpecialRegisters() const
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Undef
Value of the register doesn't matter.
static unsigned getAccessSize(unsigned int Flags)
unsigned getFirstReg(unsigned Reg)
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
int getTargetMemOpcode(uint16_t Opcode)
const unsigned CCMASK_CMP_GT
const unsigned CCMASK_ANY
static bool isImmLL(uint64_t Val)
static bool isImmLH(uint64_t Val)
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
unsigned reverseCCMask(unsigned CCMask)
const unsigned CCMASK_CMP_EQ
const unsigned CCMASK_ICMP
MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
const unsigned CCMASK_CMP_LT
const unsigned CCMASK_CMP_NE
bool isHighReg(unsigned int Reg)
const unsigned CCMASK_CMP_UO
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
constexpr size_t range_size(R &&Range)
Returns the size of the Range, i.e., the number of elements.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getUndefRegState(bool B)
@ And
Bitwise or logical AND of integers.
unsigned getKillRegState(bool B)