60#define CLEAR(v) ((v) = 0)
61#define SET0(v, n) ((v) &= ~((unsigned long)1 << (n)))
62#define SET1(v, n) ((v) |= (unsigned long)1 << (n))
63#define ISSET(v, n) (((v) & ((unsigned long)1 << (n))) != 0)
64#define ASSIGN(d, s) ((d) = (s))
65#define EQ(a, b) ((a) == (b))
66#define STATEVARS long dummy
67#define STATESETUP(m, n)
68#define STATETEARDOWN(m)
69#define SETUP(v) ((v) = 0)
71#define INIT(o, n) ((o) = (unsigned long)1 << (n))
72#define INC(o) ((o) = (unsigned long)(o) << 1)
73#define ISSTATEIN(v, o) (((v) & (o)) != 0)
76#define FWD(dst, src, n) ((dst) |= ((unsigned long)(src)&(here)) << (n))
77#define BACK(dst, src, n) ((dst) |= ((unsigned long)(src)&(here)) >> (n))
78#define ISSETBACK(v, n) (((v) & ((unsigned long)here >> (n))) != 0)
107#define CLEAR(v) memset(v, 0, m->g->nstates)
108#define SET0(v, n) ((v)[n] = 0)
109#define SET1(v, n) ((v)[n] = 1)
110#define ISSET(v, n) ((v)[n])
111#define ASSIGN(d, s) memmove(d, s, m->g->nstates)
112#define EQ(a, b) (memcmp(a, b, m->g->nstates) == 0)
113#define STATEVARS long vn; char *space
114#define STATESETUP(m, nv) { (m)->space = malloc((nv)*(m)->g->nstates); \
115 if ((m)->space == NULL) return(REG_ESPACE); \
117#define STATETEARDOWN(m) { free((m)->space); }
118#define SETUP(v) ((v) = &m->space[m->vn++ * m->g->nstates])
120#define INIT(o, n) ((o) = (n))
121#define INC(o) ((o)++)
122#define ISSTATEIN(v, o) ((v)[o])
125#define FWD(dst, src, n) ((dst)[here+(n)] |= (src)[here])
126#define BACK(dst, src, n) ((dst)[here-(n)] |= (src)[here])
127#define ISSETBACK(v, n) ((v)[here - (n)])
146# define GOODFLAGS(f) (f)
148# define GOODFLAGS(f) ((f)&(REG_NOTBOL|REG_NOTEOL|REG_STARTEND))
159 return(smatcher(
g,
string, nmatch, pmatch, eflags));
161 return(lmatcher(
g,
string, nmatch, pmatch, eflags));
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
INLINE void g(uint32_t *state, size_t a, size_t b, size_t c, size_t d, uint32_t x, uint32_t y)
int llvm_regexec(const llvm_regex_t *preg, const char *string, size_t nmatch, llvm_regmatch_t pmatch[], int eflags)