MachineCombinerPattern.h File Reference

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	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Enumerations
enum	llvm::MachineCombinerPattern {   llvm::MachineCombinerPattern::REASSOC_AX_BY, llvm::MachineCombinerPattern::REASSOC_AX_YB, llvm::MachineCombinerPattern::REASSOC_XA_BY, llvm::MachineCombinerPattern::REASSOC_XA_YB,   llvm::MachineCombinerPattern::REASSOC_XY_AMM_BMM, llvm::MachineCombinerPattern::REASSOC_XMM_AMM_BMM, llvm::MachineCombinerPattern::REASSOC_XY_BCA, llvm::MachineCombinerPattern::REASSOC_XY_BAC,   llvm::MachineCombinerPattern::MULADDW_OP1, llvm::MachineCombinerPattern::MULADDW_OP2, llvm::MachineCombinerPattern::MULSUBW_OP1, llvm::MachineCombinerPattern::MULSUBW_OP2,   llvm::MachineCombinerPattern::MULADDWI_OP1, llvm::MachineCombinerPattern::MULSUBWI_OP1, llvm::MachineCombinerPattern::MULADDX_OP1, llvm::MachineCombinerPattern::MULADDX_OP2,   llvm::MachineCombinerPattern::MULSUBX_OP1, llvm::MachineCombinerPattern::MULSUBX_OP2, llvm::MachineCombinerPattern::MULADDXI_OP1, llvm::MachineCombinerPattern::MULSUBXI_OP1,   llvm::MachineCombinerPattern::MULADDv8i8_OP1, llvm::MachineCombinerPattern::MULADDv8i8_OP2, llvm::MachineCombinerPattern::MULADDv16i8_OP1, llvm::MachineCombinerPattern::MULADDv16i8_OP2,   llvm::MachineCombinerPattern::MULADDv4i16_OP1, llvm::MachineCombinerPattern::MULADDv4i16_OP2, llvm::MachineCombinerPattern::MULADDv8i16_OP1, llvm::MachineCombinerPattern::MULADDv8i16_OP2,   llvm::MachineCombinerPattern::MULADDv2i32_OP1, llvm::MachineCombinerPattern::MULADDv2i32_OP2, llvm::MachineCombinerPattern::MULADDv4i32_OP1, llvm::MachineCombinerPattern::MULADDv4i32_OP2,   llvm::MachineCombinerPattern::MULSUBv8i8_OP1, llvm::MachineCombinerPattern::MULSUBv8i8_OP2, llvm::MachineCombinerPattern::MULSUBv16i8_OP1, llvm::MachineCombinerPattern::MULSUBv16i8_OP2,   llvm::MachineCombinerPattern::MULSUBv4i16_OP1, llvm::MachineCombinerPattern::MULSUBv4i16_OP2, llvm::MachineCombinerPattern::MULSUBv8i16_OP1, llvm::MachineCombinerPattern::MULSUBv8i16_OP2,   llvm::MachineCombinerPattern::MULSUBv2i32_OP1, llvm::MachineCombinerPattern::MULSUBv2i32_OP2, llvm::MachineCombinerPattern::MULSUBv4i32_OP1, llvm::MachineCombinerPattern::MULSUBv4i32_OP2,   llvm::MachineCombinerPattern::MULADDv4i16_indexed_OP1, llvm::MachineCombinerPattern::MULADDv4i16_indexed_OP2, llvm::MachineCombinerPattern::MULADDv8i16_indexed_OP1, llvm::MachineCombinerPattern::MULADDv8i16_indexed_OP2,   llvm::MachineCombinerPattern::MULADDv2i32_indexed_OP1, llvm::MachineCombinerPattern::MULADDv2i32_indexed_OP2, llvm::MachineCombinerPattern::MULADDv4i32_indexed_OP1, llvm::MachineCombinerPattern::MULADDv4i32_indexed_OP2,   llvm::MachineCombinerPattern::MULSUBv4i16_indexed_OP1, llvm::MachineCombinerPattern::MULSUBv4i16_indexed_OP2, llvm::MachineCombinerPattern::MULSUBv8i16_indexed_OP1, llvm::MachineCombinerPattern::MULSUBv8i16_indexed_OP2,   llvm::MachineCombinerPattern::MULSUBv2i32_indexed_OP1, llvm::MachineCombinerPattern::MULSUBv2i32_indexed_OP2, llvm::MachineCombinerPattern::MULSUBv4i32_indexed_OP1, llvm::MachineCombinerPattern::MULSUBv4i32_indexed_OP2,   llvm::MachineCombinerPattern::FMULADDH_OP1, llvm::MachineCombinerPattern::FMULADDH_OP2, llvm::MachineCombinerPattern::FMULSUBH_OP1, llvm::MachineCombinerPattern::FMULSUBH_OP2,   llvm::MachineCombinerPattern::FMULADDS_OP1, llvm::MachineCombinerPattern::FMULADDS_OP2, llvm::MachineCombinerPattern::FMULSUBS_OP1, llvm::MachineCombinerPattern::FMULSUBS_OP2,   llvm::MachineCombinerPattern::FMULADDD_OP1, llvm::MachineCombinerPattern::FMULADDD_OP2, llvm::MachineCombinerPattern::FMULSUBD_OP1, llvm::MachineCombinerPattern::FMULSUBD_OP2,   llvm::MachineCombinerPattern::FNMULSUBH_OP1, llvm::MachineCombinerPattern::FNMULSUBS_OP1, llvm::MachineCombinerPattern::FNMULSUBD_OP1, llvm::MachineCombinerPattern::FMLAv1i32_indexed_OP1,   llvm::MachineCombinerPattern::FMLAv1i32_indexed_OP2, llvm::MachineCombinerPattern::FMLAv1i64_indexed_OP1, llvm::MachineCombinerPattern::FMLAv1i64_indexed_OP2, llvm::MachineCombinerPattern::FMLAv4f16_OP1,   llvm::MachineCombinerPattern::FMLAv4f16_OP2, llvm::MachineCombinerPattern::FMLAv8f16_OP1, llvm::MachineCombinerPattern::FMLAv8f16_OP2, llvm::MachineCombinerPattern::FMLAv2f32_OP2,   llvm::MachineCombinerPattern::FMLAv2f32_OP1, llvm::MachineCombinerPattern::FMLAv2f64_OP1, llvm::MachineCombinerPattern::FMLAv2f64_OP2, llvm::MachineCombinerPattern::FMLAv4i16_indexed_OP1,   llvm::MachineCombinerPattern::FMLAv4i16_indexed_OP2, llvm::MachineCombinerPattern::FMLAv8i16_indexed_OP1, llvm::MachineCombinerPattern::FMLAv8i16_indexed_OP2, llvm::MachineCombinerPattern::FMLAv2i32_indexed_OP1,   llvm::MachineCombinerPattern::FMLAv2i32_indexed_OP2, llvm::MachineCombinerPattern::FMLAv2i64_indexed_OP1, llvm::MachineCombinerPattern::FMLAv2i64_indexed_OP2, llvm::MachineCombinerPattern::FMLAv4f32_OP1,   llvm::MachineCombinerPattern::FMLAv4f32_OP2, llvm::MachineCombinerPattern::FMLAv4i32_indexed_OP1, llvm::MachineCombinerPattern::FMLAv4i32_indexed_OP2, llvm::MachineCombinerPattern::FMLSv1i32_indexed_OP2,   llvm::MachineCombinerPattern::FMLSv1i64_indexed_OP2, llvm::MachineCombinerPattern::FMLSv4f16_OP1, llvm::MachineCombinerPattern::FMLSv4f16_OP2, llvm::MachineCombinerPattern::FMLSv8f16_OP1,   llvm::MachineCombinerPattern::FMLSv8f16_OP2, llvm::MachineCombinerPattern::FMLSv2f32_OP1, llvm::MachineCombinerPattern::FMLSv2f32_OP2, llvm::MachineCombinerPattern::FMLSv2f64_OP1,   llvm::MachineCombinerPattern::FMLSv2f64_OP2, llvm::MachineCombinerPattern::FMLSv4i16_indexed_OP1, llvm::MachineCombinerPattern::FMLSv4i16_indexed_OP2, llvm::MachineCombinerPattern::FMLSv8i16_indexed_OP1,   llvm::MachineCombinerPattern::FMLSv8i16_indexed_OP2, llvm::MachineCombinerPattern::FMLSv2i32_indexed_OP1, llvm::MachineCombinerPattern::FMLSv2i32_indexed_OP2, llvm::MachineCombinerPattern::FMLSv2i64_indexed_OP1,   llvm::MachineCombinerPattern::FMLSv2i64_indexed_OP2, llvm::MachineCombinerPattern::FMLSv4f32_OP1, llvm::MachineCombinerPattern::FMLSv4f32_OP2, llvm::MachineCombinerPattern::FMLSv4i32_indexed_OP1,   llvm::MachineCombinerPattern::FMLSv4i32_indexed_OP2, llvm::MachineCombinerPattern::FMULv2i32_indexed_OP1, llvm::MachineCombinerPattern::FMULv2i32_indexed_OP2, llvm::MachineCombinerPattern::FMULv2i64_indexed_OP1,   llvm::MachineCombinerPattern::FMULv2i64_indexed_OP2, llvm::MachineCombinerPattern::FMULv4i16_indexed_OP1, llvm::MachineCombinerPattern::FMULv4i16_indexed_OP2, llvm::MachineCombinerPattern::FMULv4i32_indexed_OP1,   llvm::MachineCombinerPattern::FMULv4i32_indexed_OP2, llvm::MachineCombinerPattern::FMULv8i16_indexed_OP1, llvm::MachineCombinerPattern::FMULv8i16_indexed_OP2 }
	These are instruction patterns matched by the machine combiner pass. More...