LLVM 18.0.0git
MachineCombinerPattern.h
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1//===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
2// combiner ------*- C++ -*-===//
3//
4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5// See https://llvm.org/LICENSE.txt for license information.
6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines instruction pattern supported by combiner
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
15#define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
16
17namespace llvm {
18
19/// These are instruction patterns matched by the machine combiner pass.
21 // These are commutative variants for reassociating a computation chain. See
22 // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
27
28 // These are patterns matched by the PowerPC to reassociate FMA chains.
31
32 // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
33 // reduce register pressure.
36
37 // These are patterns used to reduce the length of dependence chain.
40
41 // These are multiply-add patterns matched by the AArch64 machine combiner.
54 // NEON integers vectors
67
80
89
98
99 // Floating Point
161
172
173 // RISCV FMADD, FMSUB, FNMSUB patterns
174 FMADD_AX,
175 FMADD_XA,
176 FMSUB,
177 FNMSUB,
178
179 // X86 VNNI
180 DPWSSD,
181
182 FNMADD,
183};
184
185} // end namespace llvm
186
187#endif
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.