Here is a list of all variables with links to the files they belong to:

- e -

EarlyByValArgsCopy : NVPTXTargetMachine.cpp
EarlyCSEDebugHash : EarlyCSE.cpp
EarlyCSEMssaOptCap : EarlyCSE.cpp
EarlyInlineAll : AMDGPUTargetMachine.cpp
EarlyLiveIntervals : TargetPassConfig.cpp
EAXRetpolineName : X86IndirectThunks.cpp
ECXRetpolineName : X86IndirectThunks.cpp
EDIRetpolineName : X86IndirectThunks.cpp
EDXRetpolineName : X86IndirectThunks.cpp
EHAllowlist : WebAssemblyLowerEmscriptenEHSjLj.cpp
ELFAtSpecifiers : AArch64MCAsmInfo.cpp
elfAtSpecifiers : PPCMCAsmInfo.cpp
ElideAllZeroBranchWeights : ProfDataUtils.cpp
EliminateFramePointer : HexagonFrameLowering.cpp
Elimination : MachineCSE.cpp, DeadStoreElimination.cpp, TailRecursionElimination.cpp
else : PassBuilderBindings.cpp
EmbedBitcode : LTOBackend.cpp
EmbeddedData : MipsTargetObjectFile.cpp
EmitBBHash : AsmPrinter.cpp, TargetPassConfig.cpp
emitclausemarkers : R600EmitClauseMarkers.cpp
EmitDot : X86LoadValueInjectionLoadHardening.cpp
EmitDotOnly : X86LoadValueInjectionLoadHardening.cpp
EmitDotVerify : X86LoadValueInjectionLoadHardening.cpp
EmitFuncLineTableOffsetsOption : DwarfCompileUnit.cpp
EmitJalrReloc : MipsAsmParser.cpp, MipsABIInfo.cpp, MipsAsmPrinter.cpp, MipsFastISel.cpp, MipsISelLowering.cpp
EmitJtInText : HexagonTargetObjectFile.cpp
EmitJumpTables : HexagonISelLowering.cpp
EmitJumpTableSizesSection : AsmPrinter.cpp
EmitLookupTables : HexagonTargetTransformInfo.cpp
EmitLutInText : HexagonTargetObjectFile.cpp
Emitter : DXContainerGlobals.cpp
EmitTestAnnotations : MachinePipeliner.cpp
EmitX8AsFP : RISCVInstPrinter.cpp
EmptyHash : TypeHashing.cpp
EmptyOption : CommandLine.cpp
EmptyVI : LLParser.cpp
EmulateOldLDV : InstrRefBasedImpl.cpp
EnableAArch64CopyPropagation : AArch64TargetMachine.cpp
EnableAArch64ELFLocalDynamicTLSGeneration : AArch64ISelLowering.cpp, AArch64MCInstLower.cpp
EnableAASchedMI : ScheduleDAGInstrs.cpp
EnableAATrace : AliasAnalysis.cpp
EnableACCForwarding : HexagonInstrInfo.cpp
EnableAccReassociation : TargetInstrInfo.cpp
EnableAddiHeuristic : PPCMachineScheduler.cpp
EnableAddPhiTranslation : PHITransAddr.cpp
EnableAddressRebalancing : HexagonISelDAGToDAG.cpp
EnableAdvSIMDScalar : AArch64TargetMachine.cpp
EnableALUForwarding : HexagonInstrInfo.cpp
EnableAMDGPUAliasAnalysis : AMDGPUTargetMachine.cpp
EnableAMDGPUAttributor : AMDGPUTargetMachine.cpp
EnableAMDGPUFunctionCallsOpt : R600TargetMachine.cpp
EnableAndCmpSinking : CodeGenPrepare.cpp
EnableAntiDepBreaking : PostRASchedulerList.cpp
EnableARCOptimizations : ObjCARCAnalysisUtils.cpp
EnableARMLoadStoreOpt : ARMTargetMachine.cpp
EnableAtomicTidy : AArch64TargetMachine.cpp, ARMTargetMachine.cpp
EnableBasePointer : M68kRegisterInfo.cpp, PPCRegisterInfo.cpp, X86RegisterInfo.cpp
EnableBitSimplify : HexagonTargetMachine.cpp
EnableBlockPlacementStats : TargetPassConfig.cpp
EnableBranchCoalescing : PPCTargetMachine.cpp
EnableBranchHint : PPCISelDAGToDAG.cpp, X86MCInstLower.cpp
EnableBranchPrediction : HexagonInstrInfo.cpp
EnableBranchTargets : AArch64TargetMachine.cpp
EnableBSBSched : HexagonSubtarget.cpp
EnableCallSiteSpecific : Attributor.cpp
EnableCCMP : AArch64TargetMachine.cpp
EnableCExtOpt : HexagonTargetMachine.cpp
EnableChainCommoning : PPCLoopInstrFormPrep.cpp
EnableCheckBankConflict : HexagonSubtarget.cpp
EnableCmovConverter : X86CmovConversion.cpp
EnableCodeSinking : InstructionCombining.cpp
EnableColdCCStressTest : GlobalOpt.cpp
EnableColdSection : HotColdSplitting.cpp
EnableCollectLOH : AArch64TargetMachine.cpp
EnableCombineMGatherIntrinsics : AArch64ISelLowering.cpp
EnableCommGEP : HexagonTargetMachine.cpp
EnableCompressedInst : CSKYAsmParser.cpp
EnableCompressJumpTables : AArch64TargetMachine.cpp
EnableCondBrTuning : AArch64TargetMachine.cpp
EnableCondOpt : AArch64TargetMachine.cpp
EnableCondStoresVectorization : LoopVectorize.cpp
EnableConsecutiveMemOpOpt : AArch64PostLegalizerCombiner.cpp
EnableConstpoolPromotion : ARMISelLowering.cpp
EnableCopyHoist : HexagonTargetMachine.cpp
EnableCopyProp : FixupStatepointCallerSaved.cpp
EnableCountDownLoop : LoopPredication.cpp
EnableCSEInIRTranslator : IRTranslator.cpp
EnableCSEInLegalizer : Legalizer.cpp
EnableCyclicPath : MachineScheduler.cpp
Enabled : Statistic.cpp
EnableDCEInRA : AMDGPUTargetMachine.cpp
EnableDeadRegisterElimination : AArch64TargetMachine.cpp
EnableDependenceTest : DependenceAnalysis.cpp
EnableDevelopmentFeatures : MLRegAllocEvictAdvisor.cpp
EnableDiscriminateMemops : X86DiscriminateMemOps.cpp
EnableDotCurSched : HexagonSubtarget.cpp
EnableDPPCombine : AMDGPUTargetMachine.cpp
EnableEarlyExitVectorization : LoopVectorize.cpp
EnableEarlyIf : HexagonTargetMachine.cpp
EnableEarlyIfConversion : AArch64TargetMachine.cpp, AMDGPUTargetMachine.cpp
EnableEarlyIfConvert : AArch64Subtarget.cpp
EnableEpilogueVectorization : LoopVectorize.cpp
EnableExpandCondsets : HexagonTargetMachine.cpp
EnableExpensiveChecks : LegalizeTypes.cpp
EnableExtraTOCRegDeps : PPCTargetMachine.cpp
EnableExtToTBL : AArch64ISelLowering.cpp
EnableFalkorHWPFFix : AArch64TargetMachine.cpp
EnableFalkorHWPFUnrollFix : AArch64TargetTransformInfo.cpp
EnableFastISelAbort : SelectionDAGISel.cpp
EnableFastISelFallbackReport : SelectionDAGISel.cpp
EnableFastISelOption : TargetPassConfig.cpp
EnableFiniteLoopControl : ScalarEvolution.cpp
EnableFixedwidthAutovecInStreamingMode : AArch64TargetTransformInfo.cpp
EnableFMARegPressureReduction : PPCInstrInfo.cpp
EnableForwardingConflictDetection : LoopAccessAnalysis.cpp
EnableGenAllInsnClass : HexagonVLIWPacketizer.cpp
EnableGenExtract : HexagonTargetMachine.cpp
EnableGenInsert : HexagonTargetMachine.cpp
EnableGenMemAbs : HexagonTargetMachine.cpp
EnableGenMux : HexagonTargetMachine.cpp
EnableGenPred : HexagonTargetMachine.cpp
EnableGEPOffsetSplit : CodeGenPrepare.cpp
EnableGEPOpt : AArch64TargetMachine.cpp, PPCTargetMachine.cpp
EnableGISelBigEndian : ARMCallLowering.cpp
EnableGISelLoadStoreOptPostLegal : AArch64TargetMachine.cpp
EnableGISelLoadStoreOptPreLegal : AArch64TargetMachine.cpp
EnableGlobalCopies : RegisterCoalescer.cpp
EnableGlobalISelAbort : TargetPassConfig.cpp
EnableGlobalISelAtO : AArch64TargetMachine.cpp
EnableGlobalISelOption : TargetPassConfig.cpp
EnableGlobalMerge : GlobalMerge.cpp, AArch64TargetMachine.cpp, ARMTargetMachine.cpp, PPCTargetMachine.cpp, RISCVTargetMachine.cpp
EnableGlobalMergeFunc : TargetPassConfig.cpp
EnableGlobalMergeOnConst : GlobalMerge.cpp
EnableGlobalMergeOnExternal : GlobalMerge.cpp
EnableGPRToVecSpills : PPCRegisterInfo.cpp
EnableHeapToStack : Attributor.cpp
EnableHexagonBP : HexagonEarlyIfConv.cpp
EnableHexagonCabac : HexagonMCTargetDesc.cpp
EnableHexSDNodeSched : HexagonISelLowering.cpp
EnableHipStdPar : AMDGPUTargetMachine.cpp
EnableHistogramVectorization : LoopVectorizationLegality.cpp
EnableHomogeneousPrologEpilog : AArch64FrameLowering.cpp, AArch64TargetMachine.cpp
EnableHVX : HexagonMCTargetDesc.cpp
EnableHvxIeeeFp : HexagonMCTargetDesc.cpp
EnableICMP_EQToICMP_ST : CodeGenPrepare.cpp
EnableIfConversion : LoopVectorizationLegality.cpp
EnableImageIntrinsicOptimizer : AMDGPUTargetMachine.cpp
EnableImplicitNullChecks : TargetPassConfig.cpp
EnableIndVarRegisterHeur : LoopVectorize.cpp
EnableInitialCFGCleanup : HexagonTargetMachine.cpp
EnableInitializesImprovement : DeadStoreElimination.cpp
EnableInlineDeferral : InlineAdvisor.cpp
EnableInsertDelayAlu : AMDGPUTargetMachine.cpp
EnableInstSimplify : HexagonTargetMachine.cpp
EnableIntArgExtCheck : SystemZISelLowering.cpp
EnableInterleave : MVELaneInterleavingPass.cpp
EnableInterleavedMemAccesses : LoopVectorize.cpp
EnableIPRA : TargetPassConfig.cpp
EnableIVTruncation : LoopPredication.cpp
EnableJoining : RegisterCoalescer.cpp
EnableJoinSplits : RegisterCoalescer.cpp
EnableKernargPreload : AMDGPUPreloadKernelArguments.cpp
EnableLDV : LiveDebugVariables.cpp
EnableLibCallSimplify : AMDGPUTargetMachine.cpp
EnableLinkOnceODRIROutlining : IROutliner.cpp
EnableLinkOnceODROutlining : MachineOutliner.cpp
EnableLIRPWcslen : LoopIdiomRecognize.cpp
EnableLoadStoreOpt : AArch64TargetMachine.cpp
EnableLoadStoreRuntimeInterleave : LoopVectorize.cpp
EnableLoadStoreVectorizer : AMDGPUTargetMachine.cpp
EnableLocalReassignment : RegAllocEvictionAdvisor.cpp
EnableLoongArchDeadRegisterElimination : LoongArchTargetMachine.cpp
EnableLoopDataPrefetch : AArch64TargetMachine.cpp, LoongArchTargetMachine.cpp, RISCVTargetMachine.cpp
EnableLoopDistribute : LoopDistribute.cpp
EnableLoopIVHeuristic : SplitKit.cpp
EnableLoopPrefetch : AMDGPUTargetMachine.cpp, HexagonTargetMachine.cpp
EnableLoopResched : HexagonTargetMachine.cpp
EnableLowerKernelArguments : AMDGPUTargetMachine.cpp
EnableLowerModuleLDS : AMDGPUTargetMachine.cpp
EnableLSRCostOpt : AArch64TargetTransformInfo.cpp
EnableM0Merge : SIFixSGPRCopies.cpp
EnableMachineCombiner : RISCVTargetMachine.cpp
EnableMachineCombinerPass : PPCTargetMachine.cpp, SystemZTargetMachine.cpp, X86TargetMachine.cpp
EnableMachineFunctionSplitter : TargetPassConfig.cpp
EnableMachineOutliner : TargetPassConfig.cpp
EnableMachinePipeliner : AArch64TargetMachine.cpp, PPCSubtarget.cpp, RISCVTargetMachine.cpp
EnableMachineSched : MachineScheduler.cpp
EnableMacroFusion : MacroFusion.cpp
EnableMADWide : NVPTXISelDAGToDAG.cpp
EnableMaskedGatherScatters : ARMTargetTransformInfo.cpp, MVEGatherScatterLowering.cpp
EnableMaskedInterleavedMemAccesses : LoopVectorize.cpp
EnableMaskedLoadStores : ARMTargetTransformInfo.cpp
EnableMCR : AArch64TargetMachine.cpp
EnableMemAccessVersioning : LoopAccessAnalysis.cpp
EnableMemCpyDAGOpt : SelectionDAG.cpp
EnableMemCpyOptWithoutLibcalls : MemCpyOptimizer.cpp
EnableMemLocFragFill : AssignmentTrackingAnalysis.cpp
EnableMemOpCluster : MachineScheduler.cpp
EnableMemtransferTPLoop : ARMSelectionDAGInfo.cpp
EnableMergeBaseOffset : LoongArchTargetMachine.cpp
EnableMonotonicityCheck : DependenceAnalysis.cpp
EnableMulMulFix : MipsTargetMachine.cpp
EnableNewLegality : AMDGPULegalizerInfo.cpp
EnableNewSMEABILowering : AArch64TargetMachine.cpp
EnableNoAliasConversion : InlineFunction.cpp
EnableNonnullArgPropagation : FunctionAttrs.cpp
EnableNoTrapAfterNoreturn : CodeGenTargetMachineImpl.cpp
EnableOCLManglingMismatchWA : AMDGPULibFunc.cpp
EnableOptimizeLogicalImm : AArch64ISelLowering.cpp
EnableOrLikeSelectOpt : AArch64TargetTransformInfo.cpp
EnableParallelRegionMerging : OpenMPOpt.cpp
EnablePartialOverwriteTracking : DeadStoreElimination.cpp
EnablePartialStoreMerging : DeadStoreElimination.cpp
EnablePatchPointLiveness : StackMapLivenessAnalysis.cpp
EnablePCRelLinkerOpt : PPCPreEmitPeephole.cpp
EnablePeelingForIV : LoopPeel.cpp
EnablePEVectorSpills : PPCFrameLowering.cpp
EnablePGSO : MachineSizeOpts.cpp
EnablePhiElim : LoopStrengthReduce.cpp
EnablePhiOfOps : NewGVN.cpp
EnablePostLoadHardening : X86SpeculativeLoadHardening.cpp
EnablePostRAMachineSched : MachineScheduler.cpp
EnablePostRAScheduler : PostRASchedulerList.cpp
EnablePostSCCAdvisorPrinting : Inliner.cpp
EnablePostShrinkWrapOpt : ShrinkWrap.cpp
EnablePPCColdCC : PPCTargetTransformInfo.cpp
EnablePPCGenScalarMASSEntries : PPCTargetMachine.cpp
EnablePreallocateSGPRSpillVGPRs : SIPreAllocateWWMRegs.cpp
EnablePrecomputePhysRegs : LiveIntervals.cpp
EnablePredicatedCalls : HexagonSubtarget.cpp
EnablePrefetch : PPCTargetMachine.cpp
EnablePreLink : AMDGPULibCalls.cpp
EnablePreRAOptimizations : AMDGPUTargetMachine.cpp
EnablePromoteAnyextLoad : X86ISelDAGToDAG.cpp
EnablePromoteConstant : AArch64TargetMachine.cpp
EnablePromoteKernelArguments : AMDGPUTargetMachine.cpp
EnableR600IfConvert : R600TargetMachine.cpp
EnableR600StructurizeCFG : R600TargetMachine.cpp
EnableRDFOpt : HexagonTargetMachine.cpp
EnableRecPhiAnalysis : BasicAliasAnalysis.cpp
EnableReduceLoadOpStoreWidth : DAGCombiner.cpp
EnableRedundantCopyElimination : AArch64TargetMachine.cpp, RISCVTargetMachine.cpp
EnableReduxCost : TargetTransformInfo.cpp
EnableRedZone : AArch64FrameLowering.cpp
EnableRegPressure : MachineScheduler.cpp
EnableRegReassign : AMDGPUTargetMachine.cpp
EnableRemarksSection : RemarkStreamer.cpp
EnableRenaming : AArch64LoadStoreOptimizer.cpp
EnableRescheduling : TwoAddressInstructionPass.cpp
EnableRewritePartialRegUses : AMDGPUTargetMachine.cpp
EnableRISCVCopyPropagation : RISCVTargetMachine.cpp
EnableRISCVDeadRegisterElimination : RISCVTargetMachine.cpp
EnableRsqrtOpt : NVPTXISelDAGToDAG.cpp
EnableSaveRestoreLong : HexagonFrameLowering.cpp
EnableScalableAutovecInStreamingMode : AArch64TargetTransformInfo.cpp
EnableScalarIRPasses : AMDGPUTargetMachine.cpp
EnableSchedItins : ScheduleDAGInstrs.cpp
EnableSchedModel : ScheduleDAGInstrs.cpp
EnableScopedNoAlias : ScopedNoAliasAA.cpp
EnableSDWAPeephole : AMDGPUTargetMachine.cpp
EnableSelectionDAGSP : StackProtector.cpp
EnableSelectOpt : AArch64TargetMachine.cpp
EnableSeparateStorageAnalysis : BasicAliasAnalysis.cpp
EnableSetWavePriority : AMDGPUTargetMachine.cpp
EnableSExtElimination : PPCMIPeephole.cpp
EnableShrinkLoadReplaceStoreWithStore : DAGCombiner.cpp
EnableShrinkWrapOpt : ShrinkWrap.cpp
EnableShrinkWrapping : HexagonFrameLowering.cpp
EnableSIModeRegisterPass : AMDGPUTargetMachine.cpp
EnableSinkFold : AArch64TargetMachine.cpp, RISCVTargetMachine.cpp
EnableSMEPeepholeOpt : AArch64TargetMachine.cpp
EnableSpeculativeExecutionSideEffectSuppression : X86SpeculativeExecutionSideEffectSuppression.cpp
EnableSpeculativeLoadHardening : X86SpeculativeLoadHardening.cpp
EnableSpillageCopyElimination : MachineCopyPropagation.cpp
EnableSpillSGPRToVGPR : SIRegisterInfo.cpp
EnableSpillVGPRToAGPR : SIFrameLowering.cpp
EnableSSPCanaryBitInTB : PPCAsmPrinter.cpp
EnableStackOVFSanitizer : HexagonFrameLowering.cpp
EnableStaticAnalysis : HotColdSplitting.cpp
EnableStats : Statistic.cpp
EnableStoreMerging : DAGCombiner.cpp
EnableStoreRefinement : NewGVN.cpp
EnableStPairSuppress : AArch64TargetMachine.cpp
EnableSubRegLiveness : MachineRegisterInfo.cpp
EnableSubregLivenessTracking : AArch64Subtarget.cpp
EnableSVEGISel : AArch64ISelLowering.cpp, AArch64CallLowering.cpp
EnableSVEIntrinsicOpts : AArch64TargetMachine.cpp
EnableSwLowerLDS : AMDGPUTargetMachine.cpp
EnableSWP : MachinePipeliner.cpp
EnableSWPOptSize : MachinePipeliner.cpp
EnableSymbolicExecution : LoopDeletion.cpp
EnableSymbolizerMarkupEnv : Signals.cpp
EnableTailPredication : ARMTargetTransformInfo.cpp, MVETailPredication.cpp
EnableTBAA : TypeBasedAliasAnalysis.cpp
EnableTCLatencySched : HexagonSubtarget.cpp
EnableTermFolding : LoopSimplifyCFG.cpp
EnableTfrCleanup : HexagonTargetMachine.cpp
EnableTileRAPass : X86TargetMachine.cpp
EnableTimingClassLatency : HexagonInstrInfo.cpp
EnableTLSOpt : PPCISelDAGToDAG.cpp
EnableTrapOptimization : PPCMIPeephole.cpp
EnableTrapUnreachable : CodeGenTargetMachineImpl.cpp
EnableTypePromotionMerge : CodeGenPrepare.cpp
EnableUniformIntrinsicCombine : AMDGPUTargetMachine.cpp
EnableUnsafeFPShrink : SimplifyLibCalls.cpp
EnableUnsafeGlobalsModRefAliasResults : GlobalsModRef.cpp
EnableUpdateFormForNonConstInc : PPCLoopInstrFormPrep.cpp
EnableV68FloatAutoHVX : HexagonTargetTransformInfo.cpp
EnableVectorCombine : HexagonTargetMachine.cpp
EnableVectorPrint : HexagonTargetMachine.cpp
EnableVerboseRemarks : OpenMPOpt.cpp
EnableVExtractOpt : HexagonTargetMachine.cpp
EnableVGPRIndexMode : GCNSubtarget.cpp
EnableVOPD : AMDGPUTargetMachine.cpp
EnableVScaleImmediates : LoopStrengthReduce.cpp
EnableWideActiveLaneMask : VPlanTransforms.cpp
EnableZExtElimination : PPCMIPeephole.cpp
EncodingExpansionRegionBit : CoverageMappingReader.cpp
EnsureWholeVectorRegisterMoveValidVTYPE : RISCVInsertVSETVLI.cpp
EnumName : MCSectionMachO.cpp
EpilogHeaderWeights : LoopUnrollRuntime.cpp
EpilogueVectorizationForceVF : LoopVectorize.cpp
EpilogueVectorizationMinVF : LoopVectorize.cpp
EqValue : CommandLine.cpp
EraseGPOpnd : MipsOptimizePICCall.cpp
ErrorHandler : ErrorHandling.cpp
ErrorHandlerUserData : ErrorHandling.cpp
ErrorMissingParenthesis : HexagonAsmParser.cpp
ErrorNoncontigiousRegister : HexagonAsmParser.cpp
EvalAAMD : AliasAnalysisEvaluator.cpp
EVLTransformOverride : ExpandVectorPredication.cpp
evolution : ScalarEvolution.cpp
exceptions : DwarfEHPrepare.cpp, WasmEHPrepare.cpp
execution : SpeculativeExecution.cpp
executionMode : jitprofiling.c
ExhaustiveSearch : RegAllocGreedy.cpp
ExitBlockBias : MachineBlockPlacement.cpp
exits : UnifyLoopExits.cpp
ExpandConstantExprs : BitcodeReader.cpp
ExpandDivRemBits : ExpandLargeDivRem.cpp
ExpandFpConvertBits : ExpandFp.cpp
ExpandLimit : MLxExpansionPass.cpp
Expansion : DXILIntrinsicExpansion.cpp
ExpensiveAsserts : InstructionPrecedenceTracking.cpp
ExpensiveChecksEnabled : PostDominators.cpp, Dominators.cpp
ExperimentalCodeGen : MachinePipeliner.cpp
ExperimentalPrefInnermostLoopAlignment : X86ISelLowering.cpp
ExportSymFlagNames : EnumTables.cpp
ExportToDot : MemProfContextDisambiguation.cpp
ExtBinaryWriteVTableTypeProf : SampleProfWriter.cpp
ExtensionMap : AArch64AsmParser.cpp
ExtensionMaxWebSize : RISCVISelLowering.cpp
Extensions : SPIRVSubtarget.cpp
ExternSData : MipsTargetObjectFile.cpp
ExtFixups : HexagonMCCodeEmitter.cpp
extract : LoopExtractor.cpp
ExtractCutoff : HexagonGenExtract.cpp
ExtraOutliningPenalty : PartialInlining.cpp
ExtTspBlockPlacementMaxBlocks : MachineBlockPlacement.cpp