X86ISelLowering.cpp File Reference

#include "X86ISelLowering.h"
#include "MCTargetDesc/X86ShuffleDecode.h"
#include "X86.h"
#include "X86CallingConv.h"
#include "X86FrameLowering.h"
#include "X86InstrBuilder.h"
#include "X86IntrinsicsInfo.h"
#include "X86MachineFunctionInfo.h"
#include "X86TargetMachine.h"
#include "X86TargetObjectFile.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Analysis/BlockFrequencyInfo.h"
#include "llvm/Analysis/ObjCARCUtil.h"
#include "llvm/Analysis/ProfileSummaryInfo.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/EHPersonalities.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <bitset>
#include <cctype>
#include <numeric>

Go to the source code of this file.

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::X86
	Define some predicates that are used for node matching.

Macros
#define	DEBUG_TYPE   "x86-isel"
#define	NODE_NAME_CASE(NODE)   case X86ISD::NODE: return "X86ISD::" #NODE;
#define	GET_EGPR_IF_ENABLED(OPC)   (Subtarget.hasEGPR() ? OPC##_EVEX : OPC)

Enumerations
enum	BitTestKind : unsigned {   UndefBit , ConstantBit , NotConstantBit , ShiftBit ,   NotShiftBit }
enum	{ llvm::X86::MaxShuffleCombineDepth = 8 }
enum class	ShrinkMode { MULS8 , MULU8 , MULS16 , MULU16 }
	Different mul shrinking modes. More...

Functions
static bool	isLogicOp (unsigned Opcode)
static bool	isTargetShuffle (unsigned Opcode)
static bool	isTargetShuffleVariableMask (unsigned Opcode)
static bool	isX86CCSigned (unsigned X86CC)
	Return true if the condition is an signed comparison operation.
static X86::CondCode	TranslateIntegerX86CC (ISD::CondCode SetCCOpcode)
static X86::CondCode	TranslateX86CC (ISD::CondCode SetCCOpcode, const SDLoc &DL, bool isFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
	Do a one-to-one translation of a ISD::CondCode to the X86-specific condition code, returning the condition code and the LHS/RHS of the comparison to make.
static bool	hasFPCMov (unsigned X86CC)
	Is there a floating point cmov for the specific X86 condition code? Current x86 isa includes the following FP cmov instructions: fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
static bool	useVPTERNLOG (const X86Subtarget &Subtarget, MVT VT)
static bool	isUndefOrEqual (int Val, int CmpVal)
	Val is the undef sentinel value or equal to the specified value.
static bool	isUndefOrEqual (ArrayRef< int > Mask, int CmpVal)
	Return true if every element in Mask is the undef sentinel value or equal to the specified value.
static bool	isUndefOrEqualInRange (ArrayRef< int > Mask, int CmpVal, unsigned Pos, unsigned Size)
	Return true if every element in Mask, beginning from position Pos and ending in Pos+Size is the undef sentinel value or equal to the specified value.
static bool	isUndefOrZero (int Val)
	Val is either the undef or zero sentinel value.
static bool	isUndefInRange (ArrayRef< int > Mask, unsigned Pos, unsigned Size)
	Return true if every element in Mask, beginning from position Pos and ending in Pos+Size is the undef sentinel value.
static bool	isUndefLowerHalf (ArrayRef< int > Mask)
	Return true if the mask creates a vector whose lower half is undefined.
static bool	isUndefUpperHalf (ArrayRef< int > Mask)
	Return true if the mask creates a vector whose upper half is undefined.
static bool	isInRange (int Val, int Low, int Hi)
	Return true if Val falls within the specified range (L, H].
static bool	isAnyInRange (ArrayRef< int > Mask, int Low, int Hi)
	Return true if the value of any element in Mask falls within the specified range (L, H].
static bool	isAnyZero (ArrayRef< int > Mask)
	Return true if the value of any element in Mask is the zero sentinel value.
static bool	isUndefOrInRange (int Val, int Low, int Hi)
	Return true if Val is undef or if its value falls within the specified range (L, H].
static bool	isUndefOrInRange (ArrayRef< int > Mask, int Low, int Hi)
	Return true if every element in Mask is undef or if its value falls within the specified range (L, H].
static bool	isUndefOrZeroOrInRange (int Val, int Low, int Hi)
	Return true if Val is undef, zero or if its value falls within the specified range (L, H].
static bool	isUndefOrZeroOrInRange (ArrayRef< int > Mask, int Low, int Hi)
	Return true if every element in Mask is undef, zero or if its value falls within the specified range (L, H].
static LLVM_ATTRIBUTE_UNUSED bool	isBlendOrUndef (ArrayRef< int > Mask)
	Return true if every element in Mask, is an in-place blend/select mask or is undef.
static bool	isSequentialOrUndefInRange (ArrayRef< int > Mask, unsigned Pos, unsigned Size, int Low, int Step=1)
	Return true if every element in Mask, beginning from position Pos and ending in Pos + Size, falls within the specified sequence (Low, Low + Step, ..., Low + (Size - 1) * Step) or is undef.
static bool	isSequentialOrUndefOrZeroInRange (ArrayRef< int > Mask, unsigned Pos, unsigned Size, int Low, int Step=1)
	Return true if every element in Mask, beginning from position Pos and ending in Pos+Size, falls within the specified sequential range (Low, Low+Size], or is undef or is zero.
static bool	isUndefOrZeroInRange (ArrayRef< int > Mask, unsigned Pos, unsigned Size)
	Return true if every element in Mask, beginning from position Pos and ending in Pos+Size is undef or is zero.
static bool	isCompletePermute (ArrayRef< int > Mask)
	Return true if every element of a single input is referenced by the shuffle mask.
static bool	canWidenShuffleElements (ArrayRef< int > Mask, SmallVectorImpl< int > &WidenedMask)
	Helper function to test whether a shuffle mask could be simplified by widening the elements being shuffled.
static bool	canWidenShuffleElements (ArrayRef< int > Mask, const APInt &Zeroable, bool V2IsZero, SmallVectorImpl< int > &WidenedMask)
static bool	canWidenShuffleElements (ArrayRef< int > Mask)
static bool	scaleShuffleElements (ArrayRef< int > Mask, unsigned NumDstElts, SmallVectorImpl< int > &ScaledMask)
static bool	canScaleShuffleElements (ArrayRef< int > Mask, unsigned NumDstElts)
static SDValue	getConstVector (ArrayRef< int > Values, MVT VT, SelectionDAG &DAG, const SDLoc &dl, bool IsMask=false)
static SDValue	getConstVector (ArrayRef< APInt > Bits, const APInt &Undefs, MVT VT, SelectionDAG &DAG, const SDLoc &dl)
static SDValue	getConstVector (ArrayRef< APInt > Bits, MVT VT, SelectionDAG &DAG, const SDLoc &dl)
static SDValue	getZeroVector (MVT VT, const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl)
	Returns a vector of specified type with all zero elements.
static SDValue	getSplitVectorSrc (SDValue LHS, SDValue RHS, bool AllowCommute)
static SDValue	extractSubVector (SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, const SDLoc &dl, unsigned vectorWidth)
static SDValue	extract128BitVector (SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, const SDLoc &dl)
	Generate a DAG to grab 128-bits from a vector > 128 bits.
static SDValue	extract256BitVector (SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, const SDLoc &dl)
	Generate a DAG to grab 256-bits from a 512-bit vector.
static SDValue	insertSubVector (SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, const SDLoc &dl, unsigned vectorWidth)
static SDValue	insert128BitVector (SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, const SDLoc &dl)
	Generate a DAG to put 128-bits into a vector > 128 bits.
static SDValue	widenSubVector (MVT VT, SDValue Vec, bool ZeroNewElements, const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl)
	Widen a vector to a larger size with the same scalar type, with the new elements either zero or undef.
static SDValue	widenSubVector (SDValue Vec, bool ZeroNewElements, const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, unsigned WideSizeInBits)
	Widen a vector to a larger size with the same scalar type, with the new elements either zero or undef.
static MVT	widenMaskVectorType (MVT VT, const X86Subtarget &Subtarget)
	Widen a mask vector type to a minimum of v8i1/v16i1 to allow use of KSHIFT and bitcast with integer types.
static SDValue	widenMaskVector (SDValue Vec, bool ZeroNewElements, const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl)
	Widen a mask vector to a minimum of v8i1/v16i1 to allow use of KSHIFT and bitcast with integer types.
static bool	collectConcatOps (SDNode *N, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG)
static SDValue	isUpperSubvectorUndef (SDValue V, const SDLoc &DL, SelectionDAG &DAG)
static bool	isFreeToSplitVector (SDNode *N, SelectionDAG &DAG)
static std::pair< SDValue, SDValue >	splitVector (SDValue Op, SelectionDAG &DAG, const SDLoc &dl)
static SDValue	splitVectorOp (SDValue Op, SelectionDAG &DAG, const SDLoc &dl)
	Break an operation into 2 half sized ops and then concatenate the results.
static SDValue	splitVectorIntUnary (SDValue Op, SelectionDAG &DAG, const SDLoc &dl)
	Break an unary integer operation into 2 half sized ops and then concatenate the result back.
static SDValue	splitVectorIntBinary (SDValue Op, SelectionDAG &DAG, const SDLoc &dl)
	Break a binary integer operation into 2 half sized ops and then concatenate the result back.
template<typename F >
SDValue	SplitOpsAndApply (SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, F Builder, bool CheckBWI=true)
static SDValue	getAVX512Node (unsigned Opcode, const SDLoc &DL, MVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	insert1BitVector (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Insert i1-subvector to i1-vector.
static SDValue	concatSubVectors (SDValue V1, SDValue V2, SelectionDAG &DAG, const SDLoc &dl)
static SDValue	getOnesVector (EVT VT, SelectionDAG &DAG, const SDLoc &dl)
	Returns a vector of specified type with all bits set.
static SDValue	getEXTEND_VECTOR_INREG (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue In, SelectionDAG &DAG)
static SDValue	getBitSelect (const SDLoc &DL, MVT VT, SDValue LHS, SDValue RHS, SDValue Mask, SelectionDAG &DAG)
static SDValue	getVectorShuffle (SelectionDAG &DAG, EVT VT, const SDLoc &dl, SDValue V1, SDValue V2, ArrayRef< int > Mask)
static SDValue	getUnpackl (SelectionDAG &DAG, const SDLoc &dl, EVT VT, SDValue V1, SDValue V2)
	Returns a vector_shuffle node for an unpackl operation.
static SDValue	getUnpackh (SelectionDAG &DAG, const SDLoc &dl, EVT VT, SDValue V1, SDValue V2)
	Returns a vector_shuffle node for an unpackh operation.
static SDValue	getPack (SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl, MVT VT, SDValue LHS, SDValue RHS, bool PackHiHalf=false)
	Returns a node that packs the LHS + RHS nodes together at half width.
static SDValue	getShuffleVectorZeroOrUndef (SDValue V2, int Idx, bool IsZero, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Return a vector_shuffle of the specified vector of zero or undef vector.
static ConstantPoolSDNode *	getTargetConstantPoolFromBasePtr (SDValue Ptr)
static const Constant *	getTargetConstantFromBasePtr (SDValue Ptr)
static const Constant *	getTargetConstantFromNode (LoadSDNode *Load)
static const Constant *	getTargetConstantFromNode (SDValue Op)
static bool	getTargetConstantBitsFromNode (SDValue Op, unsigned EltSizeInBits, APInt &UndefElts, SmallVectorImpl< APInt > &EltBits, bool AllowWholeUndefs=true, bool AllowPartialUndefs=false)
bool	llvm::X86::isConstantSplat (SDValue Op, APInt &SplatVal, bool AllowPartialUndefs=true)
	If Op is a constant whose elements are all the same constant or undefined, return true and return the constant value in SplatVal.
static bool	getTargetShuffleMaskIndices (SDValue MaskNode, unsigned MaskEltSizeInBits, SmallVectorImpl< uint64_t > &RawMask, APInt &UndefElts)
static SDValue	IsNOT (SDValue V, SelectionDAG &DAG)
static void	createPackShuffleMask (MVT VT, SmallVectorImpl< int > &Mask, bool Unary, unsigned NumStages=1)
	Create a shuffle mask that matches the PACKSS/PACKUS truncation.
static void	getPackDemandedElts (EVT VT, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS)
static void	getHorizDemandedElts (EVT VT, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS)
static bool	getTargetShuffleMask (SDValue N, bool AllowSentinelZero, SmallVectorImpl< SDValue > &Ops, SmallVectorImpl< int > &Mask, bool &IsUnary)
	Calculates the shuffle mask corresponding to the target-specific opcode.
static bool	getTargetShuffleMask (SDValue N, bool AllowSentinelZero, SmallVectorImpl< SDValue > &Ops, SmallVectorImpl< int > &Mask)
static void	computeZeroableShuffleElements (ArrayRef< int > Mask, SDValue V1, SDValue V2, APInt &KnownUndef, APInt &KnownZero)
	Compute whether each element of a shuffle is zeroable.
static bool	getTargetShuffleAndZeroables (SDValue N, SmallVectorImpl< int > &Mask, SmallVectorImpl< SDValue > &Ops, APInt &KnownUndef, APInt &KnownZero)
	Decode a target shuffle mask and inputs and see if any values are known to be undef or zero from their inputs.
static void	resolveTargetShuffleFromZeroables (SmallVectorImpl< int > &Mask, const APInt &KnownUndef, const APInt &KnownZero, bool ResolveKnownZeros=true)
static void	resolveZeroablesFromTargetShuffle (const SmallVectorImpl< int > &Mask, APInt &KnownUndef, APInt &KnownZero)
static bool	createShuffleMaskFromVSELECT (SmallVectorImpl< int > &Mask, SDValue Cond, bool IsBLENDV=false)
static bool	getTargetShuffleInputs (SDValue Op, const APInt &DemandedElts, SmallVectorImpl< SDValue > &Inputs, SmallVectorImpl< int > &Mask, const SelectionDAG &DAG, unsigned Depth, bool ResolveKnownElts)
static bool	getFauxShuffleMask (SDValue N, const APInt &DemandedElts, SmallVectorImpl< int > &Mask, SmallVectorImpl< SDValue > &Ops, const SelectionDAG &DAG, unsigned Depth, bool ResolveKnownElts)
static void	resolveTargetShuffleInputsAndMask (SmallVectorImpl< SDValue > &Inputs, SmallVectorImpl< int > &Mask)
	Removes unused/repeated shuffle source inputs and adjusts the shuffle mask.
static bool	getTargetShuffleInputs (SDValue Op, const APInt &DemandedElts, SmallVectorImpl< SDValue > &Inputs, SmallVectorImpl< int > &Mask, APInt &KnownUndef, APInt &KnownZero, const SelectionDAG &DAG, unsigned Depth, bool ResolveKnownElts)
	Calls getTargetShuffleAndZeroables to resolve a target shuffle mask's inputs and then sets the SM_SentinelUndef and SM_SentinelZero values.
static bool	getTargetShuffleInputs (SDValue Op, SmallVectorImpl< SDValue > &Inputs, SmallVectorImpl< int > &Mask, const SelectionDAG &DAG, unsigned Depth=0, bool ResolveKnownElts=true)
static SDValue	getBROADCAST_LOAD (unsigned Opcode, const SDLoc &DL, EVT VT, EVT MemVT, MemSDNode *Mem, unsigned Offset, SelectionDAG &DAG)
static SDValue	getShuffleScalarElt (SDValue Op, unsigned Index, SelectionDAG &DAG, unsigned Depth)
	Returns the scalar element that will make up the i'th element of the result of the vector shuffle.
static SDValue	LowerBuildVectorAsInsert (SDValue Op, const SDLoc &DL, const APInt &NonZeroMask, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerBuildVectorv16i8 (SDValue Op, const SDLoc &DL, const APInt &NonZeroMask, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Custom lower build_vector of v16i8.
static SDValue	LowerBuildVectorv8i16 (SDValue Op, const SDLoc &DL, const APInt &NonZeroMask, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Custom lower build_vector of v8i16.
static SDValue	LowerBuildVectorv4x32 (SDValue Op, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Custom lower build_vector of v4i32 or v4f32.
static SDValue	getVShift (bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI, const SDLoc &dl)
	Return a vector logical shift node.
static SDValue	LowerAsSplatVectorLoad (SDValue SrcOp, MVT VT, const SDLoc &dl, SelectionDAG &DAG)
static bool	findEltLoadSrc (SDValue Elt, LoadSDNode *&Ld, int64_t &ByteOffset)
static SDValue	EltsFromConsecutiveLoads (EVT VT, ArrayRef< SDValue > Elts, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget, bool IsAfterLegalize)
	Given the initializing elements 'Elts' of a vector of type 'VT', see if the elements can be replaced by a single large load which has the same value as a build_vector or insert_subvector whose loaded operands are 'Elts'.
static SDValue	combineToConsecutiveLoads (EVT VT, SDValue Op, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget, bool IsAfterLegalize)
static Constant *	getConstantVector (MVT VT, ArrayRef< APInt > Bits, const APInt &Undefs, LLVMContext &C)
static Constant *	getConstantVector (MVT VT, const APInt &SplatValue, unsigned SplatBitSize, LLVMContext &C)
static bool	isFoldableUseOfShuffle (SDNode *N)
static SDValue	lowerBuildVectorAsBroadcast (BuildVectorSDNode *BVOp, const SDLoc &dl, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Attempt to use the vbroadcast instruction to generate a splat value from a splat BUILD_VECTOR which uses: a.
static int	getUnderlyingExtractedFromVec (SDValue &ExtractedFromVec, SDValue ExtIdx)
	For an EXTRACT_VECTOR_ELT with a constant index return the real underlying vector and index.
static SDValue	buildFromShuffleMostly (SDValue Op, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	LowerBUILD_VECTORvXbf16 (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerBUILD_VECTORvXi1 (SDValue Op, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static LLVM_ATTRIBUTE_UNUSED bool	isHorizOp (unsigned Opcode)
static bool	isHorizontalBinOpPart (const BuildVectorSDNode *N, unsigned Opcode, const SDLoc &DL, SelectionDAG &DAG, unsigned BaseIdx, unsigned LastIdx, SDValue &V0, SDValue &V1)
	This is a helper function of LowerToHorizontalOp().
static SDValue	ExpandHorizontalBinOp (const SDValue &V0, const SDValue &V1, const SDLoc &DL, SelectionDAG &DAG, unsigned X86Opcode, bool Mode, bool isUndefLO, bool isUndefHI)
	Emit a sequence of two 128-bit horizontal add/sub followed by a concat_vector.
static bool	isAddSubOrSubAdd (const BuildVectorSDNode *BV, const X86Subtarget &Subtarget, SelectionDAG &DAG, SDValue &Opnd0, SDValue &Opnd1, unsigned &NumExtracts, bool &IsSubAdd)
	Returns true iff BV builds a vector with the result equivalent to the result of ADDSUB/SUBADD operation.
static bool	isFMAddSubOrFMSubAdd (const X86Subtarget &Subtarget, SelectionDAG &DAG, SDValue &Opnd0, SDValue &Opnd1, SDValue &Opnd2, unsigned ExpectedUses)
	Returns true if is possible to fold MUL and an idiom that has already been recognized as ADDSUB/SUBADD(Opnd0, Opnd1) into FMADDSUB/FMSUBADD(x, y, Opnd1).
static SDValue	lowerToAddSubOrFMAddSub (const BuildVectorSDNode *BV, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to fold a build_vector that performs an 'addsub' or 'fmaddsub' or 'fsubadd' operation accordingly to X86ISD::ADDSUB or X86ISD::FMADDSUB or X86ISD::FMSUBADD node.
static bool	isHopBuildVector (const BuildVectorSDNode *BV, SelectionDAG &DAG, unsigned &HOpcode, SDValue &V0, SDValue &V1)
static SDValue	getHopForBuildVector (const BuildVectorSDNode *BV, const SDLoc &DL, SelectionDAG &DAG, unsigned HOpcode, SDValue V0, SDValue V1)
static SDValue	LowerToHorizontalOp (const BuildVectorSDNode *BV, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
static SDValue	LowerShift (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerBuildVectorToBitOp (BuildVectorSDNode *Op, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	If a BUILD_VECTOR's source elements all apply the same bit operation and one of their operands is constant, lower to a pair of BUILD_VECTOR and just apply the bit to the vectors.
static SDValue	materializeVectorConstant (SDValue Op, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Create a vector constant without a load.
static SDValue	createVariablePermute (MVT VT, SDValue SrcVec, SDValue IndicesVec, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Look for opportunities to create a VPERMV/VPERMILPV/PSHUFB variable permute from a vector of source values and a vector of extraction indices.
static SDValue	LowerBUILD_VECTORAsVariablePermute (SDValue V, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerAVXCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerCONCAT_VECTORSvXi1 (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerCONCAT_VECTORS (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static bool	isNoopShuffleMask (ArrayRef< int > Mask)
	Tiny helper function to identify a no-op mask.
static bool	isLaneCrossingShuffleMask (unsigned LaneSizeInBits, unsigned ScalarSizeInBits, ArrayRef< int > Mask)
	Test whether there are elements crossing LaneSizeInBits lanes in this shuffle mask.
static bool	is128BitLaneCrossingShuffleMask (MVT VT, ArrayRef< int > Mask)
	Test whether there are elements crossing 128-bit lanes in this shuffle mask.
static bool	isMultiLaneShuffleMask (unsigned LaneSizeInBits, unsigned ScalarSizeInBits, ArrayRef< int > Mask)
	Test whether elements in each LaneSizeInBits lane in this shuffle mask come from multiple lanes - this is different to isLaneCrossingShuffleMask to better support 'repeated mask + lane permute' style shuffles.
static bool	isRepeatedShuffleMask (unsigned LaneSizeInBits, MVT VT, ArrayRef< int > Mask, SmallVectorImpl< int > &RepeatedMask)
	Test whether a shuffle mask is equivalent within each sub-lane.
static bool	is128BitLaneRepeatedShuffleMask (MVT VT, ArrayRef< int > Mask, SmallVectorImpl< int > &RepeatedMask)
	Test whether a shuffle mask is equivalent within each 128-bit lane.
static bool	is128BitLaneRepeatedShuffleMask (MVT VT, ArrayRef< int > Mask)
static bool	is256BitLaneRepeatedShuffleMask (MVT VT, ArrayRef< int > Mask, SmallVectorImpl< int > &RepeatedMask)
	Test whether a shuffle mask is equivalent within each 256-bit lane.
static bool	isRepeatedTargetShuffleMask (unsigned LaneSizeInBits, unsigned EltSizeInBits, ArrayRef< int > Mask, SmallVectorImpl< int > &RepeatedMask)
	Test whether a target shuffle mask is equivalent within each sub-lane.
static bool	isRepeatedTargetShuffleMask (unsigned LaneSizeInBits, MVT VT, ArrayRef< int > Mask, SmallVectorImpl< int > &RepeatedMask)
	Test whether a target shuffle mask is equivalent within each sub-lane.
static bool	IsElementEquivalent (int MaskSize, SDValue Op, SDValue ExpectedOp, int Idx, int ExpectedIdx)
	Checks whether the vector elements referenced by two shuffle masks are equivalent.
static bool	isShuffleEquivalent (ArrayRef< int > Mask, ArrayRef< int > ExpectedMask, SDValue V1=SDValue(), SDValue V2=SDValue())
	Checks whether a shuffle mask is equivalent to an explicit list of arguments.
static bool	isTargetShuffleEquivalent (MVT VT, ArrayRef< int > Mask, ArrayRef< int > ExpectedMask, const SelectionDAG &DAG, SDValue V1=SDValue(), SDValue V2=SDValue())
	Checks whether a target shuffle mask is equivalent to an explicit pattern.
static bool	isUnpackWdShuffleMask (ArrayRef< int > Mask, MVT VT, const SelectionDAG &DAG)
static bool	is128BitUnpackShuffleMask (ArrayRef< int > Mask, const SelectionDAG &DAG)
static bool	hasIdenticalHalvesShuffleMask (ArrayRef< int > Mask)
	Return true if a shuffle mask chooses elements identically in its top and bottom halves.
static unsigned	getV4X86ShuffleImm (ArrayRef< int > Mask)
	Get a 4-lane 8-bit shuffle immediate for a mask.
static SDValue	getV4X86ShuffleImm8ForMask (ArrayRef< int > Mask, const SDLoc &DL, SelectionDAG &DAG)
static bool	isNonZeroElementsInOrder (const APInt &Zeroable, ArrayRef< int > Mask, const EVT &VectorType, bool &IsZeroSideLeft)
static SDValue	lowerShuffleWithPSHUFB (const SDLoc &DL, MVT VT, ArrayRef< int > Mask, SDValue V1, SDValue V2, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower a shuffle with a single PSHUFB of V1 or V2.
static SDValue	getMaskNode (SDValue Mask, MVT MaskVT, const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl)
	Return Mask with the necessary casting or extending for Mask according to MaskVT when lowering masking intrinsics.
static SDValue	lowerShuffleToEXPAND (const SDLoc &DL, MVT VT, const APInt &Zeroable, ArrayRef< int > Mask, SDValue &V1, SDValue &V2, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static bool	matchShuffleWithUNPCK (MVT VT, SDValue &V1, SDValue &V2, unsigned &UnpackOpcode, bool IsUnary, ArrayRef< int > TargetMask, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	lowerShuffleWithUNPCK (const SDLoc &DL, MVT VT, ArrayRef< int > Mask, SDValue V1, SDValue V2, SelectionDAG &DAG)
static SDValue	lowerShuffleWithUNPCK256 (const SDLoc &DL, MVT VT, ArrayRef< int > Mask, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Check if the mask can be mapped to a preliminary shuffle (vperm 64-bit) followed by unpack 256-bit.
static bool	matchShuffleAsVTRUNC (MVT &SrcVT, MVT &DstVT, MVT VT, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget)
static SDValue	getAVX512TruncNode (const SDLoc &DL, MVT DstVT, SDValue Src, const X86Subtarget &Subtarget, SelectionDAG &DAG, bool ZeroUppers)
static SDValue	lowerShuffleWithVPMOV (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerShuffleAsVTRUNC (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static int	canLowerByDroppingElements (ArrayRef< int > Mask, bool MatchEven, bool IsSingleInput)
	Check whether a compaction lowering can be done by dropping even/odd elements and compute how many times even/odd elements must be dropped.
static bool	matchShuffleWithPACK (MVT VT, MVT &SrcVT, SDValue &V1, SDValue &V2, unsigned &PackOpcode, ArrayRef< int > TargetMask, const SelectionDAG &DAG, const X86Subtarget &Subtarget, unsigned MaxStages=1)
static SDValue	lowerShuffleWithPACK (const SDLoc &DL, MVT VT, ArrayRef< int > Mask, SDValue V1, SDValue V2, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	lowerShuffleAsBitMask (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to emit a bitmask instruction for a shuffle.
static SDValue	lowerShuffleAsBitBlend (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG)
	Try to emit a blend instruction for a shuffle using bit math.
static SDValue	getVectorMaskingNode (SDValue Op, SDValue Mask, SDValue PreservedSrc, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Return (and Op, Mask) for compare instructions or (vselect Mask, Op, PreservedSrc) for others along with the necessary casting or extending for Mask when lowering masking intrinsics.
static bool	matchShuffleAsBlend (MVT VT, SDValue V1, SDValue V2, MutableArrayRef< int > Mask, const APInt &Zeroable, bool &ForceV1Zero, bool &ForceV2Zero, uint64_t &BlendMask)
static SDValue	lowerShuffleAsBlend (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Original, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to emit a blend instruction for a shuffle.
static SDValue	lowerShuffleAsBlendAndPermute (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG, bool ImmBlends=false)
	Try to lower as a blend of elements from two inputs followed by a single-input permutation.
static SDValue	lowerShuffleAsUNPCKAndPermute (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG)
	Try to lower as an unpack of elements from two inputs followed by a single-input permutation.
static SDValue	lowerShuffleAsPermuteAndUnpack (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower a shuffle as a permute of the inputs followed by an UNPCK instruction.
static SDValue	lowerShuffleAsByteRotateAndPermute (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Helper to form a PALIGNR-based rotate+permute, merging 2 inputs and then permuting the elements of the result in place.
static bool	isBroadcastShuffleMask (ArrayRef< int > Mask)
static bool	isNoopOrBroadcastShuffleMask (ArrayRef< int > Mask)
static bool	isSingleElementRepeatedMask (ArrayRef< int > Mask)
	Check if the Mask consists of the same element repeated multiple times.
static SDValue	lowerShuffleAsDecomposedShuffleMerge (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Generic routine to decompose a shuffle and blend into independent blends and permutes.
static int	matchShuffleAsBitRotate (MVT &RotateVT, int EltSizeInBits, const X86Subtarget &Subtarget, ArrayRef< int > Mask)
static SDValue	lowerShuffleAsBitRotate (const SDLoc &DL, MVT VT, SDValue V1, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Lower shuffle using X86ISD::VROTLI rotations.
static int	matchShuffleAsElementRotate (SDValue &V1, SDValue &V2, ArrayRef< int > Mask)
	Try to match a vector shuffle as an element rotation.
static int	matchShuffleAsByteRotate (MVT VT, SDValue &V1, SDValue &V2, ArrayRef< int > Mask)
	Try to lower a vector shuffle as a byte rotation.
static SDValue	lowerShuffleAsByteRotate (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerShuffleAsVALIGN (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower a vector shuffle as a dword/qword rotation.
static SDValue	lowerShuffleAsByteShiftMask (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower a vector shuffle as a byte shift sequence.
static int	matchShuffleAsShift (MVT &ShiftVT, unsigned &Opcode, unsigned ScalarSizeInBits, ArrayRef< int > Mask, int MaskOffset, const APInt &Zeroable, const X86Subtarget &Subtarget)
	Try to lower a vector shuffle as a bit shift (shifts in zeros).
static SDValue	lowerShuffleAsShift (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG, bool BitwiseOnly)
static bool	matchShuffleAsEXTRQ (MVT VT, SDValue &V1, SDValue &V2, ArrayRef< int > Mask, uint64_t &BitLen, uint64_t &BitIdx, const APInt &Zeroable)
static bool	matchShuffleAsINSERTQ (MVT VT, SDValue &V1, SDValue &V2, ArrayRef< int > Mask, uint64_t &BitLen, uint64_t &BitIdx)
static SDValue	lowerShuffleWithSSE4A (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, SelectionDAG &DAG)
	Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
static SDValue	lowerShuffleAsSpecificZeroOrAnyExtend (const SDLoc &DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Lower a vector shuffle as a zero or any extension.
static SDValue	lowerShuffleAsZeroOrAnyExtend (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower a vector shuffle as a zero extension on any microarch.
static SDValue	getScalarValueForVectorElement (SDValue V, int Idx, SelectionDAG &DAG)
	Try to get a scalar value for a specific element of a vector.
static bool	isShuffleFoldableLoad (SDValue V)
	Helper to test for a load that can be folded with x86 shuffles.
template<typename T >
static bool	isSoftF16 (T VT, const X86Subtarget &Subtarget)
static SDValue	lowerShuffleAsElementInsertion (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower insertion of a single element into a zero vector.
static SDValue	lowerShuffleAsTruncBroadcast (const SDLoc &DL, MVT VT, SDValue V0, int BroadcastIdx, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower broadcast of a single - truncated - integer element, coming from a scalar_to_vector/build_vector node V0 with larger elements.
static bool	isSingleSHUFPSMask (ArrayRef< int > Mask)
	Test whether this can be lowered with a single SHUFPS instruction.
static bool	isShuffleMaskInputInPlace (int Input, ArrayRef< int > Mask)
	Test whether the specified input (0 or 1) is in-place blended by the given mask.
static SDValue	lowerShuffleOfExtractsAsVperm (const SDLoc &DL, SDValue N0, SDValue N1, ArrayRef< int > Mask, SelectionDAG &DAG)
	If we are extracting two 128-bit halves of a vector and shuffling the result, match that to a 256-bit AVX2 vperm* instruction to avoid a multi-shuffle lowering.
static SDValue	lowerShuffleAsBroadcast (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower broadcast of a single element.
static bool	matchShuffleAsInsertPS (SDValue &V1, SDValue &V2, unsigned &InsertPSMask, const APInt &Zeroable, ArrayRef< int > Mask, SelectionDAG &DAG)
static SDValue	lowerShuffleAsInsertPS (const SDLoc &DL, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, SelectionDAG &DAG)
static SDValue	lowerV2F64Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 2-lane 64-bit floating point shuffles.
static SDValue	lowerV2I64Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 2-lane 64-bit integer shuffles.
static SDValue	lowerShuffleWithSHUFPS (const SDLoc &DL, MVT VT, ArrayRef< int > Mask, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower a vector shuffle using the SHUFPS instruction.
static SDValue	lowerV4F32Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Lower 4-lane 32-bit floating point shuffles.
static SDValue	lowerV4I32Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Lower 4-lane i32 vector shuffles.
static SDValue	lowerV8I16GeneralSingleInputShuffle (const SDLoc &DL, MVT VT, SDValue V, MutableArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Lowering of single-input v8i16 shuffles is the cornerstone of SSE2 shuffle lowering, and the most complex part.
static SDValue	lowerShuffleAsBlendOfPSHUFBs (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, SelectionDAG &DAG, bool &V1InUse, bool &V2InUse)
	Helper to form a PSHUFB-based shuffle+blend, opportunistically avoiding the blend if only one input is used.
static SDValue	lowerV8I16Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Generic lowering of 8-lane i16 shuffles.
static SDValue	lowerV8F16Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Lower 8-lane 16-bit floating point shuffles.
static SDValue	lowerShuffleWithPERMV (const SDLoc &DL, MVT VT, ArrayRef< int > Mask, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerV16I8Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Generic lowering of v16i8 shuffles.
static SDValue	lower128BitShuffle (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Dispatching routine to lower various 128-bit x86 vector shuffles.
static SDValue	splitAndLowerShuffle (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG, bool SimpleOnly)
	Generic routine to split vector shuffle into half-sized shuffles.
static SDValue	lowerShuffleAsSplitOrBlend (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Either split a vector in halves or decompose the shuffles and the blend/unpack.
static SDValue	lowerShuffleAsLanePermuteAndSHUFP (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG)
static SDValue	lowerShuffleAsLanePermuteAndPermute (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Lower a vector shuffle crossing multiple 128-bit lanes as a lane permutation followed by a per-lane permutation.
static void	computeInLaneShuffleMask (const ArrayRef< int > &Mask, int LaneSize, SmallVector< int > &InLaneMask)
	Helper to get compute inlane shuffle mask for a complete shuffle mask.
static SDValue	lowerShuffleAsLanePermuteAndShuffle (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Lower a vector shuffle crossing multiple 128-bit lanes by shuffling one source with a lane permutation.
static SDValue	lowerV2X128Shuffle (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering 2-lane 128-bit shuffles.
static SDValue	lowerShuffleAsLanePermuteAndRepeatedMask (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Lower a vector shuffle by first fixing the 128-bit lanes and then shuffling each lane.
static bool	getHalfShuffleMask (ArrayRef< int > Mask, MutableArrayRef< int > HalfMask, int &HalfIdx1, int &HalfIdx2)
	If the input shuffle mask results in a vector that is undefined in all upper or lower half elements and that mask accesses only 2 halves of the shuffle's operands, return true.
static SDValue	getShuffleHalfVectors (const SDLoc &DL, SDValue V1, SDValue V2, ArrayRef< int > HalfMask, int HalfIdx1, int HalfIdx2, bool UndefLower, SelectionDAG &DAG, bool UseConcat=false)
	Given the output values from getHalfShuffleMask(), create a half width shuffle of extracted vectors followed by an insert back to full width.
static SDValue	lowerShuffleWithUndefHalf (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Lower shuffles where an entire half of a 256 or 512-bit vector is UNDEF.
static SDValue	lowerShuffleAsRepeatedMaskAndLanePermute (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle case where shuffle sources are coming from the same 128-bit lane and every lane can be represented as the same repeating mask - allowing us to shuffle the sources with the repeating shuffle and then permute the result to the destination lanes.
static bool	matchShuffleWithSHUFPD (MVT VT, SDValue &V1, SDValue &V2, bool &ForceV1Zero, bool &ForceV2Zero, unsigned &ShuffleImm, ArrayRef< int > Mask, const APInt &Zeroable)
static SDValue	lowerShuffleWithSHUFPD (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerShuffleAsVTRUNCAndUnpack (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, const APInt &Zeroable, SelectionDAG &DAG)
static SDValue	lowerShufflePairAsUNPCKAndPermute (const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef< int > Mask, SelectionDAG &DAG)
static SDValue	lowerV4F64Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 4-lane 64-bit floating point shuffles.
static SDValue	lowerV4I64Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 4-lane 64-bit integer shuffles.
static SDValue	lowerV8F32Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 8-lane 32-bit floating point shuffles.
static SDValue	lowerV8I32Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 8-lane 32-bit integer shuffles.
static SDValue	lowerV16I16Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 16-lane 16-bit integer shuffles.
static SDValue	lowerV32I8Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 32-lane 8-bit integer shuffles.
static SDValue	lower256BitShuffle (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	High-level routine to lower various 256-bit x86 vector shuffles.
static SDValue	lowerV4X128Shuffle (const SDLoc &DL, MVT VT, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower a vector shuffle as a 128-bit shuffles.
static SDValue	lowerV8F64Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 8-lane 64-bit floating point shuffles.
static SDValue	lowerV16F32Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 16-lane 32-bit floating point shuffles.
static SDValue	lowerV8I64Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 8-lane 64-bit integer shuffles.
static SDValue	lowerV16I32Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 16-lane 32-bit integer shuffles.
static SDValue	lowerV32I16Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 32-lane 16-bit integer shuffles.
static SDValue	lowerV64I8Shuffle (const SDLoc &DL, ArrayRef< int > Mask, const APInt &Zeroable, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle lowering of 64-lane 8-bit integer shuffles.
static SDValue	lower512BitShuffle (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	High-level routine to lower various 512-bit x86 vector shuffles.
static SDValue	lower1BitShuffleAsKSHIFTR (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static int	match1BitShuffleAsKSHIFT (unsigned &Opcode, ArrayRef< int > Mask, int MaskOffset, const APInt &Zeroable)
static SDValue	lower1BitShuffle (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, const APInt &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static bool	canonicalizeShuffleMaskWithCommute (ArrayRef< int > Mask)
	Helper function that returns true if the shuffle mask should be commuted to improve canonicalization.
static bool	canCombineAsMaskOperation (SDValue V, const X86Subtarget &Subtarget)
static SDValue	canonicalizeShuffleMaskWithHorizOp (MutableArrayRef< SDValue > Ops, MutableArrayRef< int > Mask, unsigned RootSizeInBits, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	lowerVECTOR_SHUFFLE (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Top-level lowering for x86 vector shuffles.
static SDValue	lowerVSELECTtoVectorShuffle (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to lower a VSELECT instruction to a vector shuffle.
static SDValue	LowerEXTRACT_VECTOR_ELT_SSE4 (SDValue Op, SelectionDAG &DAG)
static SDValue	ExtractBitFromMaskVector (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Extract one bit from mask vector, like v16i1 or v8i1.
static APInt	getExtractedDemandedElts (SDNode *N)
static SDValue	InsertBitToMaskVector (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Insert one bit to mask vector, like v16i1 or v8i1.
static SDValue	LowerSCALAR_TO_VECTOR (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerINSERT_SUBVECTOR (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerEXTRACT_SUBVECTOR (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	GetTLSADDR (SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue *InGlue, const EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags, bool LocalDynamic=false)
static SDValue	LowerToTLSGeneralDynamicModel32 (GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT)
static SDValue	LowerToTLSGeneralDynamicModel64 (GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT)
static SDValue	LowerToTLSGeneralDynamicModelX32 (GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT)
static SDValue	LowerToTLSLocalDynamicModel (GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT, bool Is64Bit, bool Is64BitLP64)
static SDValue	LowerToTLSExecModel (GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT, TLSModel::Model model, bool is64Bit, bool isPIC)
static SDValue	LowerShiftParts (SDValue Op, SelectionDAG &DAG)
	Lower SRA_PARTS and friends, which return two i32 values and take a 2 x i32 value to shift plus a shift amount.
static SDValue	LowerI64IntToFP_AVX512DQ (SDValue Op, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerI64IntToFP16 (SDValue Op, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static bool	useVectorCast (unsigned Opcode, MVT FromVT, MVT ToVT, const X86Subtarget &Subtarget)
static SDValue	vectorizeExtractedCast (SDValue Cast, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Given a scalar cast operation that is extracted from a vector, try to vectorize the cast op followed by extraction.
static SDValue	lowerFPToIntToFP (SDValue CastToFP, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Given a scalar cast to FP with a cast to integer operand (almost an ftrunc), try to vectorize the cast ops.
static SDValue	lowerINT_TO_FP_vXi64 (SDValue Op, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	promoteXINT_TO_FP (SDValue Op, const SDLoc &dl, SelectionDAG &DAG)
static bool	isLegalConversion (MVT VT, bool IsSigned, const X86Subtarget &Subtarget)
static bool	shouldUseHorizontalOp (bool IsSingleSource, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Horizontal vector math instructions may be slower than normal math with shuffles.
static SDValue	LowerUINT_TO_FP_i64 (SDValue Op, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	64-bit unsigned integer to double expansion.
static SDValue	LowerUINT_TO_FP_i32 (SDValue Op, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	32-bit unsigned integer to float expansion.
static SDValue	lowerUINT_TO_FP_v2i32 (SDValue Op, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	lowerUINT_TO_FP_vXi32 (SDValue Op, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	lowerUINT_TO_FP_vec (SDValue Op, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerAVXExtend (SDValue Op, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	SplitAndExtendv16i1 (unsigned ExtOpc, MVT VT, SDValue In, const SDLoc &dl, SelectionDAG &DAG)
static SDValue	LowerZERO_EXTEND_Mask (SDValue Op, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerZERO_EXTEND (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	truncateVectorWithPACK (unsigned Opcode, EVT DstVT, SDValue In, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Helper to recursively truncate vector elements in half with PACKSS/PACKUS.
static SDValue	truncateVectorWithPACKUS (EVT DstVT, SDValue In, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Truncate using inreg zero extension (AND mask) and X86ISD::PACKUS.
static SDValue	truncateVectorWithPACKSS (EVT DstVT, SDValue In, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Truncate using inreg sign extension and X86ISD::PACKSS.
static SDValue	matchTruncateWithPACK (unsigned &PackOpcode, EVT DstVT, SDValue In, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Helper to determine if In truncated to DstVT has the necessary signbits / leading zero bits to be truncated with PACKSS / PACKUS, possibly by converting a SRL node to SRA for sign extension.
static SDValue	LowerTruncateVecPackWithSignBits (MVT DstVT, SDValue In, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	This function lowers a vector truncation of 'extended sign-bits' or 'extended zero-bits' values.
static SDValue	LowerTruncateVecPack (MVT DstVT, SDValue In, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	This function lowers a vector truncation from vXi32/vXi64 to vXi8/vXi16 into X86ISD::PACKUS/X86ISD::PACKSS operations.
static SDValue	LowerTruncateVecI1 (SDValue Op, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	expandFP_TO_UINT_SSE (MVT VT, SDValue Src, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerFP16_TO_FP (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFP_TO_FP16 (SDValue Op, SelectionDAG &DAG)
static SDValue	lowerAddSubToHorizontalOp (SDValue Op, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Depending on uarch and/or optimizing for size, we might prefer to use a vector operation in place of the typical scalar operation.
static SDValue	LowerFROUND (SDValue Op, SelectionDAG &DAG)
	ISD::FROUND is defined to round to nearest with ties rounding away from 0.
static SDValue	LowerFABSorFNEG (SDValue Op, SelectionDAG &DAG)
	The only differences between FABS and FNEG are the mask and the logic op.
static SDValue	LowerFCOPYSIGN (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFGETSIGN (SDValue Op, SelectionDAG &DAG)
static SDValue	getBT (SDValue Src, SDValue BitNo, const SDLoc &DL, SelectionDAG &DAG)
	Helper for attempting to create a X86ISD::BT node.
static SDValue	getSETCC (X86::CondCode Cond, SDValue EFLAGS, const SDLoc &dl, SelectionDAG &DAG)
	Helper for creating a X86ISD::SETCC node.
static bool	isOrXorXorTree (SDValue X, bool Root=true)
	Recursive helper for combineVectorSizedSetCCEquality() to see if we have a recognizable memcmp expansion.
template<typename F >
static SDValue	emitOrXorXorTree (SDValue X, const SDLoc &DL, SelectionDAG &DAG, EVT VecVT, EVT CmpVT, bool HasPT, F SToV)
	Recursive helper for combineVectorSizedSetCCEquality() to emit the memcmp expansion.
static SDValue	combineVectorSizedSetCCEquality (EVT VT, SDValue X, SDValue Y, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Try to map a 128-bit or larger integer comparison to vector instructions before type legalization splits it up into chunks.
static bool	matchScalarReduction (SDValue Op, ISD::NodeType BinOp, SmallVectorImpl< SDValue > &SrcOps, SmallVectorImpl< APInt > *SrcMask=nullptr)
	Helper for matching BINOP(EXTRACTELT(X,0),BINOP(EXTRACTELT(X,1),...)) style scalarized (associative) reduction patterns.
static SDValue	LowerVectorAllEqual (const SDLoc &DL, SDValue LHS, SDValue RHS, ISD::CondCode CC, const APInt &OriginalMask, const X86Subtarget &Subtarget, SelectionDAG &DAG, X86::CondCode &X86CC)
static SDValue	MatchVectorAllEqualTest (SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG, X86::CondCode &X86CC)
static bool	hasNonFlagsUse (SDValue Op)
	return true if Op has a use that doesn't just read flags.
static bool	isProfitableToUseFlagOp (SDValue Op)
static SDValue	EmitTest (SDValue Op, unsigned X86CC, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Emit nodes that will be selected as "test Op0,Op0", or something equivalent.
static SDValue	EmitCmp (SDValue Op0, SDValue Op1, unsigned X86CC, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Emit nodes that will be selected as "cmp Op0,Op1", or something equivalent.
static SDValue	LowerAndToBT (SDValue And, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG, X86::CondCode &X86CC)
	Result of 'and' is compared against zero.
static bool	cheapX86FSETCC_SSE (ISD::CondCode SetCCOpcode)
static unsigned	translateX86FSETCC (ISD::CondCode SetCCOpcode, SDValue &Op0, SDValue &Op1, bool &IsAlwaysSignaling)
	Turns an ISD::CondCode into a value suitable for SSE floating-point mask CMPs.
static SDValue	splitIntVSETCC (EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SelectionDAG &DAG, const SDLoc &dl)
	Break a VSETCC 256-bit integer VSETCC into two new 128 ones and then concatenate the result back.
static SDValue	LowerIntVSETCC_AVX512 (SDValue Op, const SDLoc &dl, SelectionDAG &DAG)
static SDValue	incDecVectorConstant (SDValue V, SelectionDAG &DAG, bool IsInc, bool NSW)
	Given a buildvector constant, return a new vector constant with each element incremented or decremented.
static SDValue	LowerVSETCCWithSUBUS (SDValue Op0, SDValue Op1, MVT VT, ISD::CondCode Cond, const SDLoc &dl, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	As another special case, use PSUBUS[BW] when it's profitable.
static SDValue	LowerVSETCC (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	EmitAVX512Test (SDValue Op0, SDValue Op1, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG, const X86Subtarget &Subtarget, SDValue &X86CC)
static std::pair< SDValue, SDValue >	getX86XALUOOp (X86::CondCode &Cond, SDValue Op, SelectionDAG &DAG)
static SDValue	LowerXALUO (SDValue Op, SelectionDAG &DAG)
static bool	isX86LogicalCmp (SDValue Op)
	Return true if opcode is a X86 logical comparison.
static bool	isTruncWithZeroHighBitsInput (SDValue V, SelectionDAG &DAG)
static SDValue	LowerSIGN_EXTEND_Mask (SDValue Op, const SDLoc &dl, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerANY_EXTEND (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerEXTEND_VECTOR_INREG (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerSIGN_EXTEND (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	splitVectorStore (StoreSDNode *Store, SelectionDAG &DAG)
	Change a vector store into a pair of half-size vector stores.
static SDValue	scalarizeVectorStore (StoreSDNode *Store, MVT StoreVT, SelectionDAG &DAG)
	Scalarize a vector store, bitcasting to TargetVT to determine the scalar type.
static SDValue	LowerStore (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerLoad (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static bool	isAndOrOfSetCCs (SDValue Op, unsigned &Opc)
	Return true if node is an ISD::AND or ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart from the AND / OR.
static SDValue	LowerVACOPY (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static unsigned	getTargetVShiftUniformOpcode (unsigned Opc, bool IsVariable)
static SDValue	getTargetVShiftByConstNode (unsigned Opc, const SDLoc &dl, MVT VT, SDValue SrcOp, uint64_t ShiftAmt, SelectionDAG &DAG)
	Handle vector element shifts where the shift amount is a constant.
static SDValue	getTargetVShiftNode (unsigned Opc, const SDLoc &dl, MVT VT, SDValue SrcOp, SDValue ShAmt, int ShAmtIdx, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Handle vector element shifts by a splat shift amount.
static SDValue	getScalarMaskingNode (SDValue Op, SDValue Mask, SDValue PreservedSrc, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Creates an SDNode for a predicated scalar operation.
static int	getSEHRegistrationNodeSize (const Function *Fn)
static SDValue	recoverFramePointer (SelectionDAG &DAG, const Function *Fn, SDValue EntryEBP)
	When the MSVC runtime transfers control to us, either to an outlined function or when returning to a parent frame after catching an exception, we recover the parent frame pointer by doing arithmetic on the incoming EBP.
static SDValue	getAVX2GatherNode (unsigned Opc, SDValue Op, SelectionDAG &DAG, SDValue Src, SDValue Mask, SDValue Base, SDValue Index, SDValue ScaleOp, SDValue Chain, const X86Subtarget &Subtarget)
static SDValue	getGatherNode (SDValue Op, SelectionDAG &DAG, SDValue Src, SDValue Mask, SDValue Base, SDValue Index, SDValue ScaleOp, SDValue Chain, const X86Subtarget &Subtarget)
static SDValue	getScatterNode (unsigned Opc, SDValue Op, SelectionDAG &DAG, SDValue Src, SDValue Mask, SDValue Base, SDValue Index, SDValue ScaleOp, SDValue Chain, const X86Subtarget &Subtarget)
static SDValue	getPrefetchNode (unsigned Opc, SDValue Op, SelectionDAG &DAG, SDValue Mask, SDValue Base, SDValue Index, SDValue ScaleOp, SDValue Chain, const X86Subtarget &Subtarget)
static SDValue	expandIntrinsicWChainHelper (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, unsigned TargetOpcode, unsigned SrcReg, const X86Subtarget &Subtarget, SmallVectorImpl< SDValue > &Results)
	Handles the lowering of builtin intrinsics with chain that return their value into registers EDX:EAX.
static void	getReadTimeStampCounter (SDNode *N, const SDLoc &DL, unsigned Opcode, SelectionDAG &DAG, const X86Subtarget &Subtarget, SmallVectorImpl< SDValue > &Results)
	Handles the lowering of builtin intrinsics that read the time stamp counter (x86_rdtsc and x86_rdtscp).
static SDValue	LowerREADCYCLECOUNTER (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	MarkEHRegistrationNode (SDValue Op, SelectionDAG &DAG)
static SDValue	MarkEHGuard (SDValue Op, SelectionDAG &DAG)
static SDValue	EmitTruncSStore (bool SignedSat, SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO, SelectionDAG &DAG)
	Emit Truncating Store with signed or unsigned saturation.
static SDValue	EmitMaskedTruncSStore (bool SignedSat, SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, SelectionDAG &DAG)
	Emit Masked Truncating Store with signed or unsigned saturation.
static SDValue	LowerINTRINSIC_W_CHAIN (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerADJUST_TRAMPOLINE (SDValue Op, SelectionDAG &DAG)
static SDValue	createSetFPEnvNodes (SDValue Ptr, SDValue Chain, const SDLoc &DL, EVT MemVT, MachineMemOperand *MMO, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerVectorCTLZ_AVX512CDI (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Lower a vector CTLZ using native supported vector CTLZ instruction.
static SDValue	LowerVectorCTLZInRegLUT (SDValue Op, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerVectorCTLZ (SDValue Op, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerCTLZ (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerCTTZ (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerAddSub (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerADDSAT_SUBSAT (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerABS (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerAVG (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerMINMAX (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerFMINIMUM_FMAXIMUM (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerABD (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerMUL (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowervXi8MulWithUNPCK (SDValue A, SDValue B, const SDLoc &dl, MVT VT, bool IsSigned, const X86Subtarget &Subtarget, SelectionDAG &DAG, SDValue *Low=nullptr)
static SDValue	LowerMULH (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerMULO (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
uint64_t	getGFNICtrlImm (unsigned Opcode, unsigned Amt=0)
SDValue	getGFNICtrlMask (unsigned Opcode, SelectionDAG &DAG, const SDLoc &DL, MVT VT, unsigned Amt=0)
static bool	supportedVectorShiftWithImm (EVT VT, const X86Subtarget &Subtarget, unsigned Opcode)
static bool	supportedVectorShiftWithBaseAmnt (EVT VT, const X86Subtarget &Subtarget, unsigned Opcode)
static bool	supportedVectorVarShift (EVT VT, const X86Subtarget &Subtarget, unsigned Opcode)
static SDValue	LowerShiftByScalarImmediate (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerShiftByScalarVariable (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	convertShiftLeftToScale (SDValue Amt, const SDLoc &dl, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerFunnelShift (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerRotate (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static std::pair< Value *, BitTestKind >	FindSingleBitChange (Value *V)
static bool	shouldExpandCmpArithRMWInIR (AtomicRMWInst *AI)
static SDValue	emitLockedStackOp (SelectionDAG &DAG, const X86Subtarget &Subtarget, SDValue Chain, const SDLoc &DL)
	Emit a locked operation on a stack location which does not change any memory location, but does involve a lock prefix.
static SDValue	LowerATOMIC_FENCE (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerCMP_SWAP (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	getPMOVMSKB (const SDLoc &DL, SDValue V, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerBITCAST (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerHorizontalByteSum (SDValue V, MVT VT, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Compute the horizontal sum of bytes in V for the elements of VT.
static SDValue	LowerVectorCTPOPInRegLUT (SDValue Op, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerVectorCTPOP (SDValue Op, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerCTPOP (SDValue N, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerBITREVERSE_XOP (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerBITREVERSE (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerPARITY (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	lowerAtomicArithWithLOCK (SDValue N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	lowerAtomicArith (SDValue N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Lower atomic_load_ops into LOCK-prefixed operations.
static SDValue	LowerATOMIC_STORE (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	LowerADDSUBO_CARRY (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFSINCOS (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	ExtendToType (SDValue InOp, MVT NVT, SelectionDAG &DAG, bool FillWithZeroes=false)
	Widen a vector input to a vector of NVT.
static SDValue	LowerMSCATTER (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerMLOAD (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerMSTORE (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerMGATHER (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue	LowerADDRSPACECAST (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerCVTPS2PH (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerPREFETCH (SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static StringRef	getInstrStrFromOpNo (const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo)
static SDValue	getFlagsOfCmpZeroFori1 (SelectionDAG &DAG, const SDLoc &DL, SDValue Mask)
static bool	isEFLAGSLiveAfter (MachineBasicBlock::iterator Itr, MachineBasicBlock *BB)
static MachineBasicBlock *	emitXBegin (MachineInstr &MI, MachineBasicBlock *MBB, const TargetInstrInfo *TII)
	Utility function to emit xbegin specifying the start of an RTM region.
static bool	checkAndUpdateEFLAGSKill (MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
static bool	isCMOVPseudo (MachineInstr &MI)
static MachineInstrBuilder	createPHIsForCMOVsInSinkBB (MachineBasicBlock::iterator MIItBegin, MachineBasicBlock::iterator MIItEnd, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB, MachineBasicBlock *SinkMBB)
static unsigned	getSUBriOpcode (bool IsLP64)
static unsigned	getOpcodeForIndirectThunk (unsigned RPOpc)
static const char *	getIndirectThunkSymbol (const X86Subtarget &Subtarget, unsigned Reg)
static void	computeKnownBitsForPSADBW (SDValue LHS, SDValue RHS, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth)
static void	computeKnownBitsForPMADDWD (SDValue LHS, SDValue RHS, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth)
static void	computeKnownBitsForPMADDUBSW (SDValue LHS, SDValue RHS, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth)
static KnownBits	computeKnownBitsForHorizontalOperation (const SDValue Op, const APInt &DemandedElts, unsigned Depth, const SelectionDAG &DAG, const function_ref< KnownBits(const KnownBits &, const KnownBits &)> KnownBitsFunc)
static SDValue	narrowLoadToVZLoad (LoadSDNode *LN, MVT MemVT, MVT VT, SelectionDAG &DAG)
static bool	matchUnaryShuffle (MVT MaskVT, ArrayRef< int > Mask, bool AllowFloatDomain, bool AllowIntDomain, SDValue V1, const SelectionDAG &DAG, const X86Subtarget &Subtarget, unsigned &Shuffle, MVT &SrcVT, MVT &DstVT)
static bool	matchUnaryPermuteShuffle (MVT MaskVT, ArrayRef< int > Mask, const APInt &Zeroable, bool AllowFloatDomain, bool AllowIntDomain, const SelectionDAG &DAG, const X86Subtarget &Subtarget, unsigned &Shuffle, MVT &ShuffleVT, unsigned &PermuteImm)
static bool	matchBinaryShuffle (MVT MaskVT, ArrayRef< int > Mask, bool AllowFloatDomain, bool AllowIntDomain, SDValue &V1, SDValue &V2, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget, unsigned &Shuffle, MVT &SrcVT, MVT &DstVT, bool IsUnary)
static bool	matchBinaryPermuteShuffle (MVT MaskVT, ArrayRef< int > Mask, const APInt &Zeroable, bool AllowFloatDomain, bool AllowIntDomain, SDValue &V1, SDValue &V2, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget, unsigned &Shuffle, MVT &ShuffleVT, unsigned &PermuteImm)
static SDValue	combineX86ShuffleChainWithExtract (ArrayRef< SDValue > Inputs, SDValue Root, ArrayRef< int > BaseMask, int Depth, bool HasVariableMask, bool AllowVariableCrossLaneMask, bool AllowVariablePerLaneMask, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineX86ShuffleChain (ArrayRef< SDValue > Inputs, SDValue Root, ArrayRef< int > BaseMask, int Depth, bool HasVariableMask, bool AllowVariableCrossLaneMask, bool AllowVariablePerLaneMask, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Combine an arbitrary chain of shuffles into a single instruction if possible.
static SDValue	combineX86ShufflesConstants (MVT VT, ArrayRef< SDValue > Ops, ArrayRef< int > Mask, bool HasVariableMask, SelectionDAG &DAG, const SDLoc &DL, const X86Subtarget &Subtarget)
static SDValue	combineX86ShufflesRecursively (ArrayRef< SDValue > SrcOps, int SrcOpIndex, SDValue Root, ArrayRef< int > RootMask, ArrayRef< const SDNode * > SrcNodes, unsigned Depth, unsigned MaxDepth, bool HasVariableMask, bool AllowVariableCrossLaneMask, bool AllowVariablePerLaneMask, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Fully generic combining of x86 shuffle instructions.
static SDValue	combineX86ShufflesRecursively (SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Helper entry wrapper to combineX86ShufflesRecursively.
static SmallVector< int, 4 >	getPSHUFShuffleMask (SDValue N)
	Get the PSHUF-style mask from PSHUF node.
static SDValue	combineRedundantDWordShuffle (SDValue N, MutableArrayRef< int > Mask, const SDLoc &DL, SelectionDAG &DAG)
	Search for a combinable shuffle across a chain ending in pshufd.
static SDValue	combineCommutableSHUFP (SDValue N, MVT VT, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	combineBlendOfPermutes (MVT VT, SDValue N0, SDValue N1, ArrayRef< int > BlendMask, const APInt &DemandedElts, SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &DL)
static bool	isUnaryOp (unsigned Opcode)
static SDValue	canonicalizeShuffleWithOp (SDValue N, SelectionDAG &DAG, const SDLoc &DL)
static SDValue	canonicalizeLaneShuffleWithRepeatedOps (SDValue V, SelectionDAG &DAG, const SDLoc &DL)
	Attempt to fold vpermf128(op(),op()) -> op(vpermf128(),vpermf128()).
static SDValue	combineTargetShuffle (SDValue N, const SDLoc &DL, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	Try to combine x86 target specific shuffles.
static bool	isAddSubOrSubAddMask (ArrayRef< int > Mask, bool &Op0Even)
	Checks if the shuffle mask takes subsequent elements alternately from two vectors.
static bool	isAddSubOrSubAdd (SDNode *N, const X86Subtarget &Subtarget, SelectionDAG &DAG, SDValue &Opnd0, SDValue &Opnd1, bool &IsSubAdd)
	Returns true iff the shuffle node N can be replaced with ADDSUB(SUBADD) operation.
static SDValue	combineShuffleToFMAddSub (SDNode *N, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Combine shuffle of two fma nodes into FMAddSub or FMSubAdd.
static SDValue	combineShuffleToAddSubOrFMAddSub (SDNode *N, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG)
	Try to combine a shuffle into a target-specific add-sub or mul-add-sub node.
static SDValue	combineShuffleOfConcatUndef (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	narrowShuffle (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
	If we have a shuffle of AVX/AVX512 (256/512 bit) vectors that only uses the low half of each source vector and does not set any high half elements in the destination vector, narrow the shuffle to half its original size.
static SDValue	combineShuffle (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static bool	checkBitcastSrcVectorSize (SDValue Src, unsigned Size, bool AllowTruncate)
static unsigned	getAltBitOpcode (unsigned Opcode)
static SDValue	adjustBitcastSrcVectorSSE1 (SelectionDAG &DAG, SDValue Src, const SDLoc &DL)
static SDValue	signExtendBitcastSrcVector (SelectionDAG &DAG, EVT SExtVT, SDValue Src, const SDLoc &DL)
static SDValue	combineBitcastvxi1 (SelectionDAG &DAG, EVT VT, SDValue Src, const SDLoc &DL, const X86Subtarget &Subtarget)
static SDValue	combinevXi1ConstantToInteger (SDValue Op, SelectionDAG &DAG)
static SDValue	combineCastedMaskArithmetic (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	createMMXBuildVector (BuildVectorSDNode *BV, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineBitcastToBoolVector (EVT VT, SDValue V, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget, unsigned Depth=0)
static SDValue	combineBitcast (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static bool	detectExtMul (SelectionDAG &DAG, const SDValue &Mul, SDValue &Op0, SDValue &Op1)
static bool	detectZextAbsDiff (const SDValue &Abs, SDValue &Op0, SDValue &Op1)
static SDValue	createVPDPBUSD (SelectionDAG &DAG, SDValue LHS, SDValue RHS, unsigned &LogBias, const SDLoc &DL, const X86Subtarget &Subtarget)
static SDValue	createPSADBW (SelectionDAG &DAG, const SDValue &Zext0, const SDValue &Zext1, const SDLoc &DL, const X86Subtarget &Subtarget)
static SDValue	combineMinMaxReduction (SDNode *Extract, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combinePredicateReduction (SDNode *Extract, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineVPDPBUSDPattern (SDNode *Extract, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineBasicSADPattern (SDNode *Extract, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineExtractFromVectorLoad (SDNode *N, EVT VecVT, SDValue SrcVec, uint64_t Idx, const SDLoc &dl, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineExtractWithShuffle (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	scalarizeExtEltFP (SDNode *ExtElt, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Extracting a scalar FP value from vector element 0 is free, so extract each operand first, then perform the math as a scalar op.
static SDValue	combineArithReduction (SDNode *ExtElt, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Try to convert a vector reduction sequence composed of binops and shuffles into horizontal ops.
static SDValue	combineExtractVectorElt (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	Detect vector gather/scatter index generation and convert it from being a bunch of shuffles and extracts into a somewhat faster sequence.
static SDValue	combineToExtendBoolVectorInReg (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N0, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineVSelectWithAllOnesOrZeros (SDNode *N, SelectionDAG &DAG, const SDLoc &DL, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	If a vector select has an operand that is -1 or 0, try to simplify the select to a bitwise logic operation.
static SDValue	narrowVectorSelect (SDNode *N, SelectionDAG &DAG, const SDLoc &DL, const X86Subtarget &Subtarget)
	If both arms of a vector select are concatenated vectors, split the select, and concatenate the result to eliminate a wide (256-bit) vector instruction: vselect Cond, (concat T0, T1), (concat F0, F1) --> concat (vselect (split Cond), T0, F0), (vselect (split Cond), T1, F1)
static SDValue	combineSelectOfTwoConstants (SDNode *N, SelectionDAG &DAG, const SDLoc &DL)
static SDValue	combineVSelectToBLENDV (SDNode *N, SelectionDAG &DAG, const SDLoc &DL, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	If this is a dynamic select (non-constant condition) and we can match this node with one of the variable blend instructions, restructure the condition so that blends can use the high (sign) bit of each element.
static SDValue	combineLogicBlendIntoConditionalNegate (EVT VT, SDValue Mask, SDValue X, SDValue Y, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	commuteSelect (SDNode *N, SelectionDAG &DAG, const SDLoc &DL, const X86Subtarget &Subtarget)
static SDValue	combineSelect (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	Do target-specific dag combines on SELECT and VSELECT nodes.
static SDValue	combineSetCCAtomicArith (SDValue Cmp, X86::CondCode &CC, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Combine: (brcond/cmov/setcc .., (cmp (atomic_load_add x, 1), 0), COND_S) to: (brcond/cmov/setcc .., (LADD x, 1), COND_LE) i.e., reusing the EFLAGS produced by the LOCKed instruction.
static SDValue	checkSignTestSetCCCombine (SDValue Cmp, X86::CondCode &CC, SelectionDAG &DAG)
static SDValue	checkBoolTestSetCCCombine (SDValue Cmp, X86::CondCode &CC)
static bool	checkBoolTestAndOrSetCCCombine (SDValue Cond, X86::CondCode &CC0, X86::CondCode &CC1, SDValue &Flags, bool &isAnd)
	Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
static SDValue	combineCarryThroughADD (SDValue EFLAGS, SelectionDAG &DAG)
static SDValue	combinePTESTCC (SDValue EFLAGS, X86::CondCode &CC, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	If we are inverting an PTEST/TESTP operand, attempt to adjust the CC to avoid the inversion.
static SDValue	combineSetCCMOVMSK (SDValue EFLAGS, X86::CondCode &CC, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineSetCCEFLAGS (SDValue EFLAGS, X86::CondCode &CC, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Optimize an EFLAGS definition used according to the condition code CC into a simpler EFLAGS value, potentially returning a new CC and replacing uses of chain values.
static SDValue	combineCMov (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL].
static bool	canReduceVMulWidth (SDNode *N, SelectionDAG &DAG, ShrinkMode &Mode)
static SDValue	reduceVMULWidth (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	When the operands of vector mul are extended from smaller size values, like i8 and i16, the type of mul may be shrinked to generate more efficient code.
static SDValue	combineMulSpecial (uint64_t MulAmt, SDNode *N, SelectionDAG &DAG, EVT VT, const SDLoc &DL)
static SDValue	combineMulToPMADDWD (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineMulToPMULDQ (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineMul (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineShiftToPMULH (SDNode *N, SelectionDAG &DAG, const SDLoc &DL, const X86Subtarget &Subtarget)
static SDValue	combineShiftLeft (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineShiftRightArithmetic (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineShiftRightLogical (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineHorizOpWithShuffle (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineVectorPack (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineVectorHADDSUB (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineVectorShiftVar (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineVectorShiftImm (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineVectorInsert (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineCompareEqual (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	Recognize the distinctive (AND (setcc ...) (setcc ..)) where both setccs reference the same FP CMP, and rewrite for CMPEQSS and friends.
static SDValue	combineAndNotIntoANDNP (SDNode *N, SelectionDAG &DAG)
	Try to fold: (and (xor X, -1), Y) -> (andnp X, Y).
static SDValue	combineAndShuffleNot (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Try to fold: and (vector_shuffle<Z,...,Z> (insert_vector_elt undef, (xor X, -1), Z), undef), Y -> andnp (vector_shuffle<Z,...,Z> (insert_vector_elt undef, X, Z), undef), Y.
static SDValue	PromoteMaskArithmetic (SDValue N, const SDLoc &DL, EVT VT, SelectionDAG &DAG, unsigned Depth)
static SDValue	PromoteMaskArithmetic (SDValue N, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static unsigned	convertIntLogicToFPLogicOpcode (unsigned Opcode)
static SDValue	convertIntLogicToFPLogic (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	If both input operands of a logic op are being cast from floating-point types or FP compares, try to convert this into a floating-point logic node to avoid unnecessary moves from SSE to integer registers.
static SDValue	combineBitOpWithMOVMSK (SDNode *N, SelectionDAG &DAG)
static SDValue	combineBitOpWithShift (SDNode *N, SelectionDAG &DAG)
static SDValue	combineBitOpWithPACK (SDNode *N, SelectionDAG &DAG)
static SDValue	combineAndMaskToShift (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	If this is a zero/all-bits result that is bitwise-anded with a low bits mask.
static SDValue	getIndexFromUnindexedLoad (LoadSDNode *Ld)
static bool	hasBZHI (const X86Subtarget &Subtarget, MVT VT)
static SDValue	combineAndLoadToBZHI (SDNode *Node, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineScalarAndWithMaskSetcc (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	getBMIMatchingOp (unsigned Opc, SelectionDAG &DAG, SDValue OpMustEq, SDValue Op, unsigned Depth)
static SDValue	combineBMILogicOp (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineX86SubCmpForFlags (SDNode *N, SDValue Flag, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &ST)
static SDValue	combineAndOrForCcmpCtest (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &ST)
static SDValue	combineAnd (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	canonicalizeBitSelect (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static bool	matchLogicBlend (SDNode *N, SDValue &X, SDValue &Y, SDValue &Mask)
static SDValue	combineLogicBlendIntoPBLENDV (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	lowerX86CmpEqZeroToCtlzSrl (SDValue Op, SelectionDAG &DAG)
static SDValue	combineOrCmpEqZeroToCtlzSrl (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	foldMaskedMergeImpl (SDValue And0_L, SDValue And0_R, SDValue And1_L, SDValue And1_R, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	foldMaskedMerge (SDNode *Node, SelectionDAG &DAG)
	Fold "masked merge" expressions like (m & x) | (~m & y) into the equivalent ((x ^ y) & m) ^ y) pattern.
static SDValue	combineAddOrSubToADCOrSBB (bool IsSub, const SDLoc &DL, EVT VT, SDValue X, SDValue Y, SelectionDAG &DAG, bool ZeroSecondOpOnly=false)
	If this is an add or subtract where one operand is produced by a cmp+setcc, then try to convert it to an ADC or SBB.
static SDValue	combineAddOrSubToADCOrSBB (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)
	If this is an add or subtract where one operand is produced by a cmp+setcc, then try to convert it to an ADC or SBB.
static SDValue	combineOrXorWithSETCC (SDNode *N, SDValue N0, SDValue N1, SelectionDAG &DAG)
static SDValue	combineOr (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	foldXorTruncShiftIntoCmp (SDNode *N, SelectionDAG &DAG)
	Try to turn tests against the signbit in the form of: XOR(TRUNCATE(SRL(X, size(X)-1)), 1) into: SETGT(X, -1)
static SDValue	foldVectorXorShiftIntoCmp (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: pcmpgt X, -1.
static SDValue	detectUSatPattern (SDValue In, EVT VT, SelectionDAG &DAG, const SDLoc &DL)
	Detect patterns of truncation with unsigned saturation:
static SDValue	detectSSatPattern (SDValue In, EVT VT, bool MatchPackUS=false)
	Detect patterns of truncation with signed saturation: (truncate (smin ((smax (x, signed_min_of_dest_type)), signed_max_of_dest_type)) to dest_type) or: (truncate (smax ((smin (x, signed_max_of_dest_type)), signed_min_of_dest_type)) to dest_type).
static SDValue	combineTruncateWithSat (SDValue In, EVT VT, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineConstantPoolLoads (SDNode *N, const SDLoc &dl, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineLoad (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static int	getOneTrueElt (SDValue V)
	If V is a build vector of boolean constants and exactly one of those constants is true, return the operand index of that true element.
static bool	getParamsForOneTrueMaskedElt (MaskedLoadStoreSDNode *MaskedOp, SelectionDAG &DAG, SDValue &Addr, SDValue &Index, Align &Alignment, unsigned &Offset)
	Given a masked memory load/store operation, return true if it has one mask bit set.
static SDValue	reduceMaskedLoadToScalarLoad (MaskedLoadSDNode *ML, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	If exactly one element of the mask is set for a non-extending masked load, it is a scalar load and vector insert.
static SDValue	combineMaskedLoadConstantMask (MaskedLoadSDNode *ML, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineMaskedLoad (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	reduceMaskedStoreToScalarStore (MaskedStoreSDNode *MS, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	If exactly one element of the mask is set for a non-truncating masked store, it is a vector extract and scalar store.
static SDValue	combineMaskedStore (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineStore (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineVEXTRACT_STORE (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static bool	isHorizontalBinOp (unsigned HOpcode, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG, const X86Subtarget &Subtarget, bool IsCommutative, SmallVectorImpl< int > &PostShuffleMask, bool ForceHorizOp)
	Return 'true' if this vector operation is "horizontal" and return the operands for the horizontal operation in LHS and RHS.
static SDValue	combineToHorizontalAddSub (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineFMulcFCMulc (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineFaddCFmul (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineFaddFsub (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Do target-specific dag combines on floating-point adds/subs.
static SDValue	combineLRINT_LLRINT (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineTruncatedArithmetic (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &DL)
	Attempt to pre-truncate inputs to arithmetic ops if it will simplify the codegen.
static SDValue	combinePMULH (SDValue Src, EVT VT, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	detectPMADDUBSW (SDValue In, EVT VT, SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &DL)
static SDValue	combineTruncate (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineVTRUNC (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	isFNEG (SelectionDAG &DAG, SDNode *N, unsigned Depth=0)
	Returns the negated value if the node N flips sign of FP value.
static unsigned	negateFMAOpcode (unsigned Opcode, bool NegMul, bool NegAcc, bool NegRes)
static SDValue	combineFneg (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	Do target-specific dag combines on floating point negations.
static SDValue	lowerX86FPLogicOp (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	foldXor1SetCC (SDNode *N, SelectionDAG &DAG)
	Fold a xor(setcc cond, val), 1 --> setcc (inverted(cond), val)
static SDValue	combineXorSubCTLZ (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineXor (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineBITREVERSE (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineAVG (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineBEXTR (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static bool	isNullFPScalarOrVectorConst (SDValue V)
static SDValue	getNullFPConstForNullVal (SDValue V, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	If a value is a scalar FP zero or a vector FP zero (potentially including undefined elements), return a zero constant that may be used to fold away that value.
static SDValue	combineFAndFNotToFAndn (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineFAnd (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Do target-specific dag combines on X86ISD::FAND nodes.
static SDValue	combineFAndn (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Do target-specific dag combines on X86ISD::FANDN nodes.
static SDValue	combineFOr (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
static SDValue	combineFMinFMax (SDNode *N, SelectionDAG &DAG)
	Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
static SDValue	combineFMinNumFMaxNum (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineX86INT_TO_FP (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineCVTP2I_CVTTP2I (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineAndnp (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	Do target-specific dag combines on X86ISD::ANDNP nodes.
static SDValue	combineBT (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineCVTPH2PS (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineSextInRegCmov (SDNode *N, SelectionDAG &DAG)
static SDValue	combineSignExtendInReg (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	promoteExtBeforeAdd (SDNode *Ext, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	sext(add_nsw(x, C)) --> add(sext(x), C_sext) zext(add_nuw(x, C)) --> add(zext(x), C_zext) Promoting a sign/zero extension ahead of a no overflow 'add' exposes opportunities to combine math ops, use an LEA, or use a complex addressing mode.
static SDValue	combineToExtendCMOV (SDNode *Extend, SelectionDAG &DAG)
static SDValue	combineExtSetcc (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineSext (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	getInvertedVectorForFMA (SDValue V, SelectionDAG &DAG)
static SDValue	combineFMA (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineFMADDSUB (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineZext (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	truncateAVX512SetCCNoBWI (EVT VT, EVT OpVT, SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	If we have AVX512, but not BWI and this is a vXi16/vXi8 setcc, just pre-promote its result type since vXi1 vectors don't get promoted during type legalization.
static SDValue	combineSetCC (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineMOVMSK (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineTESTP (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineX86GatherScatter (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	rebuildGatherScatter (MaskedGatherScatterSDNode *GorS, SDValue Index, SDValue Base, SDValue Scale, SelectionDAG &DAG)
static SDValue	combineGatherScatter (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineX86SetCC (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineBrCond (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	Optimize branch condition evaluation.
static SDValue	combineVectorCompareAndMaskUnaryOp (SDNode *N, SelectionDAG &DAG)
static SDValue	combineToFPTruncExtElt (SDNode *N, SelectionDAG &DAG)
	If we are converting a value to floating-point, try to replace scalar truncate of an extracted vector element with a bitcast.
static SDValue	combineUIntToFP (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineSIntToFP (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static bool	needCarryOrOverflowFlag (SDValue Flags)
static bool	onlyZeroFlagUsed (SDValue Flags)
static SDValue	combineCMP (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineX86AddSub (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &ST)
static SDValue	combineSBB (SDNode *N, SelectionDAG &DAG)
static SDValue	combineADC (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	matchPMADDWD (SelectionDAG &DAG, SDValue Op0, SDValue Op1, const SDLoc &DL, EVT VT, const X86Subtarget &Subtarget)
static SDValue	matchPMADDWD_2 (SelectionDAG &DAG, SDValue N0, SDValue N1, const SDLoc &DL, EVT VT, const X86Subtarget &Subtarget)
static SDValue	combineAddOfPMADDWD (SelectionDAG &DAG, SDValue N0, SDValue N1, const SDLoc &DL, EVT VT)
static SDValue	pushAddIntoCmovOfConsts (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget)
	CMOV of constants requires materializing constant operands in registers.
static SDValue	combineAdd (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineSubABS (SDNode *N, SelectionDAG &DAG)
static SDValue	combineSubSetcc (SDNode *N, SelectionDAG &DAG)
static SDValue	combineX86CloadCstore (SDNode *N, SelectionDAG &DAG)
static SDValue	combineSub (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineVectorCompare (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static std::optional< unsigned >	CastIntSETCCtoFP (MVT VT, ISD::CondCode CC, unsigned NumSignificantBitsLHS, unsigned NumSignificantBitsRHS)
static SDValue	combineConcatVectorOps (const SDLoc &DL, MVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
	Helper that combines an array of subvector ops as if they were the operands of a ISD::CONCAT_VECTORS node, but may have come from another source (e.g.
static SDValue	combineCONCAT_VECTORS (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineINSERT_SUBVECTOR (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	narrowExtractedVectorSelect (SDNode *Ext, const SDLoc &DL, SelectionDAG &DAG)
	If we are extracting a subvector of a vector select and the select condition is composed of concatenated vectors, try to narrow the select width.
static SDValue	combineEXTRACT_SUBVECTOR (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineScalarToVector (SDNode *N, SelectionDAG &DAG)
static SDValue	combinePMULDQ (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineVPMADD (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineEXTEND_VECTOR_INREG (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineKSHIFT (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineFP16_TO_FP (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineFP_EXTEND (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget)
static SDValue	combineBROADCAST_LOAD (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineFP_ROUND (SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget)
static SDValue	combineMOVDQ2Q (SDNode *N, SelectionDAG &DAG)
static SDValue	combinePDEP (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	FixupMMXIntrinsicTypes (SDNode *N, SelectionDAG &DAG)
static SDValue	combineINTRINSIC_WO_CHAIN (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineINTRINSIC_W_CHAIN (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineINTRINSIC_VOID (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
static bool	matchAsm (StringRef S, ArrayRef< const char * > Pieces)
static bool	clobbersFlagRegisters (const SmallVector< StringRef, 4 > &AsmPieces)
static X86::CondCode	parseConstraintCode (llvm::StringRef Constraint)
static bool	isGRClass (const TargetRegisterClass &RC)
	Check if RC is a general purpose register class.
static bool	isFRClass (const TargetRegisterClass &RC)
	Check if RC is a vector register class.
static bool	isVKClass (const TargetRegisterClass &RC)
	Check if RC is a mask register class.
static bool	useEGPRInlineAsm (const X86Subtarget &Subtarget)

Variables
static cl::opt< int >	ExperimentalPrefInnermostLoopAlignment ("x86-experimental-pref-innermost-loop-alignment", cl::init(4), cl::desc("Sets the preferable loop alignment for experiments (as log2 bytes) " "for innermost loops only. If specified, this option overrides " "alignment set by x86-experimental-pref-loop-alignment."), cl::Hidden)
static cl::opt< int >	BrMergingBaseCostThresh ("x86-br-merging-base-cost", cl::init(2), cl::desc("Sets the cost threshold for when multiple conditionals will be merged " "into one branch versus be split in multiple branches. Merging " "conditionals saves branches at the cost of additional instructions. " "This value sets the instruction cost limit, below which conditionals " "will be merged, and above which conditionals will be split. Set to -1 " "to never merge branches."), cl::Hidden)
static cl::opt< int >	BrMergingCcmpBias ("x86-br-merging-ccmp-bias", cl::init(6), cl::desc("Increases 'x86-br-merging-base-cost' in cases that the target " "supports conditional compare instructions."), cl::Hidden)
static cl::opt< int >	BrMergingLikelyBias ("x86-br-merging-likely-bias", cl::init(0), cl::desc("Increases 'x86-br-merging-base-cost' in cases that it is likely " "that all conditionals will be executed. For example for merging " "the conditionals (a == b && c > d), if its known that a == b is " "likely, then it is likely that if the conditionals are split " "both sides will be executed, so it may be desirable to increase " "the instruction cost threshold. Set to -1 to never merge likely " "branches."), cl::Hidden)
static cl::opt< int >	BrMergingUnlikelyBias ("x86-br-merging-unlikely-bias", cl::init(-1), cl::desc("Decreases 'x86-br-merging-base-cost' in cases that it is unlikely " "that all conditionals will be executed. For example for merging " "the conditionals (a == b && c > d), if its known that a == b is " "unlikely, then it is unlikely that if the conditionals are split " "both sides will be executed, so it may be desirable to decrease " "the instruction cost threshold. Set to -1 to never merge unlikely " "branches."), cl::Hidden)
static cl::opt< bool >	MulConstantOptimization ("mul-constant-optimization", cl::init(true), cl::desc("Replace 'mul x, Const' with more effective instructions like " "SHIFT, LEA, etc."), cl::Hidden)
const unsigned	X87StateSize = 28
const unsigned	FPStateSize = 32
const unsigned	FPStateSizeInBits = FPStateSize * 8

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "x86-isel"

Definition at line 71 of file X86ISelLowering.cpp.

GET_EGPR_IF_ENABLED

#define GET_EGPR_IF_ENABLED

(

OPC

)

(Subtarget.hasEGPR() ? OPC##_EVEX : OPC)

NODE_NAME_CASE

#define NODE_NAME_CASE

(

NODE

)

case X86ISD::NODE: return "X86ISD::" #NODE;

Enumeration Type Documentation

BitTestKind

enum BitTestKind : unsigned

Enumerator
UndefBit
ConstantBit
NotConstantBit
ShiftBit
NotShiftBit

Definition at line 30523 of file X86ISelLowering.cpp.

ShrinkMode

enum class ShrinkMode

strong

Different mul shrinking modes.

Enumerator
MULS8
MULU8
MULS16
MULU16

Definition at line 47526 of file X86ISelLowering.cpp.

Function Documentation

adjustBitcastSrcVectorSSE1()

static SDValue adjustBitcastSrcVectorSSE1 ( SelectionDAG &  DAG, SDValue  Src, const SDLoc &  DL  )

static

Definition at line 43442 of file X86ISelLowering.cpp.

References adjustBitcastSrcVectorSSE1(), llvm::ISD::AND, llvm::ISD::BITCAST, DL, getAltBitOpcode(), llvm::SelectionDAG::getBitcast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isNormalLoad(), llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETLT, and llvm::ISD::XOR.

Referenced by adjustBitcastSrcVectorSSE1(), and combineBitcastvxi1().

buildFromShuffleMostly()

static SDValue buildFromShuffleMostly ( SDValue  Op, const SDLoc &  DL, SelectionDAG &  DAG  )

static

Definition at line 7548 of file X86ISelLowering.cpp.

References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), getUnderlyingExtractedFromVec(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), Idx, llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), and llvm::ISD::UNDEF.

canCombineAsMaskOperation()

static bool canCombineAsMaskOperation ( SDValue  V, const X86Subtarget &  Subtarget  )

static

Definition at line 17552 of file X86ISelLowering.cpp.

References llvm::ISD::ABS, llvm::ISD::ADD, llvm::ISD::AND, llvm::X86Subtarget::hasAVX512(), llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::UMAX, llvm::ISD::UMIN, and llvm::ISD::XOR.

Referenced by commuteSelect(), and lowerVECTOR_SHUFFLE().

canLowerByDroppingElements()

static int canLowerByDroppingElements ( ArrayRef< int >  Mask, bool  MatchEven, bool  IsSingleInput  )

static

Check whether a compaction lowering can be done by dropping even/odd elements and compute how many times even/odd elements must be dropped.

This handles shuffles which take every Nth element where N is a power of two. Example shuffle masks:

(even) N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14 N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12 N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28 N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8 N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24

(odd) N = 1: 1, 3, 5, 7, 9, 11, 13, 15, 0, 2, 4, 6, 8, 10, 12, 14 N = 1: 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31

Any of these lanes can of course be undef.

This routine only supports N <= 3. FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here for larger N.

Returns

N above, or the number of times even/odd elements must be dropped if there is such a number. Otherwise returns zero.

Definition at line 10314 of file X86ISelLowering.cpp.

References assert(), llvm::isPowerOf2_32(), N, and llvm::Offset.

Referenced by lowerV16I8Shuffle(), and lowerV8I16Shuffle().

canonicalizeBitSelect()

static SDValue canonicalizeBitSelect ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 50153 of file X86ISelLowering.cpp.

References A, llvm::ISD::AND, llvm::X86ISD::ANDNP, assert(), B, llvm::CallingConv::C, DL, getAVX512Node(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), getTargetConstantBitsFromNode(), llvm::MVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::MVT::isVector(), N, llvm::ISD::OR, llvm::peekThroughBitcasts(), llvm::SmallVectorBase< Size_T >::size(), useVPTERNLOG(), llvm::X86ISD::VPTERNLOG, X, and Y.

Referenced by combineOr().

canonicalizeLaneShuffleWithRepeatedOps()

static SDValue canonicalizeLaneShuffleWithRepeatedOps ( SDValue  V, SelectionDAG &  DAG, const SDLoc &  DL  )

static

Attempt to fold vpermf128(op(),op()) -> op(vpermf128(),vpermf128()).

Definition at line 40665 of file X86ISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getBitcast(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::isUndef(), LHS, llvm::X86ISD::MOVDDUP, llvm::peekThroughBitcasts(), llvm::X86ISD::PSHUFD, RHS, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMILPI, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRAI, and llvm::X86ISD::VSRLI.

Referenced by combineTargetShuffle().

canonicalizeShuffleMaskWithCommute()

static bool canonicalizeShuffleMaskWithCommute ( ArrayRef< int >  Mask )

static

Helper function that returns true if the shuffle mask should be commuted to improve canonicalization.

Definition at line 17490 of file X86ISelLowering.cpp.

References assert(), and Size.

Referenced by combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), and lowerVECTOR_SHUFFLE().

canonicalizeShuffleMaskWithHorizOp()

static SDValue canonicalizeShuffleMaskWithHorizOp ( MutableArrayRef< SDValue >  Ops, MutableArrayRef< int >  Mask, unsigned  RootSizeInBits, const SDLoc &  DL, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 39394 of file X86ISelLowering.cpp.

References llvm::all_of(), llvm::any_of(), assert(), llvm::ShuffleVectorSDNode::commuteMask(), DL, llvm::ArrayRef< T >::empty(), extract128BitVector(), llvm::X86ISD::FHADD, llvm::X86ISD::FHSUB, llvm::SelectionDAG::getBitcast(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), getV4X86ShuffleImm8ForMask(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getZeroVector(), llvm::X86ISD::HADD, llvm::Hi, llvm::X86ISD::HSUB, isInRange(), llvm::SDNode::isOnlyUserOf(), isRepeatedTargetShuffleMask(), isUndefInRange(), isUndefOrZero(), isUndefOrZeroOrInRange(), LHS, llvm::Lo, llvm::M0(), llvm::M1(), llvm::X86ISD::PACKSS, llvm::X86ISD::PACKUS, llvm::peekThroughBitcasts(), llvm::peekThroughOneUseBitcasts(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), RHS, scaleShuffleElements(), shouldUseHorizontalOp(), llvm::X86ISD::SHUFP, llvm::ArrayRef< T >::size(), llvm::SmallVectorBase< Size_T >::size(), llvm::SM_SentinelUndef, llvm::SM_SentinelZero, std::swap(), and widenSubVector().

Referenced by combineX86ShufflesRecursively(), and lowerVECTOR_SHUFFLE().

canonicalizeShuffleWithOp()

static SDValue canonicalizeShuffleWithOp ( SDValue  N, SelectionDAG &  DAG, const SDLoc &  DL  )

static

Definition at line 40507 of file X86ISelLowering.cpp.

References llvm::X86ISD::BLENDI, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), getTargetConstantFromNode(), llvm::SelectionDAG::getTargetLoweringInfo(), getTargetShuffleMask(), llvm::SDValue::getValueType(), llvm::ISD::INSERT_SUBVECTOR, llvm::X86ISD::INSERTPS, llvm::TargetLoweringBase::isBinOp(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), isLogicOp(), isShuffleFoldableLoad(), llvm::SelectionDAG::isSplatValue(), isTargetShuffle(), isUnaryOp(), LHS, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSS, N, llvm::peekThroughOneUseBitcasts(), llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, RHS, llvm::X86ISD::SHUFP, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VBROADCAST, llvm::X86ISD::VPERMI, and llvm::X86ISD::VPERMILPI.

Referenced by combineShuffle().

canReduceVMulWidth()

static bool canReduceVMulWidth ( SDNode *  N, SelectionDAG &  DAG, ShrinkMode &  Mode  )

static

Definition at line 47528 of file X86ISelLowering.cpp.

References assert(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::EVT::getScalarSizeInBits(), N, and llvm::SelectionDAG::SignBitIsZero().

Referenced by matchPMADDWD(), and reduceVMULWidth().

canScaleShuffleElements()

static bool canScaleShuffleElements ( ArrayRef< int >  Mask, unsigned  NumDstElts  )

static

Definition at line 3775 of file X86ISelLowering.cpp.

References scaleShuffleElements().

Referenced by combineBlendOfPermutes(), and combineSetCCMOVMSK().

canWidenShuffleElements() [1/3]

static bool canWidenShuffleElements ( ArrayRef< int >  Mask )

static

Definition at line 3740 of file X86ISelLowering.cpp.

References canWidenShuffleElements().

canWidenShuffleElements() [2/3]

static bool canWidenShuffleElements ( ArrayRef< int >  Mask, const APInt &  Zeroable, bool  V2IsZero, SmallVectorImpl< int > &  WidenedMask  )

static

Definition at line 3724 of file X86ISelLowering.cpp.

References assert(), canWidenShuffleElements(), llvm::APInt::isZero(), Size, llvm::SM_SentinelUndef, and llvm::SM_SentinelZero.

canWidenShuffleElements() [3/3]

static bool canWidenShuffleElements ( ArrayRef< int >  Mask, SmallVectorImpl< int > &  WidenedMask  )

static

Helper function to test whether a shuffle mask could be simplified by widening the elements being shuffled.

Appends the mask for wider elements in WidenedMask if valid. Otherwise leaves it in an unspecified state.

NOTE: This must handle normal vector shuffle masks and target vector shuffle masks. The latter have the special property of a '-2' representing a zero-ed lane of a vector.

Definition at line 3674 of file X86ISelLowering.cpp.

References assert(), llvm::SmallVectorImpl< T >::assign(), llvm::M0(), llvm::M1(), llvm::SmallVectorBase< Size_T >::size(), Size, llvm::SM_SentinelUndef, and llvm::SM_SentinelZero.

Referenced by canWidenShuffleElements(), combineBlendOfPermutes(), combineExtractWithShuffle(), combineX86ShuffleChainWithExtract(), combineX86ShufflesRecursively(), LowerShift(), lowerShuffleAsBlendAndPermute(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), and scaleShuffleElements().

CastIntSETCCtoFP()

static std::optional< unsigned > CastIntSETCCtoFP ( MVT  VT, ISD::CondCode  CC, unsigned  NumSignificantBitsLHS, unsigned  NumSignificantBitsRHS  )

static

Definition at line 56090 of file X86ISelLowering.cpp.

References assert(), CC, llvm::MVT::getFltSemantics(), llvm::MVT::getScalarType(), llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SETEQ, llvm::ISD::SETGT, and llvm::ISD::SINT_TO_FP.

Referenced by combineConcatVectorOps().

cheapX86FSETCC_SSE()

static bool cheapX86FSETCC_SSE ( ISD::CondCode  SetCCOpcode )

static

Definition at line 23042 of file X86ISelLowering.cpp.

References llvm::ISD::SETONE, and llvm::ISD::SETUEQ.

Referenced by convertIntLogicToFPLogic(), and LowerVSETCC().

checkAndUpdateEFLAGSKill()

static bool checkAndUpdateEFLAGSKill ( MachineBasicBlock::iterator  SelectItr, MachineBasicBlock *  BB, const TargetRegisterInfo *  TRI  )

static

Definition at line 34855 of file X86ISelLowering.cpp.

References isEFLAGSLiveAfter(), and TRI.

checkBitcastSrcVectorSize()

static bool checkBitcastSrcVectorSize ( SDValue  Src, unsigned  Size, bool  AllowTruncate  )

static

Definition at line 43400 of file X86ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BUILD_VECTOR, checkBitcastSrcVectorSize(), llvm::ISD::FREEZE, llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SETCC, Size, llvm::ISD::TRUNCATE, llvm::ISD::VSELECT, and llvm::ISD::XOR.

Referenced by checkBitcastSrcVectorSize(), and combineBitcastvxi1().

checkBoolTestAndOrSetCCCombine()

static bool checkBoolTestAndOrSetCCCombine ( SDValue  Cond, X86::CondCode &  CC0, X86::CondCode &  CC1, SDValue &  Flags, bool &  isAnd  )

static

Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.

Match: (X86or (X86setcc) (X86setcc)) (X86cmp (and (X86setcc) (X86setcc)), 0)

Definition at line 46754 of file X86ISelLowering.cpp.

References llvm::ISD::AND, llvm::X86ISD::AND, llvm::X86ISD::CMP, Cond, llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::isNullConstant(), llvm::ISD::OR, llvm::X86ISD::OR, and llvm::X86ISD::SETCC.

Referenced by combineCMov().

checkBoolTestSetCCCombine()

static SDValue checkBoolTestSetCCCombine ( SDValue  Cmp, X86::CondCode &  CC  )

static

Definition at line 46636 of file X86ISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::CallingConv::C, CC, llvm::X86ISD::CMOV, llvm::X86ISD::CMP, llvm::X86::COND_B, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::X86::GetOppositeBranchCondition(), llvm::ConstantSDNode::getZExtValue(), llvm::isOneConstant(), llvm::X86ISD::RDRAND, llvm::X86ISD::RDSEED, llvm::X86ISD::SETCC, llvm::X86ISD::SETCC_CARRY, llvm::X86ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by combineSetCCEFLAGS().

checkSignTestSetCCCombine()

static SDValue checkSignTestSetCCCombine ( SDValue  Cmp, X86::CondCode &  CC, SelectionDAG &  DAG  )

static

Definition at line 46567 of file X86ISelLowering.cpp.

References llvm::ISD::AND, CC, llvm::X86ISD::CMP, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::X86::COND_NS, llvm::X86::COND_S, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::APInt::getSignMask(), llvm::SelectionDAG::getValidShiftAmount(), llvm::isNullConstant(), llvm::APInt::lshrInPlace(), llvm::X86ISD::OR, llvm::ISD::SHL, llvm::SelectionDAG::SignBitIsZero(), and llvm::ISD::SRA.

Referenced by combineSetCCEFLAGS().

clobbersFlagRegisters()

static bool clobbersFlagRegisters ( const SmallVector< StringRef, 4 > &  AsmPieces )

static

Definition at line 58303 of file X86ISelLowering.cpp.

References llvm::is_contained(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by llvm::X86TargetLowering::ExpandInlineAsm().

collectConcatOps()

static bool collectConcatOps ( SDNode *  N, SmallVectorImpl< SDValue > &  Ops, SelectionDAG &  DAG  )

static

Definition at line 4053 of file X86ISelLowering.cpp.

References llvm::SmallVectorImpl< T >::append(), assert(), collectConcatOps(), llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorBase< Size_T >::empty(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::Hi, Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::isNullConstant(), llvm::Lo, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by collectConcatOps(), combineBitcastvxi1(), combineINSERT_SUBVECTOR(), combineSetCCMOVMSK(), combineTargetShuffle(), isFreeToSplitVector(), IsNOT(), and isUpperSubvectorUndef().

combineADC()

static SDValue combineADC ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 55397 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADC, llvm::ISD::ADD, llvm::ISD::AND, combineCarryThroughADD(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::X86::COND_B, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), LHS, N, RHS, and llvm::X86ISD::SETCC_CARRY.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineAdd()

static SDValue combineAdd ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 55812 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADC, llvm::ISD::ADD, assert(), combineAddOfPMADDWD(), combineAddOrSubToADCOrSBB(), combineToHorizontalAddSub(), DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SDNode::getVTList(), getZeroVector(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::hasOneUse(), llvm::ISD::isBuildVectorAllZeros(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::X86::isZeroNode(), matchPMADDWD(), matchPMADDWD_2(), N, llvm::X86ISD::PSADBW, pushAddIntoCmovOfConsts(), Select, llvm::ISD::SIGN_EXTEND, llvm::ISD::SUB, llvm::SelectionDAG::willNotOverflowAdd(), and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineAddOfPMADDWD()

static SDValue combineAddOfPMADDWD ( SelectionDAG &  DAG, SDValue  N0, SDValue  N1, const SDLoc &  DL, EVT  VT  )

static

Definition at line 55703 of file X86ISelLowering.cpp.

References DL, llvm::APInt::getAllOnes(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSizeInBits(), llvm::APInt::getSplat(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), LHS, llvm::SelectionDAG::MaskedValueIsZero(), RHS, and llvm::X86ISD::VPMADDWD.

Referenced by combineAdd().

combineAddOrSubToADCOrSBB() [1/2]

static SDValue combineAddOrSubToADCOrSBB ( bool  IsSub, const SDLoc &  DL, EVT  VT, SDValue  X, SDValue  Y, SelectionDAG &  DAG, bool  ZeroSecondOpOnly = false  )

static

If this is an add or subtract where one operand is produced by a cmp+setcc, then try to convert it to an ADC or SBB.

This replaces TEST+SET+{ADD/SUB} with CMP+{ADC, SBB}. Also try (ADD/SUB)+(AND(SRL,1)) bit extraction pattern with BT+{ADC, SBB}.

Definition at line 50465 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADC, llvm::ISD::AND, CC, llvm::X86ISD::CMP, llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_NE, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getVTList(), llvm::SelectionDAG::getVTList(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::TargetLoweringBase::isTypeLegal(), llvm::X86::isZeroNode(), LowerAndToBT(), llvm::X86ISD::SBB, llvm::X86ISD::SETCC, llvm::X86ISD::SETCC_CARRY, llvm::ISD::SETNE, llvm::X86ISD::SUB, X, Y, and llvm::ISD::ZERO_EXTEND.

Referenced by combineAdd(), combineAddOrSubToADCOrSBB(), combineOrXorWithSETCC(), combineSub(), and combineX86AddSub().

combineAddOrSubToADCOrSBB() [2/2]

static SDValue combineAddOrSubToADCOrSBB ( SDNode *  N, const SDLoc &  DL, SelectionDAG &  DAG  )

static

If this is an add or subtract where one operand is produced by a cmp+setcc, then try to convert it to an ADC or SBB.

This replaces TEST+SET+{ADD/SUB} with CMP+{ADC, SBB}.

Definition at line 50649 of file X86ISelLowering.cpp.

References combineAddOrSubToADCOrSBB(), DL, llvm::SelectionDAG::getNegative(), N, llvm::ISD::SUB, X, and Y.

combineAnd()

static SDValue combineAnd ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 49887 of file X86ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::all_of(), llvm::ISD::AND, assert(), llvm::APInt::clearAllBits(), combineAndLoadToBZHI(), combineAndMaskToShift(), combineAndNotIntoANDNP(), combineAndOrForCcmpCtest(), combineAndShuffleNot(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBMILogicOp(), combineCompareEqual(), combineScalarAndWithMaskSetcc(), combineX86ShufflesRecursively(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::X86::COND_AE, llvm::X86::COND_B, convertIntLogicToFPLogic(), llvm::ISD::DELETED_NODE, llvm::APInt::exactLogBase2(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::X86ISD::FAND, llvm::APInt::getAllOnes(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getBitcast(), getBitWidth(), getBT(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::APInt::getHighBitsSet(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNegative(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), getSETCC(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), getTargetConstantBitsFromNode(), getTargetConstantFromNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), I, Idx, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isBitwiseNot(), llvm::isConstOrConstSplat(), llvm::isOneConstant(), llvm::SDNode::isOnlyUserOf(), llvm::APInt::isPowerOf2(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isZero(), LHS, llvm::SelectionDAG::MaskedValueIsZero(), matchScalarReduction(), llvm::X86::MaxShuffleCombineDepth, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, N, RHS, llvm::APInt::setBit(), llvm::ISD::SETEQ, llvm::ISD::SHL, llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::SmallVectorBase< Size_T >::size(), llvm::SM_SentinelUndef, llvm::SM_SentinelZero, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::APInt::uge(), and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineAndLoadToBZHI()

static SDValue combineAndLoadToBZHI ( SDNode *  Node, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 49519 of file X86ISelLowering.cpp.

References llvm::AllOnes, llvm::ISD::AND, GEP, llvm::SelectionDAG::getAllOnesConstant(), llvm::Type::getArrayElementType(), llvm::Type::getArrayNumElements(), llvm::SelectionDAG::getConstant(), getIndexFromUnindexedLoad(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::Type::getScalarSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MachineMemOperand::getValue(), llvm::SelectionDAG::getZExtOrTrunc(), hasBZHI(), llvm::Type::isIntegerTy(), N, llvm::ISD::SRL, llvm::ISD::SUB, and llvm::ISD::TRUNCATE.

Referenced by combineAnd().

combineAndMaskToShift()

static SDValue combineAndMaskToShift ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

If this is a zero/all-bits result that is bitwise-anded with a low bits mask.

(Mask == 1 for the x86 lowering of a SETCC + ZEXT), replace the 'and' with a shift-right to eliminate loading the vector constant mask value.

Definition at line 49424 of file X86ISelLowering.cpp.

References llvm::X86ISD::ANDNP, llvm::SelectionDAG::ComputeNumSignBits(), llvm::APInt::countr_one(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), getTargetVShiftByConstNode(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesOrAllOnesSplat(), llvm::isBitwiseNot(), llvm::X86::isConstantSplat(), llvm::EVT::isInteger(), llvm::APInt::isMask(), llvm::EVT::isSimple(), N, llvm::X86ISD::PCMPGT, llvm::peekThroughBitcasts(), llvm::ISD::SRA, llvm::ISD::SRL, supportedVectorShiftWithImm(), llvm::X86ISD::VSRAI, llvm::X86ISD::VSRLI, X, and Y.

Referenced by combineAnd().

combineAndNotIntoANDNP()

static SDValue combineAndNotIntoANDNP ( SDNode *  N, SelectionDAG &  DAG  )

static

Try to fold: (and (xor X, -1), Y) -> (andnp X, Y).

Definition at line 49024 of file X86ISelLowering.cpp.

References llvm::ISD::AND, llvm::X86ISD::ANDNP, assert(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), IsNOT(), N, X, and Y.

Referenced by combineAnd().

combineAndnp()

static SDValue combineAndnp ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Do target-specific dag combines on X86ISD::ANDNP nodes.

Definition at line 53483 of file X86ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::AND, llvm::ISD::BITCAST, llvm::APInt::clearAllBits(), combineX86ShufflesRecursively(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::ISD::DELETED_NODE, DL, llvm::APInt::getAllOnes(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getConstVector(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), getTargetConstantBitsFromNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), llvm::SDNode::hasOneUse(), I, llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), IsNOT(), llvm::SDValue::isUndef(), llvm::MVT::isVector(), isZero(), N, llvm::ISD::OR, llvm::peekThroughOneUseBitcasts(), llvm::X86ISD::PSHUFB, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::APInt::setBit(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifyDemandedVectorElts().

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineAndOrForCcmpCtest()

static SDValue combineAndOrForCcmpCtest ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  ST  )

static

Definition at line 49807 of file X86ISelLowering.cpp.

References llvm::X86ISD::CCMP, llvm::X86ISD::CMP, llvm::X86::COND_NP, llvm::X86::COND_P, llvm::X86ISD::CTEST, DL, llvm::SDNode::getAsAPIntVal(), llvm::X86::getCCMPCondFlagsFromCondCode(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::X86::GetOppositeBranchCondition(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getTargetConstant(), llvm::isNullConstant(), N, llvm::ISD::OR, llvm::X86ISD::SETCC, llvm::X86ISD::SUB, and std::swap().

Referenced by combineAnd(), and combineOr().

combineAndShuffleNot()

static SDValue combineAndShuffleNot ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Try to fold: and (vector_shuffle<Z,...,Z> (insert_vector_elt undef, (xor X, -1), Z), undef), Y -> andnp (vector_shuffle<Z,...,Z> (insert_vector_elt undef, X, Z), undef), Y.

Definition at line 49055 of file X86ISelLowering.cpp.

References llvm::ISD::AND, llvm::X86ISD::ANDNP, assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getBitcast(), llvm::SDValue::getConstantOperandAPInt(), llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::X86Subtarget::hasAVX(), llvm::SDValue::hasOneUse(), llvm::X86Subtarget::hasSSE2(), llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::EVT::is512BitVector(), IsNOT(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, llvm::peekThroughOneUseBitcasts(), splitVector(), llvm::X86Subtarget::useAVX512Regs(), X, and Y.

Referenced by combineAnd().

combineArithReduction()

static SDValue combineArithReduction ( SDNode *  ExtElt, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Try to convert a vector reduction sequence composed of binops and shuffles into horizontal ops.

Definition at line 45025 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::EVT::changeVectorElementType(), llvm::SelectionDAG::computeKnownBits(), llvm::ISD::CONCAT_VECTORS, DL, extract128BitVector(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::X86ISD::FHADD, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::KnownBits::getMaxValue(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), getUnpackh(), getUnpackl(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), getZeroVector(), llvm::X86ISD::HADD, llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE3(), llvm::X86Subtarget::hasSSE41(), llvm::X86Subtarget::hasSSSE3(), llvm::Hi, llvm::ISD::INSERT_VECTOR_ELT, llvm::isNullConstant(), llvm::isPowerOf2_32(), llvm::Lo, llvm::Log2_32(), llvm::SelectionDAG::matchBinOpReduction(), llvm::ISD::MUL, llvm::X86ISD::PACKUS, llvm::X86ISD::PSADBW, shouldUseHorizontalOp(), SplitOpsAndApply(), splitVector(), llvm::ISD::TRUNCATE, llvm::APInt::ule(), and llvm::ISD::ZERO_EXTEND.

Referenced by combineExtractVectorElt().

combineAVG()

static SDValue combineAVG ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 53181 of file X86ISelLowering.cpp.

References llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::APInt::getSignMask(), llvm::EVT::isVector(), N, and llvm::ISD::XOR.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineBasicSADPattern()

static SDValue combineBasicSADPattern ( SDNode *  Extract, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 44600 of file X86ISelLowering.cpp.

References llvm::ISD::ABS, llvm::ISD::ADD, llvm::ISD::ANY_EXTEND, createPSADBW(), detectZextAbsDiff(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::X86Subtarget::hasSSE2(), llvm::isPowerOf2_32(), llvm::Log2_32(), llvm::SelectionDAG::matchBinOpReduction(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by combineExtractVectorElt().

combineBEXTR()

static SDValue combineBEXTR ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 53205 of file X86ISelLowering.cpp.

References llvm::APInt::getAllOnes(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), N, and llvm::TargetLowering::SimplifyDemandedBits().

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineBitcast()

static SDValue combineBitcast ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 43898 of file X86ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::EVT::changeVectorElementTypeToInteger(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineCastedMaskArithmetic(), combinevXi1ConstantToInteger(), llvm::ISD::CONCAT_VECTORS, llvm::countl_zero(), createMMXBuildVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, F64, llvm::X86ISD::FAND, llvm::X86ISD::FOR, llvm::ISD::FP_TO_SINT, llvm::X86ISD::FXOR, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::MVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), getTargetConstantBitsFromNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::X86Subtarget::hasAVX512(), llvm::SDValue::hasOneUse(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::APFloatBase::IEEEdouble(), llvm::EVT::is128BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::isNullConstantOrUndef(), llvm::isPowerOf2_32(), llvm::EVT::isScalarInteger(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::X86ISD::MMX_MOVW2D, llvm::X86ISD::MOVDQ2Q, llvm::X86ISD::MOVMSK, N, llvm::SDNode::ops(), llvm::ISD::OR, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorImpl< T >::resize(), llvm::ISD::SETLT, llvm::ISD::TRUNCATE, llvm::X86ISD::VBROADCAST_LOAD, and llvm::ISD::XOR.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineBitcastToBoolVector()

static SDValue combineBitcastToBoolVector ( EVT  VT, SDValue  V, const SDLoc &  DL, SelectionDAG &  DAG, const X86Subtarget &  Subtarget, unsigned  Depth = 0  )

static

Definition at line 43809 of file X86ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::CallingConv::C, combineBitcastToBoolVector(), llvm::ISD::Constant, llvm::Depth, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNodeIfExists(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::isFloatingPoint(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::X86ISD::KSHIFTL, llvm::SelectionDAG::MaxRecursionDepth, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::TRUNCATE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

Referenced by combineBitcast(), and combineBitcastToBoolVector().

combineBitcastvxi1()

static SDValue combineBitcastvxi1 ( SelectionDAG &  DAG, EVT  VT, SDValue  Src, const SDLoc &  DL, const X86Subtarget &  Subtarget  )

static

Definition at line 43507 of file X86ISelLowering.cpp.

References adjustBitcastSrcVectorSSE1(), llvm::all_of(), llvm::ISD::ANY_EXTEND, llvm::SmallVectorTemplateCommon< T, typename >::begin(), checkBitcastSrcVectorSize(), collectConcatOps(), combineBitcastvxi1(), DL, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), getPMOVMSKB(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX2(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isSimple(), llvm::X86ISD::MOVMSK, llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SIGN_EXTEND, signExtendBitcastSrcVector(), llvm::MVT::SimpleTy, llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::TRUNCATE, and widenSubVector().

Referenced by combineAnd(), combineBitcast(), combineBitcastvxi1(), combineExtractVectorElt(), combineOr(), and combinePredicateReduction().

combineBitOpWithMOVMSK()

static SDValue combineBitOpWithMOVMSK ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 49303 of file X86ISelLowering.cpp.

References llvm::ISD::AND, assert(), convertIntLogicToFPLogicOpcode(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isFloatingPoint(), llvm::X86ISD::MOVMSK, N, llvm::ISD::OR, and llvm::ISD::XOR.

Referenced by combineAnd(), combineOr(), and combineXor().

combineBitOpWithPACK()

static SDValue combineBitOpWithPACK ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 49381 of file X86ISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::SelectionDAG::ComputeNumSignBits(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SDValue::hasOneUse(), LHS, N, llvm::ISD::OR, llvm::X86ISD::PACKSS, llvm::peekThroughOneUseBitcasts(), RHS, and llvm::ISD::XOR.

Referenced by combineAnd(), combineOr(), and combineXor().

combineBitOpWithShift()

static SDValue combineBitOpWithShift ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 49338 of file X86ISelLowering.cpp.

References llvm::ISD::AND, assert(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), N, llvm::ISD::OR, llvm::peekThroughOneUseBitcasts(), llvm::X86ISD::VSHLI, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRLI, and llvm::ISD::XOR.

Referenced by combineAnd(), combineOr(), and combineXor().

combineBITREVERSE()

static SDValue combineBITREVERSE ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 53153 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getBitcast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::SDValue::hasOneUse(), llvm::X86Subtarget::hasSSSE3(), I, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), and N.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineBlendOfPermutes()

static SDValue combineBlendOfPermutes ( MVT  VT, SDValue  N0, SDValue  N1, ArrayRef< int >  BlendMask, const APInt &  DemandedElts, SelectionDAG &  DAG, const X86Subtarget &  Subtarget, const SDLoc &  DL  )

static

Definition at line 40402 of file X86ISelLowering.cpp.

References assert(), canScaleShuffleElements(), canWidenShuffleElements(), DL, llvm::SelectionDAG::getBitcast(), llvm::MVT::getScalarSizeInBits(), llvm::getShuffleDemandedElts(), getTargetShuffleMask(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::X86Subtarget::hasAVX2(), llvm::SDValue::hasOneUse(), I, llvm::APInt::intersects(), is128BitLaneRepeatedShuffleMask(), llvm::MVT::is256BitVector(), isBlendOrUndef(), isLaneCrossingShuffleMask(), isUndefOrEqual(), isUndefOrInRange(), llvm::APInt::isZero(), llvm::peekThroughOneUseBitcasts(), scaleShuffleElements(), and llvm::SM_SentinelUndef.

Referenced by llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().

combineBMILogicOp()

static SDValue combineBMILogicOp ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 49726 of file X86ISelLowering.cpp.

References llvm::ISD::AND, assert(), getBMIMatchingOp(), llvm::EVT::isScalarInteger(), N, and llvm::ISD::XOR.

Referenced by combineAnd(), and combineXor().

combineBrCond()

static SDValue combineBrCond ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Optimize branch condition evaluation.

Definition at line 54829 of file X86ISelLowering.cpp.

References llvm::X86ISD::BRCOND, CC, combineSetCCEFLAGS(), Cond, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), and N.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineBROADCAST_LOAD()

static SDValue combineBROADCAST_LOAD ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 57661 of file X86ISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), extractSubVector(), llvm::SelectionDAG::getBitcast(), llvm::EVT::getFixedSizeInBits(), llvm::EVT::getSizeInBits(), N, Ptr, llvm::X86ISD::SUBV_BROADCAST_LOAD, and llvm::X86ISD::VBROADCAST_LOAD.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineBT()

static SDValue combineBT ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 53616 of file X86ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::BitWidth, llvm::ISD::DELETED_NODE, llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueSizeInBits(), llvm::Log2_32(), N, and llvm::TargetLowering::SimplifyDemandedBits().

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineCarryThroughADD()

static SDValue combineCarryThroughADD ( SDValue  EFLAGS, SelectionDAG &  DAG  )

static

Definition at line 46795 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADD, llvm::ISD::AND, llvm::X86::COND_A, llvm::X86::COND_B, llvm::X86::COND_E, DL, getBT(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SDValue::getValueType(), llvm::SDNode::getVTList(), llvm::SDNode::hasOneUse(), llvm::isAllOnesConstant(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::X86ISD::SETCC, llvm::X86ISD::SETCC_CARRY, llvm::ISD::SRL, llvm::X86ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

combineCastedMaskArithmetic()

static SDValue combineCastedMaskArithmetic ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 43673 of file X86ISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::ISD::BITCAST, combinevXi1ConstantToInteger(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::X86Subtarget::hasAVX512(), llvm::Value::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::EVT::isScalarInteger(), llvm::EVT::isVector(), LHS, N, llvm::ISD::OR, RHS, and llvm::ISD::XOR.

Referenced by combineBitcast().

combineCMov()

static SDValue combineCMov ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL].

Definition at line 47276 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADC, llvm::Add, llvm::ISD::ADD, assert(), llvm::X86Subtarget::canUseCMOV(), CC, checkBoolTestAndOrSetCCCombine(), llvm::X86ISD::CMOV, llvm::X86ISD::CMP, combineSetCCEFLAGS(), Cond, llvm::X86::COND_AE, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, DL, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::X86::GetOppositeBranchCondition(), getSETCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::APInt::getZExtValue(), hasFPCMov(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::ISD::MUL, N, llvm::ISD::SHL, llvm::ISD::SUB, llvm::X86ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::APInt::ult(), and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineCMP()

static SDValue combineCMP ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 55185 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::X86ISD::ADD, llvm::ISD::AND, llvm::X86ISD::AND, llvm::BitWidth, llvm::X86ISD::CMP, combineX86SubCmpForFlags(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBitcast(), llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::APInt::getHighBitsSet(), llvm::EVT::getIntegerVT(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isTypeLegal(), llvm::X86ISD::KSHIFTR, llvm::SelectionDAG::MaskedValueIsZero(), N, needCarryOrOverflowFlag(), onlyZeroFlagUsed(), llvm::ISD::OR, llvm::X86ISD::OR, llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::SUB, llvm::X86ISD::SUB, llvm::ISD::TRUNCATE, llvm::APInt::ult(), widenMaskVector(), llvm::ISD::XOR, llvm::X86ISD::XOR, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineCommutableSHUFP()

static SDValue combineCommutableSHUFP ( SDValue  N, MVT  VT, const SDLoc &  DL, SelectionDAG &  DAG  )

static

Definition at line 40347 of file X86ISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getTargetConstant(), llvm::X86::mayFoldLoad(), N, llvm::peekThroughOneUseBitcasts(), llvm::X86ISD::SHUFP, and llvm::X86ISD::VPERMILPI.

Referenced by combineTargetShuffle().

combineCompareEqual()

static SDValue combineCompareEqual ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Recognize the distinctive (AND (setcc ...) (setcc ..)) where both setccs reference the same FP CMP, and rewrite for CMPEQSS and friends.

Likewise for OR -> CMPNEQSS.

Definition at line 48917 of file X86ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::X86::COND_NP, llvm::X86::COND_P, llvm::ISD::CopyToReg, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::X86ISD::FCMP, llvm::X86ISD::FSETCC, llvm::X86ISD::FSETCCM, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasSSE2(), llvm::ISD::INSERT_SUBVECTOR, isAndOrOfSetCCs(), N, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by combineAnd(), and combineOr().

combineCONCAT_VECTORS()

static SDValue combineCONCAT_VECTORS ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 56782 of file X86ISelLowering.cpp.

References llvm::CallingConv::C, combineConcatVectorOps(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::APInt::getZero(), llvm::X86Subtarget::hasAVX(), I, llvm::TargetLoweringBase::isTypeLegal(), N, llvm::peekThroughBitcasts(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineConcatVectorOps()

static SDValue combineConcatVectorOps ( const SDLoc &  DL, MVT  VT, ArrayRef< SDValue >  Ops, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Helper that combines an array of subvector ops as if they were the operands of a ISD::CONCAT_VECTORS node, but may have come from another source (e.g.

ISD::INSERT_SUBVECTOR). The ops are assumed to be of the same type.

Definition at line 56112 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::all_equal(), llvm::all_of(), llvm::X86TargetLowering::allowsMemoryAccess(), llvm::ISD::AND, llvm::X86ISD::ANDNP, llvm::SmallVectorImpl< T >::append(), assert(), llvm::X86ISD::BLENDI, llvm::X86ISD::BLENDV, llvm::CallingConv::C, CastIntSETCCtoFP(), llvm::EVT::changeVectorElementType(), llvm::X86ISD::CMPP, llvm::SelectionDAG::ComputeMaxSignificantBits(), llvm::ISD::CONCAT_VECTORS, concatSubVectors(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, DL, EltsFromConsecutiveLoads(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, extractSubVector(), llvm::ISD::FADD, llvm::CallingConv::Fast, llvm::ISD::FDIV, llvm::X86ISD::FHADD, llvm::X86ISD::FHSUB, llvm::ISD::FMUL, llvm::ISD::FSUB, llvm::SelectionDAG::getBitcast(), llvm::APInt::getBitWidth(), getBROADCAST_LOAD(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getConstantPool(), llvm::MachinePointerInfo::getConstantPool(), getConstantVector(), getConstVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getEntryNode(), llvm::MVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86Subtarget::getPreferVectorWidth(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::MVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getSelect(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), getTargetConstantBitsFromNode(), getTargetConstantFromNode(), llvm::X86Subtarget::getTargetLowering(), llvm::SelectionDAG::getTargetLoweringInfo(), getTargetShuffleMask(), llvm::SelectionDAG::getUNDEF(), getV4X86ShuffleImm8ForMask(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::APInt::getZero(), getZeroVector(), llvm::X86ISD::GF2P8AFFINEQB, llvm::X86ISD::HADD, llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX2(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasInt256(), llvm::X86ISD::HSUB, I, Idx, llvm::APInt::insertBits(), llvm::EVT::is256BitVector(), llvm::MVT::is256BitVector(), llvm::EVT::is512BitVector(), llvm::MVT::is512BitVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::EVT::isFloatingPoint(), llvm::MVT::isFloatingPoint(), llvm::ISD::isNormalLoad(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), LHS, llvm::X86::mayFoldLoad(), llvm::X86::mayFoldLoadIntoBroadcastFromMem(), llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::ISD::MUL, llvm::none_of(), llvm::ISD::OR, llvm::X86ISD::PACKSS, llvm::X86ISD::PACKUS, llvm::X86ISD::PALIGNR, llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPGT, llvm::peekThroughBitcasts(), llvm::X86ISD::PSADBW, llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), RHS, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SETEQ, llvm::ISD::SETGT, llvm::ISD::SETOEQ, llvm::ISD::SETOGT, llvm::X86ISD::SHUF128, llvm::X86ISD::SHUFP, llvm::ArrayRef< T >::size(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::SUB, llvm::X86ISD::SUBV_BROADCAST_LOAD, translateX86FSETCC(), llvm::ISD::TRUNCATE, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86Subtarget::useAVX512Regs(), llvm::X86Subtarget::useBWIRegs(), llvm::X86ISD::VBROADCAST, llvm::X86ISD::VBROADCAST_LOAD, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMI, llvm::X86ISD::VPERMILPI, llvm::X86ISD::VPERMV, llvm::X86ISD::VPERMV3, llvm::X86ISD::VPMADDUBSW, llvm::X86ISD::VPMADDWD, llvm::X86ISD::VROTLI, llvm::X86ISD::VROTRI, llvm::ISD::VSELECT, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLI, widenSubVector(), and llvm::ISD::XOR.

Referenced by combineCONCAT_VECTORS(), and combineINSERT_SUBVECTOR().

combineConstantPoolLoads()

static SDValue combineConstantPoolLoads ( SDNode *  N, const SDLoc &  dl, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 51159 of file X86ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::CombineTo(), extractSubVector(), llvm::SelectionDAG::getBitcast(), llvm::APInt::getBitWidth(), llvm::EVT::getFixedSizeInBits(), llvm::Type::getPrimitiveSizeInBits(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), getTargetConstantBitsFromNode(), getTargetConstantFromBasePtr(), llvm::Value::getType(), llvm::SDNode::getValueType(), llvm::X86Subtarget::hasAVX(), I, llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::ISD::isNormalLoad(), N, llvm::ISD::NON_EXTLOAD, Ptr, llvm::X86ISD::SUBV_BROADCAST_LOAD, llvm::SDNode::uses(), and llvm::X86ISD::VBROADCAST_LOAD.

Referenced by combineLoad().

combineCVTP2I_CVTTP2I()

static SDValue combineCVTP2I_CVTTP2I ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 53446 of file X86ISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SelectionDAG::getBitcast(), llvm::MVT::getFloatingPointVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::is128BitVector(), llvm::ISD::isNormalLoad(), N, narrowLoadToVZLoad(), llvm::TargetLowering::DAGCombinerInfo::recursivelyDeleteUnusedNodes(), and llvm::SelectionDAG::ReplaceAllUsesOfValueWith().

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineCVTPH2PS()

static SDValue combineCVTPH2PS ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 53632 of file X86ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::ISD::DELETED_NODE, llvm::SelectionDAG::getBitcast(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::ISD::isNormalLoad(), N, narrowLoadToVZLoad(), llvm::TargetLowering::DAGCombinerInfo::recursivelyDeleteUnusedNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::TargetLowering::SimplifyDemandedVectorElts(), and llvm::X86ISD::STRICT_CVTPH2PS.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineEXTEND_VECTOR_INREG()

static SDValue combineEXTEND_VECTOR_INREG ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 57456 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::EVT::changeVectorElementType(), combineX86ShufflesRecursively(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getOpcode_EXTEND(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorNumElements(), llvm::X86Subtarget::hasSSE41(), I, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::ISD::ZEXTLOAD.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineEXTRACT_SUBVECTOR()

static SDValue combineEXTRACT_SUBVECTOR ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 57029 of file X86ISelLowering.cpp.

References llvm::ISD::AND, llvm::X86ISD::BLENDI, llvm::ISD::BUILD_VECTOR, llvm::X86ISD::CMPP, Concat, llvm::ISD::CONCAT_VECTORS, llvm::X86ISD::CVTSI2P, llvm::X86ISD::CVTUI2P, DL, llvm::ISD::EXTRACT_SUBVECTOR, extractSubVector(), llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), getOnesVector(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getOpcode_EXTEND_VECTOR_INREG(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), getTargetShuffleInputs(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MVT::getVectorNumElements(), getZeroVector(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX2(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::is256BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isBitwiseNot(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isExtOpcode(), llvm::ISD::isExtVecInRegOpcode(), llvm::SelectionDAG::isSplatValue(), llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::LOAD, llvm::X86ISD::MOVDDUP, N, narrowExtractedVectorSelect(), llvm::SDNode::ops(), llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPGT, llvm::peekThroughBitcasts(), llvm::peekThroughOneUseBitcasts(), scaleShuffleElements(), llvm::ISD::SINT_TO_FP, llvm::SM_SentinelUndef, llvm::SM_SentinelZero, splitVectorIntBinary(), llvm::X86ISD::SUBV_BROADCAST_LOAD, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VBROADCAST, llvm::X86ISD::VBROADCAST_LOAD, llvm::X86ISD::VFPEXT, llvm::ISD::VSELECT, llvm::X86ISD::VSHLI, and llvm::X86ISD::VSRLI.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineExtractFromVectorLoad()

static SDValue combineExtractFromVectorLoad ( SDNode *  N, EVT  VecVT, SDValue  SrcVec, uint64_t  Idx, const SDLoc &  dl, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 44683 of file X86ISelLowering.cpp.

References llvm::any_of(), assert(), llvm::commonAlignment(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getLoad(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueSizeInBits(), llvm::TargetLowering::getVectorElementPointer(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::MachinePointerInfo::getWithOffset(), Idx, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::EVT::isInteger(), llvm::ISD::isNormalLoad(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), and N.

Referenced by combineExtractVectorElt(), and combineExtractWithShuffle().

combineExtractVectorElt()

static SDValue combineExtractVectorElt ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Detect vector gather/scatter index generation and convert it from being a bunch of shuffles and extracts into a somewhat faster sequence.

For i686, the best sequence is apparently storing the value and loading scalars back, while for x64 we should use 64-bit extracts and shifts.

Definition at line 45218 of file X86ISelLowering.cpp.

References llvm::all_of(), llvm::ISD::AND, assert(), llvm::ISD::BITCAST, combineArithReduction(), combineBasicSADPattern(), combineBitcastvxi1(), combineExtractFromVectorLoad(), combineExtractWithShuffle(), combineMinMaxReduction(), combinePredicateReduction(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), combineVPDPBUSDPattern(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::getAllOnes(), llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSetCC(), getTargetConstantBitsFromNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDValue::hasOneUse(), Idx, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::TargetLoweringBase::isTypeLegal(), llvm::X86ISD::MMX_MOVD2W, N, llvm::peekThroughBitcasts(), llvm::X86ISD::PINSRB, llvm::X86ISD::PINSRW, llvm::SmallVectorTemplateBase< T, bool >::push_back(), scalarizeExtEltFP(), llvm::ISD::SETEQ, llvm::ISD::SHL, llvm::TargetLowering::SimplifyDemandedBits(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::TRUNCATE, and llvm::SDNode::uses().

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineExtractWithShuffle()

static SDValue combineExtractWithShuffle ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 44720 of file X86ISelLowering.cpp.

References llvm::any_of(), assert(), canWidenShuffleElements(), combineExtractFromVectorLoad(), extract128BitVector(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), getTargetShuffleInputs(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), llvm::Hi, Idx, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalarInteger(), isUndefOrZeroInRange(), llvm::Lo, N, llvm::narrowShuffleMaskElts(), llvm::Offset, llvm::peekThroughBitcasts(), llvm::X86ISD::PEXTRB, llvm::X86ISD::PEXTRW, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SCALAR_TO_VECTOR, llvm::SM_SentinelUndef, llvm::SM_SentinelZero, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::APInt::uge(), llvm::APInt::ult(), llvm::APInt::urem(), llvm::X86ISD::VBROADCAST, and llvm::X86ISD::VBROADCAST_LOAD.

Referenced by combineExtractVectorElt().

combineExtSetcc()

static SDValue combineExtSetcc ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 53903 of file X86ISelLowering.cpp.

References CC, llvm::EVT::changeVectorElementTypeToInteger(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::X86Subtarget::hasAVX512(), llvm::ISD::isUnsignedIntSetCC(), llvm::EVT::isVector(), N, llvm::ISD::SETCC, Size, llvm::X86Subtarget::useAVX512Regs(), and llvm::ISD::ZERO_EXTEND.

Referenced by combineSext(), and combineZext().

combineFaddCFmul()

static SDValue combineFaddCFmul ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 52232 of file X86ISelLowering.cpp.

References llvm::TargetOptions::AllowFPOpFusion, llvm::ISD::BITCAST, llvm::SelectionDAG::computeKnownBits(), llvm::ISD::FADD, llvm::FPOpFusion::Fast, llvm::SelectionDAG::getBitcast(), llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTarget(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::ISD::isBuildVectorAllZeros(), LHS, N, llvm::TargetOptions::NoSignedZerosFPMath, llvm::TargetMachine::Options, RHS, llvm::X86ISD::VFCMADDC, llvm::X86ISD::VFCMULC, llvm::X86ISD::VFMADDC, and llvm::X86ISD::VFMULC.

Referenced by combineFaddFsub().

combineFaddFsub()

static SDValue combineFaddFsub ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Do target-specific dag combines on floating-point adds/subs.

Definition at line 52307 of file X86ISelLowering.cpp.

References combineFaddCFmul(), combineToHorizontalAddSub(), and N.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFAnd()

static SDValue combineFAnd ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Do target-specific dag combines on X86ISD::FAND nodes.

Definition at line 53275 of file X86ISelLowering.cpp.

References combineFAndFNotToFAndn(), getNullFPConstForNullVal(), lowerX86FPLogicOp(), and N.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFAndFNotToFAndn()

static SDValue combineFAndFNotToFAndn ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 53243 of file X86ISelLowering.cpp.

References llvm::CallingConv::C, DL, llvm::X86ISD::FANDN, llvm::X86ISD::FXOR, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::ISD::isBuildVectorAllOnes(), and N.

Referenced by combineFAnd().

combineFAndn()

static SDValue combineFAndn ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Do target-specific dag combines on X86ISD::FANDN nodes.

Definition at line 53292 of file X86ISelLowering.cpp.

References getNullFPConstForNullVal(), isNullFPScalarOrVectorConst(), lowerX86FPLogicOp(), and N.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFMA()

static SDValue combineFMA ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 54051 of file X86ISelLowering.cpp.

References A, assert(), B, llvm::CallingConv::C, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::TargetLowering::getCheaperNegatedExpression(), llvm::MachineFunction::getFunction(), getInvertedVectorForFMA(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::X86Subtarget::hasAnyFMA(), llvm::Function::hasOptSize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::isNullConstant(), llvm::TargetLoweringBase::isOperationExpand(), llvm::TargetLoweringBase::isTypeLegal(), N, and negateFMAOpcode().

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFMADDSUB()

static SDValue combineFMADDSUB ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 54139 of file X86ISelLowering.cpp.

References llvm::TargetLowering::getCheaperNegatedExpression(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::Function::hasOptSize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, and negateFMAOpcode().

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFMinFMax()

static SDValue combineFMinFMax ( SDNode *  N, SelectionDAG &  DAG  )

static

Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.

Definition at line 53326 of file X86ISelLowering.cpp.

References assert(), llvm::X86ISD::FMAX, llvm::X86ISD::FMAXC, llvm::X86ISD::FMIN, llvm::X86ISD::FMINC, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTarget(), llvm_unreachable, N, llvm::TargetOptions::NoNaNsFPMath, llvm::TargetOptions::NoSignedZerosFPMath, and llvm::TargetMachine::Options.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFMinNumFMaxNum()

static SDValue combineFMinNumFMaxNum ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 53347 of file X86ISelLowering.cpp.

References DL, llvm::X86ISD::FMAX, llvm::ISD::FMAXNUM, llvm::X86ISD::FMIN, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::Function::hasMinSize(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::SelectionDAG::isKnownNeverNaN(), isSoftF16(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, llvm::TargetOptions::NoNaNsFPMath, llvm::TargetMachine::Options, and llvm::ISD::SETUO.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFMulcFCMulc()

static SDValue combineFMulcFCMulc ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 52191 of file X86ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::getBitcast(), llvm::KnownBits::getBitWidth(), llvm::KnownBits::getConstant(), llvm::SelectionDAG::getNode(), llvm::Value::hasOneUse(), llvm::KnownBits::isConstant(), LHS, N, RHS, std::swap(), llvm::X86ISD::VFCMULC, llvm::X86ISD::VFMULC, and llvm::ISD::XOR.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFneg()

static SDValue combineFneg ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Do target-specific dag combines on floating point negations.

Definition at line 52858 of file X86ISelLowering.cpp.

References DL, llvm::ISD::FMUL, llvm::X86ISD::FNMSUB, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstantFP(), llvm::SDNode::getFlags(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLowering::getNegatedExpression(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::X86Subtarget::hasAnyFMA(), llvm::SDNodeFlags::hasNoSignedZeros(), llvm::Function::hasOptSize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isFNEG(), llvm::TargetLoweringBase::isTypeLegal(), and N.

Referenced by combineFOr(), combineXor(), and llvm::X86TargetLowering::PerformDAGCombine().

combineFOr()

static SDValue combineFOr ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.

Definition at line 53306 of file X86ISelLowering.cpp.

References assert(), combineFneg(), llvm::X86ISD::FOR, llvm::X86ISD::FXOR, isNullFPScalarOrVectorConst(), lowerX86FPLogicOp(), and N.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFP16_TO_FP()

static SDValue combineFP16_TO_FP ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 57542 of file X86ISelLowering.cpp.

References llvm::X86ISD::CVTPH2PS, llvm::X86ISD::CVTPS2PH, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_TO_FP16, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::ISD::SCALAR_TO_VECTOR.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFP_EXTEND()

static SDValue combineFP_EXTEND ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const X86Subtarget &  Subtarget  )

static

Definition at line 57564 of file X86ISelLowering.cpp.

References assert(), llvm::EVT::changeTypeToInteger(), llvm::EVT::changeVectorElementType(), llvm::EVT::changeVectorElementTypeToInteger(), llvm::ISD::CONCAT_VECTORS, llvm::X86ISD::CVTPH2PS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isPowerOf2_32(), llvm::EVT::isVector(), N, llvm::ISD::SHL, llvm::X86ISD::STRICT_CVTPH2PS, llvm::ISD::STRICT_FP_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineFP_ROUND()

static SDValue combineFP_ROUND ( SDNode *  N, SelectionDAG &  DAG, const X86Subtarget &  Subtarget  )

static

Definition at line 57697 of file X86ISelLowering.cpp.

References assert(), llvm::EVT::changeVectorElementTypeToInteger(), llvm::ISD::CONCAT_VECTORS, llvm::X86ISD::CVTPS2PH, llvm::X86ISD::CVTSI2P, llvm::X86ISD::CVTUI2P, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), llvm::SDNode::isStrictFPOpcode(), llvm::EVT::isVector(), N, llvm::ISD::SINT_TO_FP, llvm::X86ISD::STRICT_CVTPS2PH, llvm::X86ISD::STRICT_CVTSI2P, llvm::X86ISD::STRICT_CVTUI2P, and llvm::ISD::STRICT_SINT_TO_FP.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineGatherScatter()

static SDValue combineGatherScatter ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 54705 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::sampleprof::Base, llvm::CallingConv::C, llvm::EVT::changeVectorElementType(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::ISD::DELETED_NODE, DL, llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantSplatNode(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::APInt::getSignMask(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::BuildVectorSDNode::isConstant(), llvm::isOneConstant(), N, llvm::BitVector::none(), rebuildGatherScatter(), llvm::ISD::SIGN_EXTEND, llvm::TargetLowering::SimplifyDemandedBits(), llvm::Splat, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::X86TargetLowering::PerformDAGCombine().

combineHorizOpWithShuffle()

static SDValue combineHorizOpWithShuffle ( SDNode *  N, SelectionDAG &  DAG,